CN215896392U - Display substrate and display panel - Google Patents

Abstract

The application provides a display substrate, display panel relates to and shows technical field, and this display panel can be under the prerequisite of guaranteeing the low-power consumption, promotes resolution ratio by a wide margin. The display substrate comprises a plurality of sub-pixels; the sub-pixel comprises a storage capacitor, a polysilicon transistor and at least one oxide transistor; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, and the first electrode is arranged on one side of the second electrode, which is far away from the substrate; the second electrode and the grid electrode of the polycrystalline silicon transistor are arranged on the same layer; the oxide transistor is arranged on one side of the first electrode far away from the substrate, and the first electrode and the active layer of the at least one oxide transistor at least partially overlap along the direction vertical to the substrate; the first electrode is configured to be connected with a power supply signal and also used as a bottom gate of the overlapping oxide transistor, and the oxide transistor at least partially overlapped with the first electrode along the direction vertical to the substrate is the overlapping oxide transistor. The application is suitable for manufacturing the display substrate.

Description

Display substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to a display substrate and a display panel.

Background

An OLED (Organic Light-emitting Diode) display gradually becomes the mainstream of the display field by virtue of excellent performances such as low power consumption, high color saturation, wide viewing angle, thin thickness and flexibility, and can be widely applied to terminal products such as smart phones, tablet computers and televisions.

Currently, wearable devices (such as smart watches) generally adopt an LTPO backplane driving circuit, i.e. a backplane structure combining an LTPS-TFT (low temperature polysilicon thin film transistor) and an oxide-TFT (oxide thin film transistor). This structure employs LTPS-TFT as a driving TFT of an OLED element and oxide-TFT as a switching TFT. The characteristics of high response speed and large starting current of the LTPS-TFT are utilized to provide a current source for OLED display; meanwhile, the characteristic of low electric leakage of the oxide-TFT is utilized, and the power consumption of the back plate is reduced. This low power design is more suitable for wearable devices.

However, in the LTPO technique, the oxide-TFT is large in size; meanwhile, the oxide-TFT is an NMOS transistor, the LTPS-TFT is a PMOS transistor, and the drive voltages of the two transistors are different, so that the wiring of the LTPO backboard is tense, and finally, a display panel with higher resolution is difficult to form.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a display substrate and a display panel, and the display panel can greatly improve the resolution ratio on the premise of ensuring low power consumption.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, a display substrate is provided, which includes a substrate and a plurality of sub-pixels arranged in an array on one side of the substrate;

the sub-pixel comprises a storage capacitor, a polysilicon transistor and at least one oxide transistor; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, and the first electrode is arranged on one side of the second electrode far away from the substrate;

the second electrode and the grid electrode of the polycrystalline silicon transistor are arranged on the same layer; the oxide transistor is arranged on one side of the first electrode far away from the substrate, and the first electrode at least partially overlaps with the active layer of at least one oxide transistor along the direction vertical to the substrate;

the first electrode is configured to be connected with a power supply signal and also used as a bottom gate of an overlapping oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode in a direction perpendicular to the substrate is the overlapping oxide transistor.

Optionally, an orthographic projection of an active layer of at least one of the oxide transistors on the substrate is located within an orthographic projection of the first electrode on the substrate.

Optionally, an orthographic projection of the second electrode on the substrate is located within an orthographic projection of the first electrode on the substrate.

Optionally, the display substrate further includes a power line, and the first electrode is electrically connected to the power line.

Optionally, the power line is disposed in the same layer as the first and second poles of the overlapping oxide transistor.

Optionally, the polysilicon transistor is a top gate polysilicon transistor, and an active layer of the polysilicon transistor is disposed between the substrate and a gate of the polysilicon transistor.

Optionally, the first pole and the second pole of the polysilicon transistor are disposed in the same layer as the first pole and the second pole of the overlapping oxide transistor.

Optionally, the sub-pixel further comprises an anode, and one of the first and second poles of the polysilicon transistor is electrically connected to the anode.

Optionally, the polysilicon transistor is a P-type transistor, and the oxide transistor is an N-type transistor.

Optionally, the sub-pixel further includes a single-gate oxide transistor, and an active layer of the single-gate oxide transistor does not overlap with the first electrode in a direction perpendicular to the substrate.

Optionally, the sub-pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the first transistor and the second transistor are the oxide transistors, and the third transistor is the polysilicon transistor;

the display substrate further comprises a power line, a light-emitting control signal line, a data signal line, a reset control signal line and an initial signal line; the sub-pixels further comprise light emitting diodes;

a gate of the first transistor is electrically connected to the reset control signal line, a second electrode of the first transistor is electrically connected to an initial signal line, a first electrode of the first transistor and a first electrode of the second transistor are electrically connected to a first node, a gate of the third transistor and the second electrode of the storage capacitor are electrically connected to the first node, and the first electrode of the storage capacitor is electrically connected to the power supply line;

a gate of the second transistor is electrically connected to the reset control signal line, a second pole of the second transistor is electrically connected to a third node, a first pole of the third transistor is electrically connected to the second node, a second pole of the third transistor is electrically connected to the third node, a first pole of the fourth transistor is electrically connected to the second node, a second pole of the fourth transistor is electrically connected to the data signal line, a gate of the fourth transistor is electrically connected to the reset control signal line, a second pole of the fifth transistor is electrically connected to the second node, a first pole of the fifth transistor is electrically connected to the power line, and a gate of the fifth transistor is electrically connected to the emission control signal line;

a gate of the sixth transistor is electrically connected to the light emission control signal line, a first electrode of the sixth transistor is electrically connected to the third node, a second electrode of the sixth transistor is electrically connected to a fourth node, a gate of the seventh transistor is electrically connected to the reset control signal line, a first electrode of the seventh transistor is electrically connected to the fourth node, a second electrode of the seventh transistor is electrically connected to the initial signal line, an anode of the light emitting diode is electrically connected to the fourth node, and a cathode of the light emitting diode is grounded;

wherein orthographic projections of the active layers of the first transistor and the second transistor on the substrate are both located within the orthographic projection of the first electrode on the substrate, and orthographic projections of the active layers of the rest transistors on the substrate are not overlapped with the orthographic projection of the first electrode on the substrate.

In another aspect, a display panel is provided, which includes the display substrate.

The embodiment of the application provides a display substrate and a display panel, wherein the display substrate comprises a substrate and a plurality of sub-pixels which are arranged on one side of the substrate in an array manner; the sub-pixel comprises a storage capacitor, a polysilicon transistor and at least one oxide transistor; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, and the first electrode is arranged on one side of the second electrode far away from the substrate; the second electrode and the grid electrode of the polycrystalline silicon transistor are arranged on the same layer; the oxide transistor is arranged on one side of the first electrode far away from the substrate, and the first electrode at least partially overlaps with the active layer of at least one oxide transistor along the direction vertical to the substrate; the first electrode is configured to be connected with a power supply signal and also used as a bottom gate of an overlapping oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode in a direction perpendicular to the substrate is the overlapping oxide transistor.

In the display substrate provided by the application, the first electrode and the active layer of at least one oxide transistor are at least partially overlapped along the direction perpendicular to the substrate, and the first electrode is also used as the bottom gate of the overlapping oxide transistor, so that the additional arrangement of the bottom gate of the overlapping oxide transistor can be avoided, the layout space is greatly saved, the space of the sub-pixels is reduced, and the resolution is greatly improved on the premise of ensuring low power consumption.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an LTPO substrate according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of a 7T1C according to an embodiment of the present disclosure;

FIG. 3 is a 7T1C layout using the structure of FIG. 1;

fig. 4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

FIG. 5 is a 7T1C layout using the structure of FIG. 4;

FIGS. 6-13 are block diagrams of a process for preparing the structure of FIG. 13 according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of another display substrate provided in this embodiment of the present application;

fig. 15 is a schematic view illustrating a test structure of a display substrate according to an embodiment of the present disclosure;

fig. 16 is an equivalent structure diagram of fig. 15.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the embodiments of the present application, the terms "first", "second", … … "," seventh ", and the like are used for distinguishing the same items or similar items with basically the same functions and actions, and are used only for clearly describing technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

In the embodiments of the present application, "a plurality" means two or more, and "at least one" means one or more unless specifically limited otherwise.

In the embodiments of the present application, the terms "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

In an embodiment of the present application, a transistor includes a gate, a source, and a drain, and one of the source and the drain is referred to as a first pole and the other is referred to as a second pole.

In the related art, the LTPO substrate may include an LTPS driving transistor 103, an oxide switching transistor 105 and a Cst capacitor 100 as shown in fig. 1, wherein the LTPS driving transistor and the oxide switching transistor are disposed in parallel, the oxide switching transistor is a dual-gate transistor, a gate electrode 104 of the LTPS driving transistor 103 and a second electrode 102 of the Cst capacitor 100 are disposed in the same layer, and a first electrode 101 of the Cst capacitor 100 and a bottom gate 106 of the oxide switching transistor 105 are disposed in the same layer; in fig. 1, the LTPO substrate further includes a PI (polyimide) substrate 107, a first GI layer 108, a first ILD layer 109, a second ILD layer 110, a Buffer layer 111, a second GI layer 112, a second ILD layer 113, a first PLN layer 114, a second PLN layer 115, an Anode layer 117, a PDL layer 118, and a PS layer 119, and the structure may be fabricated by using 13 masks. The LTPO substrate may adopt a 7T1C driving circuit as shown in fig. 2, wherein the transistor T3 may adopt an LTPS driving transistor as shown in fig. 1, the transistors T1 and T2 may adopt an oxide switching transistor as shown in fig. 1, the layout of the 7T1C driving circuit may be as shown in fig. 3, the Pitch of the finally formed sub-pixel is 56 μm, and the corresponding PPI (pixel density) is about 450. With LTPS technology, PPI can reach 630. The PPI of LTPO panels is yet to be further improved.

Based on the above, an embodiment of the present application provides a display substrate, which includes a substrate and a plurality of sub-pixels arranged in an array on one side of the substrate.

Referring to fig. 4, the sub-pixel includes a storage capacitor 2, a polysilicon transistor 1, at least one oxide transistor 3; the storage capacitor 2 includes a first electrode 18 and a second electrode 16, which are oppositely disposed, and the first electrode 18 is disposed on a side of the second electrode 16 away from the substrate 10.

Referring to fig. 4, the second electrode 16 is disposed in the same layer as the gate electrode 15 of the polysilicon transistor 1; the oxide transistor 3 is arranged on a side of the first electrode 18 facing away from the substrate 10, the first electrode 18 at least partially overlapping the active layer 20 of the at least one oxide transistor 3 in a direction perpendicular to the substrate.

The first electrode is configured to be connected with a power supply signal and also used as a bottom gate of the overlapping oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode along the direction vertical to the substrate is the overlapping oxide transistor.

The specific structure of the driving circuit used in the sub-pixel is not limited, and for example, a 2T1C driving circuit, a 3T1C driving circuit, or a 7T1C driving circuit may be used. For better driving performance, a 7T1C driving circuit as shown in fig. 2 may be adopted, and for example, a polysilicon transistor may be used as the driving transistor T3, an oxide transistor may be used as the switching transistor T1, T2, or the like.

The material of the active layer of the Oxide transistor may be a metal Oxide such as IGZO (Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide).

The type of the polysilicon transistor is not limited, and the polysilicon transistor may be a top gate type polysilicon transistor, or may also be a bottom gate type polysilicon transistor. Fig. 4 illustrates a top gate polysilicon transistor as an example.

The at least partial overlapping of the first electrode and the active layer of the at least one oxide transistor along a direction perpendicular to the substrate comprises: the first electrode partially overlaps with the active layer of the at least one oxide transistor along a direction perpendicular to the substrate, and at this time, an orthographic projection of the first electrode on the substrate may partially overlap with an orthographic projection of the active layer of the at least one oxide transistor on the substrate; or, the first electrode and the active layer of the at least one oxide transistor completely overlap in a direction perpendicular to the substrate, and in this case, an orthogonal projection of the active layer of the at least one oxide transistor on the substrate may be located within an orthogonal projection of the first electrode on the substrate.

The first electrode of the storage capacitor is used as the bottom gate and is electrically connected with the power signal line, so that the effects of protecting a channel and improving stability can be achieved, and the first electrode can be used as a light shielding layer to further protect the performance of the overlapping oxide transistor.

Note that the top gate and the bottom gate of the double-gate transistor are connected to the same gate signal, and in this application, the top gate of the cross-oxide transistor is connected to the gate signal, and the bottom gate (i.e., the first electrode) is connected to the power supply signal VDD (typically 4.6V dc voltage). Performance tests were conducted using the structure shown in fig. 15 as an example, and referring to fig. 15, the overlapping oxide transistor 200 includes a light-shielding electrode 202, an IGZO active layer 205, a gate (G) electrode 206, a source (S) electrode 207, and a drain (D) electrode 208; of course, the test structure further includes a glass substrate 201, silicon oxide (thickness)

) And silicon nitride (thickness)

) A buffer layer 203, a GI gate insulating layer 204, a PVX passivation layer 210, a Resin planarization layer 211, and a PDL definition layer 212, which are stacked. In which a light-shielding electrode is used as a bottom gate, refer to fig. 16Different direct current voltages are input to the shading electrodes, and corresponding voltages are input to the grid (G) electrode, the source (S) electrode and the drain (D) electrode at the same time, so that test results shown in the table I are obtained. Referring to table one, when the voltage of the light shielding electrode is 5V, the threshold voltage Vth of the transistor is about-1.5V, and at this time, the voltage Vgl for turning off the transistor is-7V, and the transistor can be normally turned off, which indicates that the transistor with this structure has good performance, good switching performance, and can be applied in a driving circuit.

Watch 1

In the display substrate provided by the application, the first electrode and the active layer of at least one oxide transistor are at least partially overlapped along the direction perpendicular to the substrate, and the first electrode is also used as the bottom gate of the overlapping oxide transistor, so that the additional arrangement of the bottom gate of the overlapping oxide transistor can be avoided, the layout space is greatly saved, the space of the sub-pixels is reduced, and the resolution is greatly improved on the premise of ensuring low power consumption.

Optionally, in order to improve the performance of the transistor, an orthographic projection of the active layer of the at least one oxide transistor on the substrate is located within an orthographic projection of the first electrode on the substrate. Referring to fig. 4, an orthographic projection F2 of the active layer 20 of the oxide transistor 3 on the substrate 10 is located inside an orthographic projection F1 of the first electrode 18 on the substrate 10. Fig. 4 is an example of the orthographic projection of the active layer of one oxide transistor on the substrate being within the orthographic projection of the first electrode on the substrate.

Here, the specific structure of the active layer is not limited, and for example, the active layer of the oxide transistor may include a semiconductor portion, and a first pole contact portion and a second pole contact portion located at both ends of the semiconductor portion, the first pole contact portion being electrically connected to the first pole, and the second pole contact portion being electrically connected to the second pole.

As a further alternative, and with reference to fig. 4, the orthographic projection F3 of the second electrode 16 on the substrate 10 is located within the orthographic projection F1 of the first electrode 18 on the substrate 10, which may further save space and improve resolution.

Alternatively, in order to better supply the power signal to the first electrode, as shown in fig. 4, the display substrate further includes a power line 31, and the first electrode 18 is electrically connected to the power line 31.

The specific location of the power line is not limited, and for example, one layer may be provided alone or in layers with other structures.

Further alternatively, in order to reduce the number of patterning and the production cost, referring to fig. 4, the power line 31 and the first and second poles 32 and 33 of the overlapping oxide transistor are disposed in the same layer, that is, the power line, the first and second poles of the overlapping oxide transistor may be formed simultaneously by a single patterning process.

The same layer setting refers to manufacturing by adopting a one-time composition process. The one-step patterning process refers to a process of forming a desired layer structure through one exposure. The primary patterning process includes masking, exposing, developing, etching, and stripping processes.

Alternatively, in order to reduce the design difficulty and the number of patterning times, referring to fig. 4, the polysilicon transistor is a top gate polysilicon transistor, and the active layer 13 of the polysilicon transistor 1 is disposed between the substrate 10 and the gate 15 of the polysilicon transistor 1.

Transistors can be classified into two types according to the positional relationship of electrodes. One is a thin film transistor of a bottom gate type in which a gate electrode is positioned below a source electrode and a drain electrode; one is a gate electrode on top of a source electrode and a drain electrode, and this is called a top gate type thin film transistor.

As a further alternative, in order to reduce the number of patterning times and the production cost, referring to fig. 4, the first pole 29 and the second pole 30 of the polysilicon transistor 1 are disposed in the same layer as the first pole 32 and the second pole 33 of the overlapping oxide transistor, that is, the first pole and the second pole of the polysilicon transistor and the first pole and the second pole of the overlapping oxide transistor can be formed simultaneously by a single patterning process.

It should be noted that, referring to fig. 4, if the display substrate further includes a power line 31, the first electrode 29 and the second electrode 30 of the polysilicon transistor are disposed in the same layer as the first electrode 32 and the second electrode 33 of the polyoxide transistor.

Further alternatively, and with reference to fig. 4, the sub-pixel further comprises an anode 35, one of the first and second poles of the polysilicon transistor being electrically connected to the anode to provide sufficient current to the light emitting diode. Fig. 4 illustrates an example in which the second pole 30 of the polysilicon transistor is electrically connected to the anode 35. It should be noted that, referring to fig. 4, the anode 35 may be electrically connected to the second pole 30 of the polysilicon transistor through a via hole penetrating the first flat layer 34; alternatively, referring to fig. 14, the anode 35 may be electrically connected to the connection electrode 41 through a via hole penetrating the second planarization layer 40, and the connection electrode 41 may be electrically connected to the second pole 30 of the polysilicon transistor through a via hole penetrating the first planarization layer 34.

In one or more embodiments, to provide better drive performance, the polysilicon transistors are P-type transistors and the oxide transistors are N-type transistors.

In one or more embodiments, in order to improve scalability of the driving circuit, the sub-pixel may further include a single gate oxide transistor whose active layer does not overlap with the first electrode in a direction perpendicular to the substrate, in which case, the sub-pixel includes a plurality of different types of transistors, and sub-pixel driving circuits having different performances may be formed. The number of the single-gate oxide transistors is not limited, and can be determined according to actual requirements.

In one or more embodiments, referring to fig. 2, the sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; the first transistor T1 and the second transistor T2 are oxide transistors as shown in fig. 4, and the third transistor T3 is a polysilicon transistor, which may be a top gate type polysilicon transistor as shown in fig. 4.

Referring to fig. 2, the display substrate further includes a power line ELVDD, a light emission control signal line EM, a Data signal line Data, a reset control signal line Scan, and an initial signal line Vinit; the sub-pixels further comprise light emitting diodes, LEDs. In fig. 2, the gates of all transistors are labeled G, the first pole is labeled S, and the second pole is labeled D.

Referring to fig. 2, a gate electrode of the first transistor T1 is electrically connected to the reset control signal line Scan, a second electrode thereof is electrically connected to the initialization signal line Vinit, a first electrode of the first transistor T1 and a first electrode of the second transistor T2 are electrically connected to the first node N1, a gate electrode of the third transistor T3 and a second electrode of the storage capacitor Cst are electrically connected to the first node N1, and a first electrode of the storage capacitor Cst is electrically connected to the power line ELVDD.

Referring to fig. 2, the gate of the second transistor T2 is electrically connected to the reset control signal line Scan, the second pole is electrically connected to the third node N3, the first pole of the third transistor T3 is electrically connected to the second node N2, the second pole is electrically connected to the third node N2, the first pole of the fourth transistor T4 is electrically connected to the second node N2, the second pole is electrically connected to the Data signal line Data, the gate is electrically connected to the reset control signal line Scan, the second pole of the fifth transistor T5 is electrically connected to the second node N2, the first pole is electrically connected to the power supply line ELVDD, and the gate is electrically connected to the emission control signal line EM.

Referring to fig. 2, the gate of the sixth transistor T6 is electrically connected to the light emission control signal line EM, the first pole is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, the gate of the seventh transistor T7 is electrically connected to the reset control signal line Scan, the first pole is electrically connected to the fourth node N4, the second pole is electrically connected to the initialization signal line Vinit, the anode of the light emitting diode LED is electrically connected to the fourth node N4, and the cathode is grounded ELVSS.

The orthographic projections of the active layers of the first transistor and the second transistor on the substrate are located within the orthographic projection of the first electrode on the substrate, and the orthographic projections of the active layers of the other transistors on the substrate are not overlapped with the orthographic projection of the first electrode on the substrate.

The first node N1, the second node N2, the third node N3, and the fourth node N4 are only for convenience of describing a circuit configuration, and are not an actual circuit unit.

The fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may all be polysilicon transistors or oxide transistors, which is not limited herein.

The sub-pixel adopts a driving circuit of 7T1C, and the driving principle of the driving circuit can be obtained by referring to the related art, which is not described herein again. The first electrode is used as one electrode of the storage capacitor and also used as the bottom gates of the first transistor and the second transistor, so that the additional arrangement of the bottom gates of the first transistor and the second transistor can be avoided, the layout space is greatly saved, and the space between sub-pixels is reduced. The first transistor T1 and the second transistor T2 have the same oxide transistor structure as shown in fig. 4, the third transistor T3 has the same polysilicon transistor structure as shown in fig. 4, and referring to fig. 5, the first transistor T1 and the second transistor T2 are disposed to overlap the first electrode 18; compared with fig. 3, the first electrode 18 is used as both the first electrode of the storage capacitor and the bottom gates of the first transistor and the second transistor, so that the additional arrangement of the bottom gates of the first transistor and the second transistor can be avoided, and the layout space is greatly saved. The Pitch of the sub-pixel shown in fig. 5 is 42 μm, and the corresponding PPI is about 600, which greatly improves the resolution ratio on the premise of ensuring low power consumption compared with the structure shown in fig. 3.

It should be noted that, as shown in fig. 4, the display substrate may further include an isolation layer 11, a first buffer layer 12, a first gate insulating layer 14, a second gate insulating layer 17, a second buffer layer 19, a third gate insulating layer 21, an interlayer dielectric layer 23, a first planarization layer 34, a pixel defining layer 36, an anode 35, and a spacer 37, and of course, other structures may also be included.

The embodiment of the application also provides a display panel which comprises the display substrate.

The display panel may be a flexible display panel (also referred to as a flexible screen) or a rigid display panel (i.e., a display panel that cannot be bent), which is not limited herein. The display panel may be an OLED (Organic Light-Emitting Diode) display panel, a Micro LED display panel or a Mini LED display panel, and any product or component having a display function, such as a television, a digital camera, a mobile phone, a tablet computer, and the like, including the display panel.

The embodiment of the application further provides a preparation method of the display substrate, which comprises the following steps:

and S01, forming a plurality of sub-pixels arranged in an array on the substrate.

S01, forming a plurality of sub-pixels arranged in an array on a substrate includes:

s10, forming a storage capacitor, a polysilicon transistor and at least one oxide transistor; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, and the first electrode is arranged on one side of the second electrode, which is far away from the substrate; the second electrode and the grid electrode of the polycrystalline silicon transistor are arranged on the same layer; the oxide transistor is arranged on one side of the first electrode far away from the substrate, and the first electrode and the active layer of the at least one oxide transistor at least partially overlap along the direction vertical to the substrate; the first electrode is configured to be connected with a power supply signal and also used as a bottom gate of the overlapping oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode along the direction vertical to the substrate is the overlapping oxide transistor.

In the display substrate formed by the preparation method, the first electrode is at least partially overlapped with the active layer of at least one oxide transistor along the direction vertical to the substrate, and meanwhile, the first electrode is also used as the bottom gate of the overlapped oxide transistor, so that the additional arrangement of the bottom gate of the overlapped oxide transistor can be avoided, the layout space is greatly saved, the space of the sub-pixels is reduced, and the resolution is greatly improved on the premise of ensuring low power consumption. The preparation method is simple and easy to implement.

Optionally, in order to reduce the number of patterning and reduce the production cost, the forming of the storage capacitor and the polysilicon transistor includes:

and S20, forming a second electrode of the storage capacitor and a gate electrode of the polysilicon transistor by adopting a one-step composition process.

Optionally, in order to reduce the number of patterning and reduce the production cost, the forming of the polysilicon transistor and the overlapping oxide transistor includes:

and S30, forming a first pole and a second pole of the polysilicon transistor and a first pole and a second pole of the overlapping oxide transistor by adopting a one-step composition process.

The specific production method will be described below by taking the structure shown in FIG. 13 as an example.

The method comprises the following steps:

s101, sequentially forming an isolation layer (Barrier)11, a first buffer layer 12, an active layer 13 of a polysilicon transistor, a first gate insulating layer 14, a gate metal layer, a second gate insulating layer 17, and a first electrode 18 of a storage capacitor on a substrate 10 as shown in fig. 6; wherein, the gate metal layer comprises a second electrode 16 of the storage capacitor and a gate 15 of the polysilicon transistor, and an orthographic projection F3 of the second electrode 16 on the substrate 10 is positioned within an orthographic projection F1 of the first electrode 18 on the substrate 10.

The second electrode and the grid electrode of the polycrystalline silicon transistor are manufactured by adopting a one-time composition process. The substrate may be a flexible substrate, for example: a PI substrate, etc.; alternatively, it may also be a rigid substrate, such as: a glass substrate, etc. If the PI substrate is adopted, in order to provide better performance, an isolating film and a PI film can be additionally arranged between the substrate and the isolating layer in sequence.

The active layer material of the polysilicon transistor may be a low temperature polysilicon material. The material of the first gate insulating layer and the second gate insulating layer may be silicon oxide, silicon nitride, or the like. The material of the gate metal layer and the first electrode may be metal, for example: copper, aluminum, and the like.

In S101, a Mask is required for forming an active layer of the polysilicon transistor, a Mask is required for forming the second electrode and the gate of the polysilicon transistor, and a Mask is required for forming the first electrode, which is a total of 3 masks.

S102, depositing a second buffer layer 19 as shown in fig. 7 on the first electrode 18.

The second buffer layer is a gate insulating layer of both the insulating layer and the bottom gate (i.e., the second electrode), and the material and thickness can be adjusted according to the specific device characteristics, and the thickness is usually selected to be

Silicon oxide of (2).

S103, the active layer 20 of the oxide transistor shown in fig. 8 is formed on the second buffer layer 19.

The material of the active layer may be a metal oxide material such as IGZO. In S103, a Mask is required to form the active layer of the oxide transistor.

S104, forming a third gate insulating layer 21 and a gate electrode (i.e., a top gate) 22 of the oxide transistor as shown in fig. 9, wherein the third gate insulating layer 21 covers the active layer 20 of the oxide transistor.

In S104, a Mask is required to form the gate of the oxide transistor.

And S105, forming an interlayer dielectric layer 23 covering the gate of the oxide transistor, and forming a first via hole 24, a second via hole 25 and a third via hole 26 as shown in FIG. 10.

The first through hole and the second through hole respectively penetrate through the interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer and the first gate insulating layer, the third through hole penetrates through the interlayer dielectric layer, the third gate insulating layer and the second buffer layer, the first through hole is used for electrically connecting a first pole of the polycrystalline silicon transistor with an active layer of the polycrystalline silicon transistor, the second through hole is used for electrically connecting a second pole of the polycrystalline silicon transistor with the active layer of the polycrystalline silicon transistor, and the third through hole is used for electrically connecting a power signal line with the first electrode.

In S105, first etching to form a first via hole and a second via hole, then performing HF (hydrogen fluoride) cleaning, and then forming a third via hole; and forming the first via hole and the second via hole requires one Mask, and forming the third via hole requires 2 masks in total.

And S106, forming a fourth via hole 27 and a fifth via hole 28 as shown in FIG. 11.

The fourth via hole and the fifth via hole respectively penetrate through the third gate insulating layer and the second buffer layer, the first pole of the oxide transistor is electrically connected with the active layer of the oxide transistor through the fourth via hole, and the second pole of the oxide transistor is electrically connected with the active layer of the oxide transistor through the fifth via hole. In S106, a Mask is required to form the fourth via and the fifth via.

S107, forming a source-drain metal layer, wherein the source-drain metal layer includes the first and second poles 29 and 30 of the polysilicon transistor, the power signal line ELVDD line 31, and the first and second poles 32 and 33 of the oxide transistor as shown in fig. 12.

The first pole and the second pole of the polycrystalline silicon transistor are respectively and electrically connected with the active layer of the polycrystalline silicon transistor through a first through hole and a second through hole, the power supply signal line ELVDD is electrically connected with the first electrode through a third through hole, and the first pole and the second pole of the oxide transistor are respectively and electrically connected with the active layer of the oxide transistor through a fourth through hole and a fifth through hole. In S107, a Mask is required to form the fourth via and the fifth via.

And S108, forming a first flat layer 34 covering the source-drain metal layer, an anode 35, a pixel defining layer 36 and a spacer (PS)37 as shown in FIG. 13.

The anode is electrically connected with the second pole of the polysilicon transistor through the sixth via hole. In S108, a Mask is required for forming the sixth via hole, a Mask is required for forming the anode, a Mask is required for forming the pixel defining layer, and a Mask is required for forming the spacer, for a total of 4 masks.

In the above preparation method, 3 masks are used in S101, 1 Mask is used in S103, 1 Mask is used in S104, 2 masks are used in S105, 1 Mask is used in S106, 1 Mask is used in S107, 4 masks are used in S108, and 13 masks are used in total.

The preparation method is simple and easy to implement, and the display substrate with higher resolution is formed under the condition that the times of the original composition process are not changed.

It should be noted that, for the description of the relevant structure of the display substrate in the embodiment of the present application, reference may be made to the foregoing embodiment, and details are not described here again.

Reference herein to "one embodiment," "an embodiment," or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Moreover, it is noted that instances of the word "in one embodiment" are not necessarily all referring to the same embodiment.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims (12)

1. The display substrate is characterized by comprising a substrate and a plurality of sub-pixels arranged in an array and positioned on one side of the substrate;

the sub-pixel comprises a storage capacitor, a polysilicon transistor and at least one oxide transistor; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, and the first electrode is arranged on one side of the second electrode far away from the substrate;

the second electrode and the grid electrode of the polycrystalline silicon transistor are arranged on the same layer; the oxide transistor is arranged on one side of the first electrode far away from the substrate, and the first electrode at least partially overlaps with the active layer of at least one oxide transistor along the direction vertical to the substrate;

the first electrode is configured to be connected with a power supply signal and also used as a bottom gate of an overlapping oxide transistor, wherein the oxide transistor at least partially overlapped with the first electrode in a direction perpendicular to the substrate is the overlapping oxide transistor.

2. The display substrate of claim 1, wherein an orthographic projection of an active layer of at least one of the oxide transistors on the substrate is located within an orthographic projection of the first electrode on the substrate.

3. The display substrate of claim 2, wherein an orthographic projection of the second electrode on the substrate is located within an orthographic projection of the first electrode on the substrate.

4. The display substrate according to claim 1, further comprising a power supply line, wherein the first electrode is electrically connected to the power supply line.

5. The display substrate of claim 4, wherein the power supply line is disposed with the first and second poles of the overlapping oxide transistor.

6. The display substrate of claim 1, wherein the polysilicon transistor is a top gate polysilicon transistor, and wherein the active layer of the polysilicon transistor is disposed between the substrate and the gate of the polysilicon transistor.

7. The display substrate of claim 6, wherein the first and second poles of the polysilicon transistor are disposed in the same layer as the first and second poles of the cross-over oxide transistor.

8. The display substrate of claim 7 wherein the subpixel further comprises an anode, one of the first and second poles of the polysilicon transistor being electrically connected to the anode.

9. The display substrate of claim 1, wherein the polysilicon transistor is P-type and the oxide transistor is N-type.

10. The display substrate of claim 1, wherein the sub-pixel further comprises a single-gate oxide transistor, and wherein an active layer of the single-gate oxide transistor does not overlap with the first electrode in a direction perpendicular to the substrate.

11. The display substrate according to claim 1, wherein the sub-pixel further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the first transistor and the second transistor are the oxide transistors, and the third transistor is the polysilicon transistor;

the display substrate further comprises a power line, a light-emitting control signal line, a data signal line, a reset control signal line and an initial signal line; the sub-pixels further comprise light emitting diodes;

a gate of the first transistor is electrically connected to the reset control signal line, a second electrode of the first transistor is electrically connected to an initial signal line, a first electrode of the first transistor and a first electrode of the second transistor are electrically connected to a first node, a gate of the third transistor and the second electrode of the storage capacitor are electrically connected to the first node, and the first electrode of the storage capacitor is electrically connected to the power supply line;

a gate of the second transistor is electrically connected to the reset control signal line, a second pole of the second transistor is electrically connected to a third node, a first pole of the third transistor is electrically connected to the second node, a second pole of the third transistor is electrically connected to the third node, a first pole of the fourth transistor is electrically connected to the second node, a second pole of the fourth transistor is electrically connected to the data signal line, a gate of the fourth transistor is electrically connected to the reset control signal line, a second pole of the fifth transistor is electrically connected to the second node, a first pole of the fifth transistor is electrically connected to the power line, and a gate of the fifth transistor is electrically connected to the emission control signal line;

a gate of the sixth transistor is electrically connected to the light emission control signal line, a first electrode of the sixth transistor is electrically connected to the third node, a second electrode of the sixth transistor is electrically connected to a fourth node, a gate of the seventh transistor is electrically connected to the reset control signal line, a first electrode of the seventh transistor is electrically connected to the fourth node, a second electrode of the seventh transistor is electrically connected to the initial signal line, an anode of the light emitting diode is electrically connected to the fourth node, and a cathode of the light emitting diode is grounded;

wherein orthographic projections of the active layers of the first transistor and the second transistor on the substrate are both located within the orthographic projection of the first electrode on the substrate, and orthographic projections of the active layers of the rest transistors on the substrate are not overlapped with the orthographic projection of the first electrode on the substrate.

12. A display panel comprising the display substrate according to any one of claims 1 to 11.

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