CN2157581Y - Data protector for high reliable random memory - Google Patents

Data protector for high reliable random memory Download PDF

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Publication number
CN2157581Y
CN2157581Y CN 93200196 CN93200196U CN2157581Y CN 2157581 Y CN2157581 Y CN 2157581Y CN 93200196 CN93200196 CN 93200196 CN 93200196 U CN93200196 U CN 93200196U CN 2157581 Y CN2157581 Y CN 2157581Y
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CN
China
Prior art keywords
power
monitoring
connected
vcc
random memory
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CN 93200196
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Chinese (zh)
Inventor
李兰兰
孙华
付卓
肖钢
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中国中医研究院基础理论研究所
李兰兰
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Priority to CN 93200196 priority Critical patent/CN2157581Y/en
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Publication of CN2157581Y publication Critical patent/CN2157581Y/en

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Abstract

The utility model discloses a data protector for a random memory with high reliability, which is composed of a casing, a power converting circuit, a monitoring and protecting circuit, wherein, the power converting circuit comprises a triode, a diode, and a chargeable cell; the monitoring and protecting circuit comprises two voltage comparator, a voltage dividing branch circuit, and a capacitance-resistance delay branch circuit. When the power is cut off, the power of the random memory is supplied by the cell, and the random memory does not be changed, the sheet selecting control signals output from the monitoring and protecting circuit can make random memory rapidly be locked by self in the process of on-and-off power when system power is lower than the normal value, avoiding generating misoperation, so that the datum can be protected. The utility model is suitable for the data protector for the random memory in the digital system.

Description

高可靠随机存储器数据保护器 Highly reliable RAM data protector

本实用新型涉及计算机技术中数据掉电保护装置,属于数字数据处理装置领域。 The present invention relates to power-down the computer art data protection means belonging to the field of digital data processing apparatus.

在数字系统中,RAM(随机存储器)常用来存放各种测试数据、累计值及表格等,在许多场合下要求长期可靠地保存这些数据。 In digital systems, RAM (Random Memory) used to store a variety of test data and the accumulated value table, etc., long-term reliable data storage requirement in many applications. 但是不可预知的断电或电源波动会造成RAM中数据丢失、表格破坏,导致整个系统不能正常运行。 But the unpredictable power down or power fluctuations can cause data loss in RAM, tables damaged, the entire system can not function properly. CN2033136U公开了一种RAM掉电保护技术,但它未能解决因上下电的瞬态过程或电源不稳可能引起的对RAM误操作问题。 CN2033136U discloses a power failure protection RAM technology, but it failed to solve the problem of misuse of RAM and down due to electrical transients or power surge may cause.

本实用新型的目是提供一种不仅在掉电而且在掉电或上电瞬态过程及电源不稳情况下使RAM中的数据不会丢失的装置。 The purpose of the present invention is to provide an apparatus in a power-down not only but also the data RAM at power up or power-down transient power is not stable and will not be lost.

本实用新型的目的是这样实现的:一种随机存储器数据保护器由外壳、电源变换电路和监测保护电路组成,系统电源Vcc一路经电源变换电路接RAM正电源VDD,另一路作为监测保护电路的被测输入信号,电源变换电路由三极管、可充电池和二极管组成,监测保护电路由输出端并接的两个电压比较器和两条均接在Vcc和公共地之间的支路-分压支路和阻容延迟支路-组成,电池电压作为比较电压接在两个比较器的负输入端,分压点和阻容串联点分别作为掉电和上电过程中的电压监测点接各自比较器的正输入端,比较器的输出端作为RAM片选控制信号。 The object of the present invention is implemented as follows: A type of RAM data protector by the housing, the power conversion circuit and a protection circuit monitoring, the system all the way to the power supply Vcc connected via the RAM positive power supply VDD power conversion circuit, the other way as protective circuit monitoring the measured input signal, the power conversion circuit by the transistor, rechargeable battery and a diode, monitoring and protection circuit and the output terminal of the voltage comparators into contact two and two are connected between Vcc and the common branch - dividing RC branch delay and branch - the composition, the battery voltage as the comparison voltage connected to the negative input terminal of the two comparators, and the dividing point as a series RC points respectively during power down and a voltage monitor connected to a respective point the positive input of the comparator, the output of the comparator as a RAM chip select control signals.

系统电源Vcc掉电过程中,分压点的电位随即降低,当降至电池电压以下时,比较器的输出变为0,RAM中的数据因片选信号无效,不能被读写而得到保护;Vcc上电过程中,阻容串联点的电位滞后上升,直至Vcc升至额定值时,该点电位才高于电池电压,比较器的输出才变为1,RAM中的数据才能被读写。 Vcc during system power down, then the potential dividing point decreases, when the battery voltage dropped below the output of the comparator becomes 0, because the data in RAM chip select signal is inactive and can not be read protected; Vcc power-on process, the potential of the point series RC hysteresis rise till the rating was raised to Vcc, higher than the potential of the point until the battery voltage, only the output of the comparator becomes 1, data is read to the RAM. 由此可见本实用新型无论在掉电或上电过程中都能对RAM数据进行可靠的保护。 RAM data can be reliably protected by the present invention process can be seen both in the power down or power.

下面结合附图和实施例对本实用新型作进一步描述。 The present invention is further described as below in conjunction with the accompanying drawings and embodiments.

图1是本实用新型的框图图2是本实用新型的电路原理图图中所示的随机存储器数据保护器由外壳1、电源变换电路2和监测保护电路3组成。 FIG. 1 is a block diagram of the present invention FIG. 2 is a random access memory data protector of the present invention is shown in circuit diagram in FIG. 1 by the housing, the power conversion circuit 2 and the monitoring circuit 3 composed of protection. 其中,外壳1上有四个接线端:系统电源Vcc、RAM电源VDD、公共地GND和RAM片选控制信号CE;电源变换电路2由三极管T、基极电阻R2、可充电池E和二极管D组成,Vcc接三极管T的发射极,电池E的负极接GND,正极分别经R2、正向二极管D与三极管T的基极、集电极相接,集电极作为VDD输出;监测保护电路3则由两个电压比较器4、5和两条均接Vcc和GND之间的支路-电阻R3R4分压支路、电阻R5电容C3阻容延迟支路-组成,分压点G和阻容串联点F分别作为掉电和上电过程中的电压监测点接各自比较器的正输入端,电源变换电路2中的电池E作为比较电压接在各比较器的负输入端,两个比较器的输出端并在一起作为RAM片选控制信号,输出端接有上拉电阻R1。 Wherein the housing has four terminals 1: System power source Vcc, the VDD power RAM, a common ground GND and the CE RAM chip select control signal; a power conversion circuit by the transistor T 2, the base resistor R2, a rechargeable battery and a diode D E composition, then the transistor T-emitting pole Vcc, GND connected to the negative electrode of the battery E, the positive electrode, respectively, by R2, the forward diode of the transistor T, group D, a collector contact, collector output as VDD; monitoring protection circuit 3 by two voltage comparators 4, 5 and the two branches are connected between Vcc and GND - R3R4 resistor divider legs, capacitor C3 and resistor R5 RC delay branch - the composition, dividing point G and point series RC output terminal F are connected to the negative input of each comparator as during power down and the positive input terminal of the voltage monitoring point, the power conversion circuit 2 in the battery E as the comparison voltage connected to each comparator, two comparators ends together as a RAM chip select control signal, output termination pull-up resistor R1.

图中:E=3.6V;CE=1时可对RAM进行正常操作;Vcc>4.5V时G点电位UG>3.6,F点电位VF=Vcc,此时系统正常工作;各元件参数依据上述值确定。 FIG: E = 3.6V; CE = 1 during normal operation may be the RAM; Vcc> 4.5V G when the potential at the point UG> 3.6, F point potential VF = Vcc, when the system is working properly; elements according to the above parameter values determine.

现在叙述本实用新型的工作原理:稳定状态:Vcc<E时,T截止D导通,VDD=E,此时RAM处数据保持状态;4.5V≥Vcc>E时,T导通D关断,VDD=Vcc,Vcc通过T的eb结和R2向E充电,但此时UG<3.6V,即低于E,故CE=O,RAM处自锁状态,不允许对其读写;Vcc)4.5V时,T导通D关断,VDD=Vcc,E被充电,此时UG)E且UF)E,故CE=1,RAM处正常工作状态。 The present invention will now be described working principle: steady state: Vcc <When E, T D is turned off, VDD = E, the holding state of the data RAM at this time; 4.5V≥Vcc> E time, T D is turned off, VDD = Vcc, Vcc is charged by the T eb junction and R2 to E, but this time UG <3.6V, i.e. less than E, so CE = O, the locked state RAM, you can not read and write; Vcc) 4.5 when V, T D is turned off, VDD = Vcc, E is charged at this time UG) E and UF) E, so CE = 1, normal operation of the RAM.

瞬态过程:在Vcc从0升至大于4.5V的上电过程中,VDD从Vcc)E时开始跟随Vcc,虽然G点电位VG随Vcc很快上升至E,但F点电位UF由于其延迟电路特性而滞后Vcc变化,不会很快超过E,故使得比较器的输出即CE仍保持低电平一段时间,这样便保证RAM在Vcc达到大于4.5V的稳态值之前不会接受误操作;而在Vcc降到0的掉电过程中,只要Vcc≤4.5V,则UG随即跟随至UG≤3.6V,使CE=0,RAM进入自锁状态,自Vcc<E后VDD=E,此时RAM由E供电进入保持状态;电源不稳的现象可归入上电或掉电过程,其分析同上。 Transient: from 0 at Vcc rises above the 4.5V power process, VDD Vcc) E from the start time to follow Vcc, while the potential of the point G VG with Vcc rises rapidly to E, but the F point potential due to its delay UF Vcc hysteresis characteristic change circuit, not quickly than E, so that the output of the comparator, i.e. CE remains low for a period, to ensure that this will not be accepted until an erroneous operation reached a steady state value greater than RAM in Vcc 4.5V ; Vcc falls down in the process 0, as long Vcc≤4.5V, then follow the UG to UG≤3.6V, so CE = 0, RAM into the locked state, since Vcc <E VDD = E, this when the RAM into the holding state by the power supply E; unstable phenomenon can be assigned to power on power on processes that analyzes supra.

由以上叙述可知,由电压比较器、R3-R5和C3组成的监测保护电路可使RAM在Vcc低于正常值时迅速自锁,避免产生误动作。 From the above description, the protection circuit monitors the voltage comparator, R3-R5 and C3 of RAM can rapidly self-locking when Vcc is lower than normal, to avoid malfunction.

此外为消除电源中的各种高频干扰对RAM产生的冲击现象,在VDD和GND之间还并接滤波电容C1和C2。 In addition, to eliminate high-frequency interference SHOCK various power generated in the RAM, also between VDD and GND, and filter capacitor C1 and C2.

Claims (3)

1.一种高可靠随机存储器数据保护器由外壳(1)电源变换电路(2)和监测保护电路(3)组成,系统电源Vcc一路经电源变换电路(2)接RAM正电源VDD,另一路作为监测保护电路(3)的被测输入信号,后者的输出作为RAM片选控制信号,电源变换电路(2)由三极管T、基极电阻R2、可充电池E和二极管D组成,其特征在于监测保护电路(3)由输出端并接的两个电压比较器(4、5)和两条均接在Vcc和公共地GND之间的支路-电阻R3、R4分压支路、电阻R5和电容C3阻容延迟支路-组成,电池E作为比较电压接电压比较器(4、5)的负输入端,分压点G和阻容串联点F分别作为掉电和上电过程中的电压监测点接各自比较器的正输入端。 A highly reliable random access memory by the data protector housing (1) power conversion circuit (2) monitoring and protection circuit (3), with the way the system power source Vcc (2) connected to positive power supply VDD via the RAM power conversion circuit, another way a monitoring and protection circuit (3) of the measured input signal, the output of which RAM chip select control signal as the power conversion circuit (2) by the transistor T, the base resistor R2, a rechargeable battery and a diode D E composition, characterized in in that the monitoring and protection circuit (3) and connected from the output terminal of the two voltage comparators (4, 5) and two are connected between Vcc and ground GND common branch - resistors R3, R4 divider legs, resistors R5 and capacitor C3 RC delay branch - the composition, the battery E as the voltage on the negative input terminal of the comparator voltage comparator (4, 5), the dividing point G and the point F respectively series RC as during power down and monitoring points connected to respective voltage comparator positive input terminal.
2.根据权利要求1所述的高可靠随机存储器数据保护器,其特征在于在所说电源变换电路(2)中,电池E的负极接GND、正极分别经基极电阻R2、正向二极管D与三极管T的基极、集电极相接,T的发射极接Vcc,集电极作为VDD输出。 The high-reliability data protector random access memory according to claim 1, characterized in that said power conversion circuit (2), the negative electrode of the battery E is connected to GND, respectively, the positive electrode via a base resistor R2, a forward diode D , the collector of the transistor T is in contact with the base, the emitter electrode connected T Vcc, the collector output as VDD.
3.根据权利要求1或2所述的高可靠随机存储器数据保持器,其特征在于所说三极管T的集电极与GND之间并联抗干扰用的滤波电容C1和C2。 3. The holder according to highly reliable data or a random access memory according to claim 1, wherein said filtering capacitor C1 and GND in parallel between the collector of transistor T and the interference with the C2.
CN 93200196 1993-01-08 1993-01-08 Data protector for high reliable random memory CN2157581Y (en)

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Application Number Priority Date Filing Date Title
CN 93200196 CN2157581Y (en) 1993-01-08 1993-01-08 Data protector for high reliable random memory

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CN 93200196 CN2157581Y (en) 1993-01-08 1993-01-08 Data protector for high reliable random memory

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900264A (en) * 2015-06-25 2015-09-09 上海斐讯数据通信技术有限公司 System and method for preventing data damage during startup and shutdown of SPI FLASH
CN101867169B (en) * 2009-04-17 2016-07-13 晨星软件研发(深圳)有限公司 The protection circuit is applied to a flash memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101867169B (en) * 2009-04-17 2016-07-13 晨星软件研发(深圳)有限公司 The protection circuit is applied to a flash memory
CN104900264A (en) * 2015-06-25 2015-09-09 上海斐讯数据通信技术有限公司 System and method for preventing data damage during startup and shutdown of SPI FLASH
WO2016206263A1 (en) * 2015-06-25 2016-12-29 上海斐讯数据通信技术有限公司 System and method of preventing data corruption during power-on/power-off of spi flash

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