CN214848590U

CN214848590U - Semiconductor packaging structure

Info

Publication number: CN214848590U
Application number: CN202120722725.7U
Authority: CN
Inventors: 杨博智
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-11-23
Anticipated expiration: 2031-04-09

Abstract

The embodiment of the application relates to a semiconductor packaging structure. A semiconductor package structure according to an embodiment, comprising: a substrate having a first surface and a second surface opposite the first surface; a die disposed on the first surface of the substrate; a first seal encapsulating the die; a solder connection at the second surface, the solder connection comprising a first portion proximate the second surface and a second portion distal the second surface; and a second seal in contact with the first portion of the solder connection and exposing the second portion of the solder connection.

Description

Semiconductor packaging structure

Technical Field

The embodiment of the application relates to the field of semiconductors, in particular to a semiconductor packaging structure.

Background

As semiconductor packaging technology advances, application scenarios of semiconductor packages become more diversified and complicated, and it is still desirable to better improve performance of semiconductor packages and reduce cost of semiconductor packages to accommodate such diversified application scenarios.

For example, in one scenario, when a semiconductor package is used in an automotive application scenario, a semiconductor package with lower manufacturing cost and better Solder Joint Reliability (SJR) performance is critical.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor package structure, which can improve SJR performance and reduce manufacturing cost.

An embodiment of the present application provides a semiconductor package structure, which includes: a substrate having a first surface and a second surface opposite the first surface; a die disposed on the first surface of the substrate; a first seal encapsulating the die; a solder connection at the second surface, the solder connection comprising a first portion proximate the second surface and a second portion distal the second surface; and a second seal in contact with the first portion of the solder connection and exposing the second portion of the solder connection.

In some embodiments of the present application, the solder connection includes a neck portion between the first portion and the second portion.

In some embodiments of the present application, a lowermost portion of the second encapsulant extends to an intermediate height of the solder connections.

In some embodiments of the present application, the semiconductor package structure further comprises a first conductive pad at the second surface of the substrate, the second seal being in contact with the first conductive pad.

In some embodiments of the present application, the semiconductor package structure further comprises a first conductive pad at the second surface of the substrate, the second seal being free of contact with the first conductive pad.

In some embodiments of the present application, a portion of the second seal between adjacent solder connections has a curvilinear shape.

In some embodiments of the present application, a portion of the second seal between adjacent solder connections has a flat shape.

In some embodiments of the present application, the semiconductor package structure further comprises a carrier having a second conductive pad, wherein the solder connection electrically connects the substrate with the second conductive pad.

In some embodiments of the present application, the semiconductor package structure further comprises: an opening through the substrate; and a bonding wire electrically coupled with the die and the second surface of the substrate; wherein the second encapsulant further encapsulates the bond wire.

In some embodiments of the present application, the opening is to expose an active surface of the die.

Drawings

The drawings necessary for describing the embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to some comparative examples of the present application.

Fig. 2 is a cross-sectional structural schematic diagram of a semiconductor package of some embodiments of the present application.

Fig. 3A is an enlarged view of the cross-sectional structure at a (a dashed-line frame portion) in fig. 2 of the present application.

Fig. 3B is another enlarged view of the sectional structure at a (a dashed-line frame portion) in fig. 2.

Fig. 4A is a partial cross-sectional structural schematic view of a semiconductor package structure according to some embodiments of the present application.

Fig. 4B is a partial cross-sectional structural schematic view of a semiconductor package structure according to some embodiments of the present application.

Fig. 5A to 5E are schematic structural views illustrating formation of a second sealing body in a semiconductor package structure according to some embodiments of the present application.

Fig. 6 is a cross-sectional structural schematic diagram of a semiconductor package structure according to some embodiments of the present application.

Fig. 7A is a schematic partial cross-sectional view of a semiconductor package structure according to some comparative examples of the present application.

Fig. 7B is a schematic scanning electron microscope of the structure of fig. 7A.

Fig. 7C is a partial cross-sectional structural schematic view of a semiconductor package structure according to some embodiments of the present application.

Fig. 7D is a schematic scanning electron microscope of the structure of fig. 7C.

Fig. 8 is a schematic cross-sectional view of a semiconductor package according to some comparative examples of the present application.

Fig. 9 is a cross-sectional structural schematic diagram of a semiconductor package of some embodiments of the present application.

Fig. 10 is a cross-sectional structural diagram of a semiconductor package structure according to some embodiments of the present application.

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

Reference throughout this specification to "some embodiments," "one embodiment," "another example," "an example," "a specific example," or "some examples" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example in this application. Thus, throughout the specification, descriptions appear, for example: "in some embodiments," "in an embodiment," "in one embodiment," "in another example," "in one example," "in a particular example," or "by example," which do not necessarily refer to the same embodiment or example in this application.

As used herein, spatially relative terms, such as "under," "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "on … …," "under … …," "down," and the like are directed relative to the orientation shown in the figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner provided that the embodiments of the present application are not biased by such arrangements.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to both an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation of less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

Some embodiments of the present application provide a semiconductor package structure including a substrate (substrate), a die (die), a first seal (encapsulation), a solder connection (solder connection), and a second seal. Wherein the substrate has a first surface and a second surface opposite the first surface, the die is disposed on the first surface of the substrate, the first seal encapsulates the die, the solder connection is at the second surface, the solder connection includes a first portion adjacent the first surface and a second portion distal from the second surface, the second seal is in contact with the first portion of the solder connection and exposes the second portion of the solder connection. The second sealing body can effectively improve the SJR performance of the solder connecting piece and reduce the overall manufacturing cost.

In some embodiments of the present application, the second encapsulant is an Epoxy Molding Compound (EMC) or other common commercially available material used for encapsulation or encapsulation in semiconductor manufacturing processes.

Fig. 1 is a schematic cross-sectional view of a semiconductor package structure 100 according to some comparative examples of the present application. The semiconductor package structure 100 includes a semiconductor package 10A, a carrier 20A, and an underfill 120.

As shown in fig. 1, the semiconductor package 10A includes a substrate 101, a die 102, a first encapsulant 103, a first conductive pad 104, a solder resist layer 105, and a solder connection 106. Wherein the substrate 101 has a first surface 101A and a second surface 101B opposite the first surface 101A, the die 102 is disposed on the first surface 101A of the substrate 101, the first seal 103 encapsulates the die 102, and the solder connection 106 is disposed on the first conductive pad 104 at the second surface 101B.

In some comparative examples of the present application, the substrate 101 includes a circuit portion that is electrically coupled to the die 102 through conductive components, such as vias (via), conductive traces (trace), etc. A first conductive pad 104 belongs to the circuit portion and is located at the second surface 101B, and a solder resist layer 105 covers the second surface 101B and exposes the first conductive pad 104 for subsequent placement of a solder connection 106 on the first conductive pad 104.

In some comparative examples of the present application, the first conductive Pad 104 is a copper Pad (Cu Pad). In some other comparative examples of the present application, other conductive structures and materials for placing solder connections during semiconductor package fabrication may be selected, but are not limited to such.

In some comparative examples of the present application, the Solder connection 106 may be a Solder Ball (Solder Ball) commonly used in the semiconductor package manufacturing process, or may be other Solder bumps (Solder Bump) commonly used in the semiconductor package manufacturing process. It is noted that the semiconductor package 10A (as well as the semiconductor packages 10B, 10C, and 10D described below) may be applied as a complete and separate functional product or structural unit when not mounted on the carrier 20A. For example, but not limited to, a memory chip, a processor chip, or other functional chips.

Returning to fig. 1, as shown therein, the carrier 20A includes a substrate 201 and a second conductive pad 202 at a surface of the substrate 201. In some comparative examples of the present application, the substrate 201 also includes a circuit portion to which the second conductive pad 202 belongs. In some comparative examples of the present application, the second conductive pad 202 is a copper pad.

In some comparative examples of the present application, the carrier 20A may also be applied as a complete and separate functional product or structural unit. For example, the carrier 20A may be a Printed Circuit Board (PCB). In some comparative examples of the present application, the carrier 20A may also be other circuit units or structures for mounting the semiconductor package structure 10A (as well as the

semiconductor package structures

10B, 10C, and 10D described below).

Specifically, when the semiconductor package 10A is mounted to the carrier 20A, a portion of the solder connection 106 remote from the substrate 101 is disposed on the second conductive pad 202 in the carrier 20A and electrically connected with the carrier 20A. In order to enhance the reliability of the connection between the semiconductor package 10A and the carrier 20A, the space between the substrate 101 and the substrate 201 is filled with the underfill 120. In some comparative examples of the present application, the underfill 120 may be an epoxy resin composition (EMC), but is not limited thereto. In addition, a filling method of dispensing the semiconductor package 10A after singulation (singulation) is used for filling. After the filling is completed, the filler 120 is cured after being baked by a high temperature, and the formed underfill layer fills the space between the semiconductor package 10A and the carrier 20A (including the space between the solder connections 106) to completely wrap the solder connections 106.

In some embodiments of the present application, another implementation different from the comparative example is provided. As shown in fig. 2, a schematic cross-sectional structure of a semiconductor package structure 10B is provided.

Compared to the semiconductor package 10A in fig. 1, the semiconductor package 10B in fig. 2 further includes a second sealing body 107.

Wherein the second encapsulant 107 contacts only the portion of the solder connection 106 adjacent to the second surface 101B of the substrate 101, which may improve the SJR performance of the solder connection 106, as will be described in detail below.

For example, in some embodiments of the present application, the solder connection 106 includes a first portion 106A and a second portion 106B, wherein the first portion 106A is adjacent to the second surface 101B of the substrate 101 and the second portion 106B is distal from the second surface 101B of the substrate 101 relative to the first portion 106A; the second seal 107 is in contact with the first portion 106A of the solder connection 106, while exposing the second portion 106B of the solder connection 106. In some embodiments of the present application, the boundary of the portion of the second encapsulant 107 in contact with the solder connections 106 and the exposed portion may be a Medium Height (e.g., a Medium Height line L1 in fig. 3A and 3B) of the solder connections 106, which in some embodiments of the present application is the Height at which the widest portion of the solder connections 106 (e.g., solder balls) is located without being affected by external forces. In some other embodiments of the present application, the portions of the second encapsulant 107 in contact with and exposed to the solder connections 106 may be selected to best enhance the SJR performance of the solder connections 106, as the case may be.

Fig. 3A and 3B are enlarged views of a dotted line region a of the semiconductor package 10B in fig. 2.

As shown in fig. 3A, in some embodiments of the present application, the portion of the second seal 107 between the two solder connections 106 has a curvilinear shape. In some embodiments of the present application, the curvilinear shape is a concave shape (e.g., a corrugated shape), and the highest portion of the second encapsulant 107 (i.e., the lowest portion of the second encapsulant 107 in fig. 3A) is the portion that contacts the solder connections 106 at an intermediate height (dashed line L1).

As shown in fig. 3B, in some embodiments of the present application, the portion of the second seal 107 between the two solder connections 106 has a substantially flat shape, i.e., a substantially flat surface. In some embodiments of the present application, the horizontal line of the highest plane of the second seal 107 (i.e., the lowest portion of the second seal 107 in fig. 3B) is flush with the mid-height of the solder connections 106 (dashed line L1).

It should be noted that the surface shape of the second sealing body 107 is determined by two forming factors, i.e., a thin film in a manufacturing tool (hereinafter, the manufacturing tool 30 and the soft film 302) and shape trimming using plasma in the process of forming the second sealing body 107, and may be selected according to actual conditions to improve the SJR performance as much as possible. Details will be described later.

Fig. 4A and 4B are partial schematic structural views of a semiconductor package 10B according to some embodiments of the present application. In some embodiments of the present application, the second seal 107 is applied to the solder resist layer 105. In some embodiments, as shown in fig. 4A, when the opening exposed between the solder resist layers 105 is large and the second conductive pad 104 is exposed from the opening, the second sealing body 107 is in contact with the second conductive pad 104. In other embodiments, as shown in fig. 4B, the second seal 107 is free of contact with the second conductive pad 104 when no opening is exposed between the solder resist layer 105 and the solder connector 10, i.e., the opening is sealed by the solder connector without exposing the second conductive pad 104. For the above two cases, the selection can be performed according to actual requirements, and details are not described here.

Fig. 5A-5E are schematic illustrations of fabrication to form the second seal 107 in some embodiments of the present application. As shown in fig. 5A, the manufacturing tool 30 for manufacturing and forming the second sealing body 107 includes a holding portion 301 and a soft film (film)302 which are oppositely arranged, wherein the soft film 302 is operated close to the substrate 101 and the solder connection member 106 by the holding portion 301. At this time, the second sealing body 107 (viscous fluid) is not injected between the surface 101B of the substrate 101 and the flexible film. Next, as shown in fig. 5B, the soft film 302 is attached to the adjacent solder connections 106, and due to the conformal property, the shape of the soft film 302 between the solder connections 106 is a curved shape (e.g., a wave shape) and serves as a temporary structure for limiting the flow of the second sealing body 107 (viscous fluid). Next, the second sealing body 107 (viscous fluid) is injected between the surface 101B of the substrate 101 and the flexible film, and the second sealing body 107 is restricted by the flexible film 302, thereby generating a curved shape (for example, a wave shape) between the adjacent solder connection members 106. As shown in fig. 5C, after the second sealing body 107 is semi-cured, the semiconductor package 10B is separated from the manufacturing tool 30, and the surface of the second sealing body 107 has a curved shape. The second encapsulant 107 is then fully cured by baking, which may be selected to be 100 ℃ for example, since the baking temperature is lower than the high temperature processing temperature in the preceding manufacturing steps, and thus does not damage the semiconductor package. The height of the cured second encapsulant 107 between adjacent solder connections 106 can be determined by adjusting the degree of conformability of the flexible film 30 of fig. 5B. In some embodiments of the present application, the height of the second seal 107 between adjacent solder connections 106 may be significantly higher than the mid-height L1 of the solder connections 106, as shown in FIG. 5C. When the height of the second seal 107 between adjacent solder connections 106 is significantly greater than the median height L1 of the solder connections 106, a plasma (plasma) trim may optionally follow to form the second seal 107 topography of FIG. 5E. In some embodiments of the present application, the height of the second seal 107 between adjacent solder connections 106 may be at an intermediate height L1 of the solder connections 106, as shown in fig. 5D.

In fig. 5E, the portion of the second sealing body 107 between the two solder connections 106 has a substantially flat shape after plasma trimming, and the horizontal line of the uppermost plane of the second sealing body 107 (i.e., the uppermost portion of the second sealing body 107 in fig. 5E) is flush with the middle height of the solder connections 106 (dashed line L1).

The height and shape of the second sealing body 107 are not limited to those described above, and may be selected in accordance with actual circumstances so as to optimally improve the SJR performance.

Fig. 6 is a cross-sectional structure diagram of a semiconductor package structure 200 according to some embodiments of the present application. The semiconductor package structure 200 includes a semiconductor package 10B and a carrier 20A, and it should be specifically noted that the underfill 120 is not included in the semiconductor package structure 200. When the semiconductor package structure 10B is disposed on the carrier 20A, a space is formed between the second seal 107 and the substrate 201 of the carrier 20A.

In addition, the semiconductor package structure 10B may be applied as a complete and separate functional product or structural unit when not mounted on the carrier 20A. For example, but not limited to, a memory chip, a processor chip, or other functional chips.

Fig. 7A is a partial structural schematic view of a semiconductor package structure in some comparative examples of the present application that does not include the second sealing body 107. Fig. 7B is a schematic view of fig. 7A scanned by a scanning electron microscope. In the structure of fig. 7B, the maximum Creep Strain (Creep Strain) region (i.e., the region where the crack C1 is easily formed) of the solder connector 106 is close to the first conductive pad 104, and the solder connector 106 (e.g., the solder ball) is easily separated from the first conductive pad 104 after forming the breaking lines, falls off and the like to lose the electrical connection due to the difference between the solder connector 106 (e.g., the solder ball) and the first conductive pad 104 (e.g., the copper pad) close to the first conductive pad 104.

Fig. 7C is a partial structural schematic view of a semiconductor package structure having the second sealing body 107 in some embodiments of the present application. Fig. 7D is a schematic view of fig. 7C scanned by a scanning electron microscope. In fig. 7C, the solder connection 106 has a necking portion (necking portion)107N at a contact position with the lowermost end of the second sealing body 107, and the necking portion 107N may be a region between the first portion 106A and the second portion 106B of the solder connection 106, for example, in the vicinity of the middle height line of the solder connection 106. As shown in fig. 7D, the region of maximum Creep Strain (Creep Strain) of the solder connection 106 (i.e., the region susceptible to crack C2) changes to the necked down portion 107N of the solder connection 106 after the addition of the second encapsulant 107, i.e., the location where the solder connection 106 meets the lowermost end of the second encapsulant 107 (e.g., the region adjacent to the intermediate height line L1). In the structure of fig. 7D, even if the breaking lines are formed as described above, since the neck portion 107N of the solder connection 106 has a wider width than the region of maximum Creep Strain (Creep Strain) of fig. 7B, the conductive performance of the solder connection 106 can be effectively ensured without interrupting the electrical connection. It is noted that the necked portion 107N of the solder connection 106 is located at the mid-Height (Medium Height) of the solder connection 106 in some embodiments of the present application, even though the necked portion 107N is not the area where the solder connection 106 has the largest width.

In the semiconductor package structure 100 of fig. 1, the package 10A and the carrier 20A are combined by dispensing to form the underfill 120. In the semiconductor package structure 200 of fig. 6, the second encapsulant 107 layer is formed to improve the SJR performance of the semiconductor package structure 200, and at the same time, the underfill 120 is not required, and the semiconductor packages 10B are not required to be subjected to continuous dispensing one by one, thereby reducing the overall cost of the semiconductor package structure 200 and increasing the yield Per Hour (Unit Per Hour, UPH). The above-described semiconductor package 200 with higher SJR performance and lower manufacturing cost may be very competitive in, for example, an automotive application scenario.

Fig. 8 is a schematic cross-sectional view of a semiconductor package 10C according to some comparative examples of the present application.

As shown in fig. 8, the semiconductor package 10C includes a substrate 101, a die 102, a first sealing body 103, and a solder connection 106. Wherein the substrate 101 has a first surface 101A and a second surface 101B opposite the first surface 101A, the die 102 is disposed on the first surface 101A of the substrate 101, the first seal 103 encapsulates the die 102, and the solder connection 106 is disposed on the first conductive pad 104 at the second surface 101B. Further, the semiconductor package 10C further includes an opening 108 penetrating the substrate 101, a bonding wire 109, and a sealing body 110. Wherein the bond wire 109 is electrically coupled to the die 102 and the second surface 101A of the substrate 101 and the seal 110 encapsulates the bond wire 109. In fig. 8, the seal 110 is not in contact with the solder connections 106.

In some comparative examples of the present application, the opening 108 exposes an active surface of the die 102.

In some comparative examples of the present application, the semiconductor package 10C in fig. 8 is a Board On Chip (BOC) package structure. When the semiconductor package 10C is combined with a carrier (not shown, such as the carrier 20A), it is still necessary to fill the space between the semiconductor package 10C and the carrier with the underfill 120, in the same manner as the semiconductor package structure 100 is filled.

Fig. 9 is a schematic cross-sectional view of a semiconductor package 10D according to some embodiments of the present disclosure.

As shown in fig. 9, the semiconductor package 10D includes a substrate 101, a die 102, a first sealing body 103, a solder connection 106, and a second sealing body 107. Wherein the substrate 101 has a first surface 101A and a second surface 101B opposite the first surface 101A, the die 102 is disposed on the first surface 101A of the substrate 101, the first seal 103 encapsulates the die 102, the solder connection 106 is disposed on the first conductive pad 104 at the second surface 101B, and the second seal 107 contacts a first portion of the solder connection 106 adjacent the second surface 101B (e.g., the first portion 106A of the solder connection 106 in the semiconductor package 10B) and exposes a second portion of the solder connection 106 distal the second surface 101A (e.g., the second portion 106B of the solder connection 106 in the semiconductor package 10B). In addition, the semiconductor package 10D further includes an opening 108 penetrating the substrate 101, a bonding wire 109, and a second sealing body 107. Wherein the bonding wire 109 is electrically coupled to the die 102 and the second surface 101A of the substrate, the second encapsulant 107 further encapsulates the bonding wire 109.

The semiconductor package 10D in fig. 9 is a Board On Chip (BOC) package structure. In contrast to the comparative example of fig. 8, the second encapsulant 107 in the embodiment of fig. 9 contacts the sides of the solder connections 106 while encapsulating the bond wires 109 to improve the SJR performance of the semiconductor package structure, as previously described for the embodiment of semiconductor package 10B.

Fig. 10 is a cross-sectional structure diagram of a semiconductor package structure 300 according to some embodiments of the present application. The semiconductor package structure 300 includes the semiconductor package 10D in fig. 9 and the carrier 20A, wherein the underfill 120 is not disposed between the semiconductor package 10D and the carrier 20A.

Because the semiconductor package 10D employs the second encapsulant 107 formed on the sides of the solder connections 106 and no underfill 120 is employed between the semiconductor package 10D and the carrier 20A, the same technical effect as previously described for the semiconductor package 200 is that the SJR performance of the semiconductor package 300 is improved, while the overall cost of the semiconductor package 200 is reduced and the hourly production UPH is increased. In addition, since the semiconductor package structure 10D employs a BOC package structure as compared with the semiconductor package structure 10B, the bonding wires 109 can be directly sealed by the second sealing member 107, thereby saving process steps and further improving UPH.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims

1. A semiconductor package structure, comprising:

a substrate having a first surface and a second surface opposite the first surface;

a die disposed on the first surface of the substrate;

a first seal encapsulating the die;

a solder connection at the second surface, the solder connection comprising a first portion proximate the second surface and a second portion distal the second surface; and

a second seal in contact with the first portion of the solder connection and exposing the second portion of the solder connection.

2. The semiconductor package structure of claim 1, wherein the solder connection comprises a neck portion between the first portion and the second portion.

3. The semiconductor package structure of claim 1, wherein a lowest portion of the second encapsulant extends to an intermediate height of the solder connection.

4. The semiconductor package structure of claim 1, further comprising a first conductive pad at the second surface of the substrate, the second seal being in contact with the first conductive pad.

5. The semiconductor package structure of claim 1, further comprising a first conductive pad at the second surface of the substrate, the second seal being free of contact with the first conductive pad.

6. The semiconductor package structure of claim 1, wherein a portion of the second seal between adjacent solder connections has a curvilinear shape.

7. The semiconductor package structure of claim 1, wherein a portion of the second seal between adjacent solder connections has a flat shape.

8. The semiconductor package structure of any one of claims 1-7, further comprising a carrier having a second conductive pad, wherein the solder connection electrically connects the substrate with the second conductive pad.

9. The semiconductor package structure of any one of claims 1-7, further comprising:

an opening through the substrate; and

a bonding wire electrically coupled with the die and the second surface of the substrate;

wherein the second encapsulant further encapsulates the bond wire.

10. The semiconductor package structure of claim 9, wherein the opening is to expose an active surface of the die.