CN213783133U - Charge bleeding circuit - Google Patents
Charge bleeding circuit Download PDFInfo
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- CN213783133U CN213783133U CN202023279732.9U CN202023279732U CN213783133U CN 213783133 U CN213783133 U CN 213783133U CN 202023279732 U CN202023279732 U CN 202023279732U CN 213783133 U CN213783133 U CN 213783133U
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- 230000000740 bleeding effect Effects 0.000 title claims description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 63
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract 2
- 150000004706 metal oxides Chemical class 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 238000012360 testing method Methods 0.000 description 14
- 238000004146 energy storage Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Abstract
The utility model provides a charge bleeder circuit, which comprises a switch, a first triode, a second triode, a first MOS (metal oxide semiconductor) tube, a first resistor, a second MOS tube, a first capacitor and a second capacitor; the switch is connected with a power supply and a base electrode of the first triode, a collector electrode of the first triode is connected with the power supply and a base electrode of the second triode, a collector electrode of the second triode is connected with the power supply and a grid electrode of the first MOS tube, and a source electrode of the first MOS tube is connected with the power supply; the drain electrode of the first MOS tube is connected with one end of the first resistor, one end of the first capacitor and one end of the second capacitor, the other end of the first resistor is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the switch, and the emitting electrodes of the first triode and the second triode and the source electrode of the second MOS tube are grounded. The utility model discloses when closed switch, first MOS pipe switches on, and the second MOS pipe ends, and first resistance is in off-working condition, has avoided first resistance to produce and has consumed the flow, has prolonged the working life of first resistance.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to charge bleeder circuit.
Background
In the prior art, the electric charge stored in the energy storage capacitor is discharged through the resistor, and in order to realize the rapid discharge of the energy storage capacitor, the resistor with a smaller resistance value is generally selected, but the resistor is always in a working state no matter whether the resistor discharges the electric charge stored in the energy storage capacitor or not, and the resistance value of the resistor is smaller, so that on one hand, when the resistor is always in a large-current working state, the current consumption of the resistor is greatly increased, and the service life of the resistor is shortened; on the other hand, if the resistor uses large current for a long time, the resistance value of the resistor is increased, and the charge stored in the energy storage capacitor cannot be discharged quickly.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to be in operating condition in order to overcome among the prior art resistance always, lead to resistance to produce consume the defect of flowing and reducing resistance working life, provide a charge bleeder circuit.
The utility model discloses an above-mentioned technical problem is solved through following technical scheme:
the utility model provides a charge bleeder circuit, the bleeder circuit includes switch, first triode, second triode, first MOS pipe, first resistance, second MOS pipe, first electric capacity and second electric capacity;
one end of the switch is electrically connected with an external power supply and the base electrode of the first triode respectively, the other end of the switch is grounded, the emitting electrode of the first triode is grounded, the collecting electrode of the first triode is electrically connected with the external power supply and the base electrode of the second triode respectively, the collecting electrode of the second triode is electrically connected with the external power supply and the grid electrode of the first MOS tube respectively, the emitting electrode of the second triode is grounded, and the source electrode of the first MOS tube is electrically connected with the external power supply;
the drain electrode of the first MOS tube is respectively electrically connected with one end of the first resistor, one end of the first capacitor and one end of the second capacitor, the other end of the first capacitor and the other end of the second capacitor are grounded, the other end of the first resistor is electrically connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is electrically connected with one end of the switch, and the source electrode of the second MOS tube is grounded.
Preferably, the bleeder circuit further comprises a second resistor, a third resistor and a fourth resistor;
the second resistor is connected in series between the external power supply and the switch;
the third resistor is connected in series between the external power supply and the collector of the first triode;
the fourth resistor is connected in series between the external power supply and the collector of the second triode.
Preferably, the bleeder circuit further comprises a third capacitor and a fourth capacitor;
one end of the third capacitor is electrically connected with one end of the switch, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is electrically connected with the base electrode of the second triode, and the other end of the fourth capacitor is grounded.
Preferably, the first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor.
Preferably, the first triode and the second triode are both NPN-type triodes.
Preferably, the resistance value of the first resistor is less than 100k Ω.
Preferably, the resistances of the second resistor, the third resistor and the fourth resistor are all 100k Ω.
Preferably, the capacitance value of the first capacitor is 100uf or 220 uf.
Preferably, the capacitance value of the second capacitor is 100uf or 220 uf.
Preferably, the capacitance values of the third capacitor and the fourth capacitor are both 10 uf.
The utility model discloses an actively advance the effect and lie in:
the utility model discloses a charge bleeder circuit through the switch in the closed bleeder circuit for first MOS pipe switches on, and the second MOS pipe ends, and first resistance is in off-working condition, has avoided first resistance to produce and has consumed the flow, has also prolonged the working life of first resistance simultaneously.
Drawings
Fig. 1 is a circuit diagram of a charge bleeding circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be more clearly and completely described below by way of embodiments with reference to the accompanying drawings, and the description of the embodiments is provided to help understanding the present invention, but the present invention is not limited thereto.
As shown in fig. 1, the present embodiment provides a charge draining circuit, which includes a switch S1, a first transistor Q1, a second transistor Q2, a first MOS transistor Q3, a first resistor R1, a second MOS transistor Q4, a first capacitor C1, a second capacitor C2, a second resistor R2, a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4.
One end of the switch S1 is respectively electrically connected with an external Power source Power and the base electrode of the first triode Q1, the other end of the switch S1 is grounded, the second resistor R2 is connected between the external Power source Power and the switch S1 in series, one end of the third capacitor C3 is electrically connected with one end of the switch S1, the other end of the third capacitor C3 is grounded, the emitter electrode of the first triode Q1 is grounded, the collector electrode of the first triode Q1 is respectively electrically connected with the external Power source Power and the base electrode of the second triode Q2, and the third resistor R3 is connected between the external Power source Power and the collector electrode of the first triode Q1 in series; one end of a fourth capacitor C4 is electrically connected with the base electrode of the second triode Q2, and the other end of the fourth capacitor C4 is grounded; a collector of the second triode Q2 is electrically connected with an external Power source Power and a gate of the first MOS transistor Q3, respectively, and the fourth resistor R4 is connected in series between the external Power source Power and the collector of the second triode Q2; the emitter of the second transistor Q2 is grounded, and the source of the first MOS transistor Q3 is electrically connected to the external Power source.
The drain of the first MOS transistor Q3 is electrically connected to one end of the first resistor R1, one end of the first capacitor C1 and one end of the second capacitor C2, the other end of the first capacitor C1 and the other end of the second capacitor C2 are both grounded, the other end of the first resistor R1 is electrically connected to the drain of the second MOS transistor Q4, the gate of the second MOS transistor Q4 is electrically connected to one end of the switch S1, and the source of the second MOS transistor Q4 is grounded.
In this embodiment, the first MOS transistor Q3 is a PMOS transistor, and the second MOS transistor Q4 is an NMOS transistor; the first transistor Q1 and the second transistor Q2 are NPN transistors.
In this embodiment, the resistances of the second resistor R2, the third resistor R3 and the fourth resistor R4 are all 100k Ω; the capacitance value of the first capacitor C1 is 100uf or 220uf, and the capacitance value of the second capacitor C2 is also 100uf or 220 uf; preferably, the capacitance values of the first capacitor C1 and the second capacitor C2 are the same. The capacitance values of the third capacitor C3 and the fourth capacitor C4 are both 10 uf.
The charge bleeding circuit in this embodiment may be applied to a test fixture for testing a communication module, or may be applied to other devices to be tested, which is not specifically limited herein. When the charge bleeder circuit is applied to a test fixture of a test communication module or other devices to be tested, the test fixture of the test communication module and a power supply end Vbat of the other devices to be tested are electrically connected with the drain electrode of the first MOS transistor Q3.
In this embodiment, when the switch S1 is closed, the test point 1 is at a logic low level, at this time, the first transistor Q1 is turned off (or when the static voltage Vbe of the first transistor Q1 is less than 0.7V, that is, Vbe <0.7V, the first transistor Q1 is turned off), the test point 2 is at a logic high level, the second transistor Q2 is turned on (or when the static voltage Vbe of the second transistor Q2 is greater than 0.7V, that is, Vbe >0.7V, the second transistor Q2 is turned on), the test point 3 is at a logic low level, the first MOS transistor Q3 is turned on (or when the gate-source voltage Vgs of the first MOS transistor Q3 is less than the threshold voltage Vgsth, that is, that Vgs < Vgsth, the first MOS transistor Q3 is turned on), the external Power supply Power to the DUT normally, and the first capacitor C1 and the second capacitor C2 store charges. When the switch S1 is turned on, because the test point 1 is at a logic low level, the second MOS transistor Q4 is turned off (or when the gate-source voltage Vgs of the second MOS transistor Q4 is smaller than the threshold voltage Vgsth, that is, Vgs < Vgsth, the second MOS transistor Q4 is turned off), and at this time, the first resistor R1 is in an off state, which prevents the first resistor R1 from generating current consumption, and also prolongs the operating life of the first resistor R1.
When the switch S1 is turned off, the test point 1 is at a logic high level, at which time the first transistor Q1 is turned on (or when the static voltage Vbe of the first transistor Q1 is greater than 0.7V, that is, Vbe >0.7V, the first transistor Q1 is turned on), the test point 2 is at a logic low level, the second transistor Q2 is turned off (or when the static voltage Vbe of the second transistor Q2 is less than 0.7V, that is, Vbe <0.7V, the second transistor Q2 is turned off), the test point 3 is at a logic high level, the first MOS transistor Q3 is turned off (or when the gate-source voltage Vgs of the first MOS transistor Q3 is greater than the threshold voltage Vgsth, that is, Vgs > vgth, the first MOS transistor Q3 is turned off), and at which time the power supply to the DUT is turned off. When the switch S1 is turned off, since the test point 1 is at a logic high level, the second MOS transistor Q4 is turned on (or when the gate-source voltage Vgs of the second MOS transistor Q4 is greater than the threshold voltage Vgsth, i.e., Vgs > Vgsth, the second MOS transistor Q4 is turned on), and at this time, the first resistor R1 and the second MOS transistor Q4 can rapidly drain the charges stored on the first capacitor C1 and the second capacitor C2. In this embodiment, the smaller the resistance of the first resistor R1 is less than 100k Ω, the faster the first resistor R1 and the second MOS transistor Q4 can drain the charges stored in the first capacitor C1 and the second capacitor C2.
In the embodiment, by closing the switch S1 in the charge leakage circuit, the first MOS transistor Q3 is turned on, the second MOS transistor Q4 is turned off, and the first resistor R1 is in an off state, so that current consumption of the first resistor R1 is avoided, and the service life of the first resistor R1 is also prolonged; then, by disconnecting the switch S1 in the charge bleeding circuit, the first MOS transistor Q3 is turned off, the second MOS transistor Q4 is turned on, and charges stored in the first capacitor C1 and the second capacitor C2 can be bled quickly through the first resistor R1 and the second MOS transistor Q4, so that the problem that the first resistor R1 is always in a large-current working state, the resistance value is increased, and the charges stored in the first capacitor C1 and the second capacitor C2 cannot be bled quickly is solved.
Although specific embodiments of the present invention have been described above, it will be understood by those skilled in the art that this is by way of example only and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and the principles of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (10)
1. The charge bleeder circuit is characterized by comprising a switch, a first triode, a second triode, a first MOS (metal oxide semiconductor) tube, a first resistor, a second MOS tube, a first capacitor and a second capacitor;
one end of the switch is electrically connected with an external power supply and the base electrode of the first triode respectively, the other end of the switch is grounded, the emitting electrode of the first triode is grounded, the collecting electrode of the first triode is electrically connected with the external power supply and the base electrode of the second triode respectively, the collecting electrode of the second triode is electrically connected with the external power supply and the grid electrode of the first MOS tube respectively, the emitting electrode of the second triode is grounded, and the source electrode of the first MOS tube is electrically connected with the external power supply;
the drain electrode of the first MOS tube is respectively electrically connected with one end of the first resistor, one end of the first capacitor and one end of the second capacitor, the other end of the first capacitor and the other end of the second capacitor are grounded, the other end of the first resistor is electrically connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is electrically connected with one end of the switch, and the source electrode of the second MOS tube is grounded.
2. The charge bleeding circuit of claim 1, wherein the bleeding circuit further comprises a second resistor, a third resistor, and a fourth resistor;
the second resistor is connected in series between the external power supply and the switch;
the third resistor is connected in series between the external power supply and the collector of the first triode;
the fourth resistor is connected in series between the external power supply and the collector of the second triode.
3. The charge bleeding circuit of claim 1, wherein the bleeding circuit further comprises a third capacitance and a fourth capacitance;
one end of the third capacitor is electrically connected with one end of the switch, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is electrically connected with the base electrode of the second triode, and the other end of the fourth capacitor is grounded.
4. The charge bleeding circuit as claimed in claim 1, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.
5. The charge bleed circuit of claim 1, wherein the first transistor and the second transistor are both NPN transistors.
6. The charge bleed circuit of claim 1, wherein the first resistor has a resistance of less than 100k Ω.
7. The charge bleeding circuit of claim 2, wherein the second resistor, the third resistor, and the fourth resistor are each 100k Ω.
8. The charge bleed circuit of claim 1, wherein the first capacitor has a capacitance of 100uf or 220 uf.
9. The charge bleed circuit of claim 1, wherein the second capacitor has a capacitance of 100uf or 220 uf.
10. The charge bleed circuit of claim 3, wherein the capacitance values of the third and fourth capacitors are each 10 uf.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023279732.9U CN213783133U (en) | 2020-12-30 | 2020-12-30 | Charge bleeding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023279732.9U CN213783133U (en) | 2020-12-30 | 2020-12-30 | Charge bleeding circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213783133U true CN213783133U (en) | 2021-07-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202023279732.9U Active CN213783133U (en) | 2020-12-30 | 2020-12-30 | Charge bleeding circuit |
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| Country | Link |
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| CN (1) | CN213783133U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512964A (en) * | 2021-12-14 | 2022-05-17 | 上海芯纬科技有限公司 | Energy storage capacitor protection circuit for electronic detonator |
-
2020
- 2020-12-30 CN CN202023279732.9U patent/CN213783133U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512964A (en) * | 2021-12-14 | 2022-05-17 | 上海芯纬科技有限公司 | Energy storage capacitor protection circuit for electronic detonator |
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