CN213522456U

CN213522456U - Intelligent lighthouse

Info

Publication number: CN213522456U
Application number: CN202022560129.1U
Authority: CN
Inventors: 谢利平
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-11-09
Filing date: 2020-11-09
Publication date: 2021-06-22
Anticipated expiration: 2030-11-09

Abstract

The utility model relates to an intelligence beacon, its technical scheme main points are: the method comprises the following steps: a network interface for coupling to a network; the input conversion module is used for converting the network signal into a serial port signal; the signal processing module is used for generating a control signal according to the serial port signal; at least one relay module for controlling light switching; the driving module is used for controlling each relay module according to the control signal; the network interface is connected with the input conversion module; the input conversion module is connected with the signal processing module; the signal processing module is connected with the driving module; the driving module is respectively connected with at least one relay module; this application has the advantage that need not go to temple also can be for the Buddha.

Description

Intelligent lighthouse

Technical Field

The utility model relates to a lighting apparatus technical field, more specifically say, it relates to an intelligence beacon.

Background

At present, the people usually need go to the temple in person when the celebration, obtain the fragrant lamp through giving temple incense fire money, and then the celebration face is crept, and this kind of way of crept is comparatively troublesome, and to old people, go to the temple comparatively troublesome, consequently provides a not need to go to the temple also can the fragrant lamp of crept and has become the technical problem that technical staff in this field awaited a urgent need to solve.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art exists, the utility model aims to provide an intelligence beacon has the advantage that need not go to the temple also can be used for the Buddha.

The above technical purpose of the present invention can be achieved by the following technical solutions: an intelligent lighthouse, comprising: a network interface for coupling to a network; the input conversion module is used for converting the network signal into a serial port signal; the signal processing module is used for generating a control signal according to the serial port signal; at least one relay module for controlling light switching; the driving module is used for controlling each relay module according to the control signal; the network interface is connected with the input conversion module; the input conversion module is connected with the signal processing module; the signal processing module is connected with the driving module; the driving module is respectively connected with at least one relay module.

Optionally, the input conversion module includes: the circuit comprises a first chip, a second chip, a first resistor and a second resistor; the 1 st end of the second chip is grounded through a first resistor, and the 1 st end of the second chip is connected with the signal processing module; the 4 th end of the second chip is grounded through the second resistor, and the 4 th end of the second chip is connected with the signal processing module; the 5 th end of the second chip is grounded; the 6 th end of the second chip is connected with the 2 nd end of the first chip; the 7 th end of the second chip is connected with the 3 rd end of the first chip; the 8 th end of the second chip is connected with the signal processing module; and the 1 st end of the first chip is connected with the network interface.

Optionally, the first chip is an RS485 chip.

Optionally, the second chip is an MX1348 chip.

Optionally, the signal processing module includes: the first chip comprises a first chip, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first crystal oscillator and a second crystal oscillator; the 1 st end of the third chip, the 24 th end of the third chip, the 36 th end of the third chip and the 48 th end of the third chip are respectively connected with the input conversion module; the 3 rd end of the third chip is grounded through a first capacitor; the 3 rd end of the third chip is grounded through the first crystal oscillator and the second capacitor in sequence; the 4 th end of the third chip is grounded through a second capacitor; the 5 th end of the third chip is grounded through a third capacitor; the 5 th end of the third chip is grounded through the second crystal oscillator and the fourth capacitor in sequence; the 6 th end of the third chip is grounded through a fourth capacitor; the 23 rd end of the third chip, the 35 th end of the third chip and the 47 th end of the third chip are all grounded; the 30 th end of the third chip and the 31 st end of the third chip are respectively connected with the input conversion module; the 10 th end of the third chip, the 11 th end of the third chip, the 12 th end of the third chip, the 13 th end of the third chip, the 14 th end of the third chip, the 15 th end of the third chip, the 16 th end of the third chip and the 17 th end of the third chip are all connected with the driving module; and the 18 th end of the third chip, the 19 th end of the third chip, the 20 th end of the third chip, the 39 th end of the third chip, the 40 th end of the third chip, the 41 th end of the third chip, the 42 th end of the third chip and the 43 th end of the third chip are respectively used for being connected with the driving modules in a one-to-one correspondence manner.

Optionally, the third chip is an STM32F103CBT6 chip.

Optionally, the driving module includes: a fourth chip and a fifth chip; the 1 st end of the fourth chip and the 10 th end of the fourth chip are respectively grounded; the 2 nd end of the fourth chip, the 3 rd end of the fourth chip, the 4 th end of the fourth chip, the 5 th end of the fourth chip, the 6 th end of the fourth chip, the 7 th end of the fourth chip, the 8 th end of the fourth chip, the 9 th end of the fourth chip and the 11 th end of the fourth chip are respectively connected with the signal processing module; the 12 th end of the fourth chip is connected with the 1 st end of the fifth chip; the 13 th end of the fourth chip is connected with the 2 nd end of the fifth chip; the 14 th end of the fourth chip is connected with the 3 rd end of the fifth chip; the 15 th end of the fourth chip is connected with the 4 th end of the fifth chip; the 16 th end of the fourth chip is connected with the 5 th end of the fifth chip; the 17 th end of the fourth chip is connected with the 6 th end of the fifth chip; the 18 th end of the fourth chip is connected with the 7 th end of the fifth chip; the 19 th end of the fourth chip is connected with the 8 th end of the fifth chip; the 10 th end of the fifth chip is connected with the input conversion module; and the 11 th end of the fifth chip, the 12 th end of the fifth chip, the 13 th end of the fifth chip, the 14 th end of the fifth chip, the 15 th end of the fifth chip, the 16 th end of the fifth chip, the 17 th end of the fifth chip and the 18 th end of the fifth chip are respectively used for being connected with the relay modules in a one-to-one correspondence manner.

Optionally, the fourth chip is a 74HC573D chip.

Optionally, the fifth chip is a ULN2803A chip.

Optionally, the relay module includes: the LED driving circuit comprises a first relay, a third resistor, a fourth resistor, a first LED and a second LED; the 1 st end of the first relay is connected with the driving module; the 2 nd end of the first relay is grounded; the 3 rd end of the first relay is connected with the input conversion module; the 4 th end of the first relay is grounded through the third resistor and the first LED in sequence; and the 5 th end of the first relay is grounded through the fourth resistor and the second LED in sequence.

To sum up, the utility model discloses following beneficial effect has: the network interface receives a signal of the cloud and converts the signal into a 485 signal through an RS485 chip, the 485 signal generates a serial port signal through an MX1348 chip, the serial port signal is processed through an STM32F103CBT6 chip to generate a control signal, the control signal saves the level state of the serial port signal through a 74HC573D chip and controls a first relay to correspondingly switch on a first LED or a second LED under the action of an ULN2803A chip, and then the Buddha figure can be served or extinguished; thereby can not need going to temple also can be worded for the buddha.

Drawings

Fig. 1 is a circuit block diagram of the present invention;

fig. 2 is a schematic circuit diagram of the input conversion module and the signal processing module according to the present invention;

fig. 3 is a schematic circuit diagram of the relay module and the driving module according to the present invention;

fig. 4 is a schematic circuit diagram of the driving module according to the present invention.

In the figure: 1. a network interface; 2. an input conversion module; 3. a signal processing module; 4. a relay module; 5. a drive module; u1, a first chip; u2, a second chip; r1, a first resistor; r2, a second resistor; u3, third chip; c1, a first capacitance; c2, a second capacitor; c3, a third capacitance; c4, a fourth capacitance; y1, a first crystal oscillator; y2, second crystal oscillator; u4, a fourth chip; u5, a fifth chip; k1, a first relay; r3, third resistor; r4, fourth resistor; d1, a first LED; d2, a second LED.

Detailed Description

In order to make the objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Several embodiments of the invention are given in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically connected or connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature. The terms "vertical," "horizontal," "left," "right," "up," "down," and the like are used for descriptive purposes only and are not intended to indicate or imply that the referenced device or element must be in a particular orientation, constructed and operated, and therefore should not be construed as limiting the present invention.

The present invention will be described in detail with reference to the accompanying drawings and examples.

The utility model provides an intelligence beacon, as shown in figure 1, include: a network interface 1 for coupling a network; the input conversion module 2 is used for converting the network signal into a serial port signal; the signal processing module 3 is used for generating a control signal according to the serial port signal; at least one relay module 4 for controlling light switching; a driving module 5 for controlling each relay module 4 according to the control signal; the network interface 1 is connected with the input conversion module 2; the input conversion module 2 is connected with the signal processing module 3; the signal processing module 3 is connected with the driving module 5; the driving module 5 is respectively connected with at least one relay module 4. Network interface 1 receives external network signal after, with network signal transmission to input conversion module 2, input conversion module 2 converts network signal into serial ports signal and sends for signal processing module 3, signal processing module 3 handles serial ports signal and generates control signal and sends for each drive module 5, each drive module 5 corresponds each relay module 4 of control according to control signal, each relay module 4 switches light according to the signal of telecommunication of drive module 5 transmission, can be after receiving the confession of the people and act on the information, the messenger lights the fragrant lamp that offers the Buddha.

Further, as shown in fig. 2, the input conversion module 2 includes: the circuit comprises a first chip U1, a second chip U2, a first resistor R1 and a second resistor R2; the 1 st end of the second chip U2 is grounded through a first resistor R1, and the 1 st end of the second chip U2 is connected with the signal processing module 3; the 4 th end of the second chip U2 is grounded through a second resistor R2, and the 4 th end of the second chip U2 is connected with the signal processing module 3; the 5 th end of the second chip U2 is grounded; the 6 th end of the second chip U2 is connected with the 2 nd end of the first chip U1; the 7 th end of the second chip U2 is connected with the 3 rd end of the first chip U1; the 8 th end of the second chip U2 is connected with the signal processing module 3; the 1 st end of the first chip U1 is connected to the network interface 1. The first chip U1 is an RS485 chip, and the second chip U2 is an MX1348 chip. The RS485 chip receives the signal sent by the cloud through the network interface 1, converts the signal into a 485 signal and sends the 485 signal to the MX1348 chip, and the MX1348 chip generates a serial signal according to the 485 signal to communicate with the signal processing module 3. And the 8 th end of the MX1348 chip is connected into a live wire.

Optionally, as shown in fig. 2, the signal processing module 3 includes: a third chip U3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first crystal oscillator Y1 and a second crystal oscillator Y2; the 1 st end of the third chip U3, the 24 th end of the third chip U3, the 36 th end of the third chip U3 and the 48 th end of the third chip U3 are respectively connected with the input conversion module 2; the 3 rd terminal of the third chip U3 is grounded through a first capacitor C1; the 3 rd end of the third chip U3 is grounded through the first crystal oscillator Y1 and the second capacitor C2 in sequence; the 4 th end of the third chip U3 is grounded through a second capacitor C2; the 5 th end of the third chip U3 is grounded through a third capacitor C3; the 5 th end of the third chip U3 is grounded through the second crystal oscillator Y2 and the fourth capacitor C4 in sequence; the 6 th end of the third chip U3 is grounded through a fourth capacitor C4; the 23 rd end of the third chip U3, the 35 th end of the third chip U3 and the 47 th end of the third chip U3 are all grounded; the 30 th end of the third chip U3 and the 31 th end of the third chip U3 are respectively connected with the input conversion module 2; the 10 th end of the third chip U3, the 11 th end of the third chip U3, the 12 th end of the third chip U3, the 13 th end of the third chip U3, the 14 th end of the third chip U3, the 15 th end of the third chip U3, the 16 th end of the third chip U3 and the 17 th end of the third chip U3 are all connected with the driving module 5; the 18 th end of the third chip U3, the 19 th end of the third chip U3, the 20 th end of the third chip U3, the 39 th end of the third chip U3, the 40 th end of the third chip U3, the 41 th end of the third chip U3, the 42 th end of the third chip U3 and the 43 th end of the third chip U3 are respectively used for being connected with the driving modules 5 in a one-to-one correspondence manner. The third chip U3 is STM32F103CBT6 chip. The signal processing module 3 adopts MCU as a singlechip of STM32F103CBT6, wherein the 24 th end, the 36 th end and the 48 th end of the STM32F103CBT6 chip are connected with a live wire; the 30 th end of the STM32F103CBT6 chip is connected with the 1 st end of the MX1348 chip; the 31 th end of the STM32F103CBT6 chip is connected with the 4 th end of the MX1348 chip; the 10 th end to the 17 th end of the STM32F103CBT6 chip are connected with each driving module 5; the 18 th end, the 19 th end, the 20 th end, the 39 th end, the 40 th end, the 41 st end, the 42 th end and the 43 th end of the STM32F103CBT6 chip are respectively connected with the driving modules 5 in a one-to-one correspondence manner; in this embodiment, there are 8 driving modules 5, that is, the 18 th end of the STM32F103CBT6 chip is connected to the first driving module 5, the 19 th end of the STM32F103CBT6 chip is connected to the second driving module 5, the 20 th end of the STM32F103CBT6 chip is connected to the third driving module 5, the 39 th end of the STM32F103CBT6 chip is connected to the fourth driving module 5, the 40 th end of the STM32F103CBT6 chip is connected to the fifth driving module 5, the 41 th end of the STM32F103CBT6 chip is connected to the sixth driving module 5, the 42 th end of the STM32F103CBT6 chip is connected to the seventh driving module 5, and the 43 th end of the STM32F103CBT6 chip is connected to the eighth driving module 5; and the 10 th end to the 17 th end of the STM32F103CBT6 chip are connected to the first driving module 5, the second driving module 5, the third driving module 5, the fourth driving module 5, the fifth driving module 5, the sixth driving module 5, the seventh driving module 5, and the eighth driving module 5.

Alternatively, as shown in fig. 3, the driving module 5 includes: a fourth chip U4 and a fifth chip U5; the 1 st end of the fourth chip U4 and the 10 th end of the fourth chip U4 are respectively grounded; the 2 nd end of the fourth chip U4, the 3 rd end of the fourth chip U4, the 4 th end of the fourth chip U4, the 5 th end of the fourth chip U4, the 6 th end of the fourth chip U4, the 7 th end of the fourth chip U4, the 8 th end of the fourth chip U4, the 9 th end of the fourth chip U4 and the 11 th end of the fourth chip U4 are respectively connected with the signal processing module 3; the 12 th end of the fourth chip U4 is connected with the 1 st end of the fifth chip U5; the 13 th end of the fourth chip U4 is connected with the 2 nd end of the fifth chip U5; the 14 th end of the fourth chip U4 is connected with the 3 rd end of the fifth chip U5; the 15 th end of the fourth chip U4 is connected with the 4 th end of the fifth chip U5; the 16 th end of the fourth chip U4 is connected with the 5 th end of the fifth chip U5; the 17 th end of the fourth chip U4 is connected with the 6 th end of the fifth chip U5; the 18 th end of the fourth chip U4 is connected with the 7 th end of the fifth chip U5; the 19 th end of the fourth chip U4 is connected with the 8 th end of the fifth chip U5; the 10 th end of the fifth chip U5 is connected with the input conversion module 2; the 11 th end of the fifth chip U5, the 12 th end of the fifth chip U5, the 13 th end of the fifth chip U5, the 14 th end of the fifth chip U5, the 15 th end of the fifth chip U5, the 16 th end of the fifth chip U5, the 17 th end of the fifth chip U5, and the 18 th end of the fifth chip U5 are respectively used for connecting the relay modules 4 in a one-to-one correspondence. The fourth chip U4 is a 74HC573D chip, and the fifth chip U5 is a ULN2803A chip.

The 74HC573D chip is a latch, and the 2 nd end to the 9 th end of the 74HC573D chip are connected with the 10 th end to the 17 th end of the STM32F103CBT6 chip in a one-to-one correspondence manner; the 11 th end of the 74HC573D chip is correspondingly connected with any one of the 18 th, 19 th, 20 th, 39 th, 40 th, 41 th, 42 th and 43 th ends of the STM32F103CBT6 chip; the 20 th end of the 74HC573D chip is connected with a live wire; after receiving the control signal generated by the STM32F103CBT6 chip, the 2 nd to 9 th terminals of the 74HC573D chip receive the control signal and change the levels of the 12 th to 19 th terminals of the corresponding 74HC573D chip according to the control signal; taking the control signals output from the 10 th end to the 17 th end of the STM32F103CBT6 chip as an example, after the 2 nd end to the 9 th end of the 74HC573D chip receive a high level, the 74HC573D chip keeps a high level state and outputs a high level from the 12 th end to the 19 th end of the 74HC573D chip; if the control signals output from the 10 th to 17 th terminals of the STM32F103CBT6 chip are converted to low level, the 2 nd to 9 th terminals of the 74HC573D chip receive low level and reset the latch, so that the 12 th to 19 th terminals of the 74HC573D chip output low level; and the ULN2803A chip can inhibit jump and avoid the damage of the relay module 4 caused by excessive instantaneous jump of the level. The 1 st end to the 8 th end of the ULN2803A chip are respectively connected with the 12 th end to the 19 th end of the 74HC573D chip in a one-to-one correspondence manner, and the 11 th end to the 18 th end of the ULN2803A chip are respectively connected with the relay modules 4 in a one-to-one correspondence manner; that is, each ULN2803A chip is connected with 8 relay modules 4; the 10 th end of the ULN2803A chip is connected with a live wire; whereas the 74HC573D chip and the ULN2803A chip are each provided with 8 and one-to-one correspondence, so that 64 relay modules 4 are provided in total. Taking a group of 74HC573D chips and a ULN2803A chip as an example, the 11 th end of the ULN2803A chip is connected to the first relay K1 module 4, the 12 th end of the ULN2803A chip is connected to the second relay module 4, the 13 th end of the ULN2803A chip is connected to the third relay module 4, the 14 th end of the ULN2803A chip is connected to the fourth relay module 4, the 15 th end of the ULN2803A chip is connected to the fifth relay module 4, the 16 th end of the ULN2803A chip is connected to the sixth relay module 4, the 17 th end of the ULN2803A chip is connected to the seventh relay module 4, the 18 th end of the ULN2803A chip is connected to the eighth relay module 4, and the level signals received from the 1 st end to the 8 th end of the ULN2803A chip correspond to the high level or low level signals input to the first relay K1 to the eighth relay.

Further, as shown in fig. 3 and 4, the relay module 4 includes: the relay comprises a first relay K1, a third resistor R3, a fourth resistor R4, a first LEDD1 and a second LEDD 2; the 1 st end of the first relay K1 is connected with the driving module 5; the 2 nd end of the first relay K1 is grounded; the 3 rd end of the first relay K1 is connected with the input conversion module 2; the 4 th end of the first relay K1 is grounded through a third resistor R3 and a first LEDD1 in sequence; the 5 th end of the first relay K1 is grounded through the fourth resistor R4 and the second LED in sequence. The first end of the first relay K1 is connected with any pin from the 11 th end to the 18 th end of the ULN2803A chip, if the output of the ULN2803A chip is at high level, the first relay K1 makes the 3 rd end of the first relay K1 and the 5 th end of the first relay K1 connected, and the 3 rd end of the first relay K1 is connected to the live wire, so that the second LED is lighted; if the output of the ULN2803A chip is low, the first relay K1 makes the 3 rd terminal of the first relay K1 and the 4 th terminal of the first relay K1 connected, so that the first LED D1 lights; the light color emitted by the first LED D1 is different from the light color emitted by the second LED, and in practical application, when the output of the ULN2803A chip is high level, the second LED D2 lights up to emit yellow light for worshipping Buddha; when the output of the ULN2803A chip is at low level, the first LED D1 lights up to emit white light, so as to achieve the effect of turning off the lamp.

In the specific implementation process, the network interface 1 receives a signal of a cloud and converts the signal into a 485 signal through an RS485 chip, the 485 signal generates a serial port signal through an MX1348 chip, the serial port signal generates a control signal after being processed through an STM32F103CBT6 chip, the control signal saves the level state of the serial port signal through a 74HC573D chip and controls the first relay K1 to correspondingly switch on the first LED D1 or the second LED D2 under the action of an ULN2803A chip, and then the Buddha figure can be served or extinguished.

The utility model discloses an intelligence beacon can not need to go to the temple also can be used for the buddha image.

It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. An intelligent lighthouse, comprising:

a network interface for coupling to a network;

the input conversion module is used for converting the network signal into a serial port signal;

the signal processing module is used for generating a control signal according to the serial port signal;

at least one relay module for controlling light switching;

the driving module is used for controlling each relay module according to the control signal;

the network interface is connected with the input conversion module; the input conversion module is connected with the signal processing module; the signal processing module is connected with the driving module; the driving module is respectively connected with at least one relay module.

2. The intelligent lighthouse of claim 1, wherein the input conversion module comprises: the circuit comprises a first chip, a second chip, a first resistor and a second resistor; the 1 st end of the second chip is grounded through a first resistor, and the 1 st end of the second chip is connected with the signal processing module; the 4 th end of the second chip is grounded through the second resistor, and the 4 th end of the second chip is connected with the signal processing module; the 5 th end of the second chip is grounded; the 6 th end of the second chip is connected with the 2 nd end of the first chip; the 7 th end of the second chip is connected with the 3 rd end of the first chip; the 8 th end of the second chip is connected with the signal processing module; and the 1 st end of the first chip is connected with the network interface.

3. The intelligent lighthouse of claim 2, wherein the first chip is an RS485 chip.

4. The intelligent lighthouse of claim 2, wherein the second chip is MX1348 chip.

5. The intelligent lighthouse of claim 1, wherein the signal processing module comprises: the first chip comprises a first chip, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first crystal oscillator and a second crystal oscillator; the 1 st end of the third chip, the 24 th end of the third chip, the 36 th end of the third chip and the 48 th end of the third chip are respectively connected with the input conversion module; the 3 rd end of the third chip is grounded through a first capacitor; the 3 rd end of the third chip is grounded through the first crystal oscillator and the second capacitor in sequence; the 4 th end of the third chip is grounded through a second capacitor; the 5 th end of the third chip is grounded through a third capacitor; the 5 th end of the third chip is grounded through the second crystal oscillator and the fourth capacitor in sequence; the 6 th end of the third chip is grounded through a fourth capacitor; the 23 rd end of the third chip, the 35 th end of the third chip and the 47 th end of the third chip are all grounded; the 30 th end of the third chip and the 31 st end of the third chip are respectively connected with the input conversion module; the 10 th end of the third chip, the 11 th end of the third chip, the 12 th end of the third chip, the 13 th end of the third chip, the 14 th end of the third chip, the 15 th end of the third chip, the 16 th end of the third chip and the 17 th end of the third chip are all connected with the driving module; and the 18 th end of the third chip, the 19 th end of the third chip, the 20 th end of the third chip, the 39 th end of the third chip, the 40 th end of the third chip, the 41 th end of the third chip, the 42 th end of the third chip and the 43 th end of the third chip are respectively used for being connected with the driving modules in a one-to-one correspondence manner.

6. An intelligent lighthouse as recited in claim 5, wherein the third chip is an STM32F103CBT6 chip.

7. The intelligent lighthouse of claim 1, wherein the driver module comprises: a fourth chip and a fifth chip; the 1 st end of the fourth chip and the 10 th end of the fourth chip are respectively grounded; the 2 nd end of the fourth chip, the 3 rd end of the fourth chip, the 4 th end of the fourth chip, the 5 th end of the fourth chip, the 6 th end of the fourth chip, the 7 th end of the fourth chip, the 8 th end of the fourth chip, the 9 th end of the fourth chip and the 11 th end of the fourth chip are respectively connected with the signal processing module; the 12 th end of the fourth chip is connected with the 1 st end of the fifth chip; the 13 th end of the fourth chip is connected with the 2 nd end of the fifth chip; the 14 th end of the fourth chip is connected with the 3 rd end of the fifth chip; the 15 th end of the fourth chip is connected with the 4 th end of the fifth chip; the 16 th end of the fourth chip is connected with the 5 th end of the fifth chip; the 17 th end of the fourth chip is connected with the 6 th end of the fifth chip; the 18 th end of the fourth chip is connected with the 7 th end of the fifth chip; the 19 th end of the fourth chip is connected with the 8 th end of the fifth chip; the 10 th end of the fifth chip is connected with the input conversion module; and the 11 th end of the fifth chip, the 12 th end of the fifth chip, the 13 th end of the fifth chip, the 14 th end of the fifth chip, the 15 th end of the fifth chip, the 16 th end of the fifth chip, the 17 th end of the fifth chip and the 18 th end of the fifth chip are respectively used for being connected with the relay modules in a one-to-one correspondence manner.

8. The intelligent lighthouse of claim 7, wherein the fourth chip is a 74HC573D chip.

9. The intelligent lighthouse of claim 7, wherein the fifth chip is a ULN2803A chip.

10. The intelligent lighthouse of claim 1, wherein the relay module comprises: the LED driving circuit comprises a first relay, a third resistor, a fourth resistor, a first LED and a second LED; the 1 st end of the first relay is connected with the driving module; the 2 nd end of the first relay is grounded; the 3 rd end of the first relay is connected with the input conversion module; the 4 th end of the first relay is grounded through the third resistor and the first LED in sequence; and the 5 th end of the first relay is grounded through the fourth resistor and the second LED in sequence.