CN213423231U - Protection type semiconductor chip high temperature resistant packaging testing arrangement - Google Patents
Protection type semiconductor chip high temperature resistant packaging testing arrangement Download PDFInfo
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- CN213423231U CN213423231U CN202022725959.5U CN202022725959U CN213423231U CN 213423231 U CN213423231 U CN 213423231U CN 202022725959 U CN202022725959 U CN 202022725959U CN 213423231 U CN213423231 U CN 213423231U
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- heat preservation
- high temperature
- temperature resistant
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Abstract
The utility model relates to the technical field of testing devices, and discloses a protective high-temperature-resistant packaging testing device for semiconductor chips, which comprises a box body, wherein a horizontal rod is arranged above the interior of the box body, a placing frame is arranged inside the horizontal rod, a closed heat conduction copper pipe is arranged at a position which is five centimeters below the placing frame, a baffle is arranged inside the box body, a cooling box is arranged at one end of the top surface of the baffle, a heat preservation layer is arranged inside the cooling box, a plain concrete layer is arranged inside the heat preservation layer, a heat preservation shell is arranged inside the plain concrete layer in a clinging manner, and condensed gas is arranged inside the heat preservation shell. Preventing gas leakage and causing material waste.
Description
Technical Field
The utility model belongs to the technical field of testing arrangement, concretely relates to protection type semiconductor chip high temperature resistant encapsulation testing arrangement.
Background
Semiconductor chip packaging testing is an essential process step for chips to become qualified products, and with the rapid progress of the semiconductor chip industry, the requirements for testing the performance of new products and packaging are very many, and the speed requirement is very high.
The existing high-temperature-resistant packaging testing device for the semiconductor chip does not have a protection measure, the semiconductor is easy to soften in the high-temperature testing process, certain potential safety hazards exist, the heat preservation effect of the cooling box is poor, the heated semiconductor cannot be rapidly cooled, the working efficiency is reduced, and the use is inconvenient.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a protection type semiconductor chip high temperature resistant encapsulation testing arrangement to solve the semiconductor and the heating plate contact heating that provide in the above-mentioned background art, make the semiconductor soften easily, reach the inflammable point, there is the problem of potential safety hazard.
In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a protection type semiconductor chip high temperature resistant encapsulation testing arrangement, includes the box, the horizon bar is installed to the inside top of box, the internally mounted of horizon bar has the rack, closed heat conduction copper pipe is installed to the position of five centimetres in below of rack, the internally mounted of box has the baffle, the cooler bin is installed to the top surface one end of baffle, the internally mounted of cooler bin has the heat preservation, the internally mounted of heat preservation has plain concrete layer, the inside on plain concrete layer is hugged closely and is installed the heat preservation shell, the internally mounted of heat preservation shell has the condensation gas.
Preferably, the bottom of the heat preservation shell is provided with an air suction port, one side of the air suction port is provided with a first conduit, and one end of the first conduit is provided with an air pump.
Preferably, a second conduit is installed at one end of the air pump, an air outlet is connected to one end of the second conduit, and the top of the air outlet is connected with the partition plate.
Preferably, the inlet pipe is installed at the top of cooler bin, the externally mounted of inlet pipe has the protective layer, the outside cover of protective layer is equipped with the lid.
Preferably, three observation windows are installed on the front surface of the box body, and a door body is installed below the observation windows.
Preferably, one end of the front surface of the cooling box is provided with a liquid level scale mark, and the surface of the box body is coated with deep-color waterproof paint.
Compared with the prior art, the beneficial effects of the utility model are that:
(1) the utility model discloses a be provided with the cooler bin, protect and store nitrogen gas through being equipped with plain concrete layer and protective layer in the inside of cooler bin, improve the holistic security performance of device to feed inlet department still is equipped with the lid airtight, prevents gas leakage, causes the material extravagant.
(2) The utility model discloses a heat conduction copper pipe is installed to the below at the rack, and the heat that produces through heat conduction copper pipe carries out high temperature treatment to the semiconductor on the rack to heat conduction copper pipe and rack interval 5 centimetres, the semiconductor not only can receive high temperature treatment, has also avoided the semiconductor to soften the burning because of the temperature is higher, has improved the security performance.
Drawings
Fig. 1 is a schematic structural view of the present invention;
FIG. 2 is an external view of the present invention;
fig. 3 is a side view of the present invention;
in the figure: 1-a box body; 2-heat conducting copper pipe; 3-a separator; 4-air outlet; 5-insulating layer; 6, an air pump; 7-a first conduit; 71-a second conduit; 8-air suction port; 9-condensing gas; 10-a heat preservation shell; 11-feed pipe; 12-a protective layer; 13-a cover body; 14-plain concrete layer; 15-placing the rack; 16-horizontal bar; 17-a viewing window; 18-a door body; 19-a cooling tank; 20-liquid level scale mark.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-3, the present invention provides the following technical solutions: a high-temperature resistant packaging test device for a protective semiconductor chip comprises a box body 1, a horizontal rod 16 is installed above the interior of the box body 1, a placing frame 15 is installed inside the horizontal rod 16, a closed heat conduction copper pipe 2 is installed at a position five centimeters below the placing frame 15, the semiconductor chip is heated by heat emitted by the heat conduction copper pipe 2, the high-temperature resistant performance of the semiconductor chip is detected, a partition plate 3 is installed inside the box body 1, the box body 1 is divided into two working areas through the partition plate 3, the two working areas are separated and do not affect each other, a cooling box 19 is installed at one end of the top surface of the partition plate 3, a heat preservation layer 5 is installed inside the cooling box 19, a plain concrete layer 14 is installed inside the heat preservation layer 5, the heat preservation is performed on nitrogen in the cooling box 19 by arranging the plain concrete layer 14, the cold air of the nitrogen is, the inside of plain concrete layer 14 is hugged closely and is installed heat preservation shell 10, and the inside of heat preservation shell 10 is installed the condensate gas 9, and condensate gas 9 is nitrogen gas.
Furthermore, the bottom of the heat preservation shell 10 is provided with an air suction port 8, one side of the air suction port 8 is provided with a first conduit 7, one end of the first conduit 7 is provided with an air pump 6, nitrogen in the cooling box 19 is conveyed into the space where the placing frame 15 is located from the first conduit 7 through the air outlet 4 through the air pump 6, and the semiconductor chip is physically cooled.
Further, one end of the air pump 6 is provided with a second conduit 71, one end of the second conduit 71 is connected with the air outlet 4, and the top of the air outlet 4 is connected with the partition plate 3.
Further, inlet pipe 11 is installed at the top of cooler bin 19, and the externally mounted of inlet pipe 11 has protective layer 12, and the outside cover of protective layer 12 is equipped with lid 13, fixes at the tip of inlet pipe 11 through lid 13 rotation, prevents that the nitrogen gas in the cooler bin 19 from leaking, causes the material extravagant.
Furthermore, three observation windows 17 are installed on the front surface of the box body 1, a door body 18 is installed below the observation windows 17, the air pump 6 is replaced and maintained by opening the door body 18, the operation is convenient, and the work efficiency is improved.
Furthermore, liquid level scale marks 20 are installed at one end of the front surface of the cooling box 19, the surface of the box body 1 is coated with deep-color waterproof paint, the storage amount of nitrogen in the cooling box 19 can be observed through the liquid level scale marks 20, and the nitrogen can be added in time after the nitrogen is used up.
The utility model discloses a theory of operation and use flow: when using the utility model discloses the time, through injecting nitrogen gas into inlet pipe 11 in cooling box 19, place semiconductor chip on rack 15 in proper order, then heat conduction copper pipe 2 generates heat, carry out high temperature resistance test to semiconductor chip, 5 centimetres apart between heat conduction copper pipe 2 and the horizon bar 16, prevent that heat conduction copper pipe 2 from hugging closely with semiconductor chip, lead to semiconductor chip to soften, there is the potential safety hazard, observe the test process through observation tube 17, the examination result comes out after, start air pump 6, condensation gas 9 is from first pipe 7, advance second pipe 71 and be discharged by gas outlet 4, reduce the inside temperature of heating structure, treat to take out after the semiconductor chip cools off.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The utility model provides a high temperature resistant encapsulation testing arrangement of protection type semiconductor chip, includes box (1), its characterized in that: horizontal pole (16) are installed to the inside top of box (1), the internally mounted of horizontal pole (16) has rack (15), closed heat conduction copper pipe (2) are installed to the position of five centimetres in below of rack (15), the internally mounted of box (1) has baffle (3), cooler bin (19) is installed to the top surface one end of baffle (3), the internally mounted of cooler bin (19) has heat preservation (5), the internally mounted of heat preservation (5) has plain concrete layer (14), the inside of plain concrete layer (14) is hugged closely and is installed heat preservation shell (10), the internally mounted of heat preservation shell (10) has condensation gas (9).
2. The device for testing the high temperature resistant package of the protected semiconductor chip according to claim 1, wherein: an air suction port (8) is formed in the bottom of the heat preservation shell (10), a first guide pipe (7) is installed on one side of the air suction port (8), and an air pump (6) is installed at one end of the first guide pipe (7).
3. The device for testing the high temperature resistant package of the protected semiconductor chip according to claim 2, wherein: a second conduit (71) is installed at one end of the air pump (6), one end of the second conduit (71) is connected with the air outlet (4), and the top of the air outlet (4) is connected with the partition board (3).
4. The device for testing the high temperature resistant package of the protected semiconductor chip according to claim 1, wherein: inlet pipe (11) are installed at the top of cooler bin (19), the externally mounted of inlet pipe (11) has protective layer (12), the outside cover of protective layer (12) is equipped with lid (13).
5. The device for testing the high temperature resistant package of the protected semiconductor chip according to claim 1, wherein: the front surface of the box body (1) is provided with three observation windows (17), and a door body (18) is arranged below the observation windows (17).
6. The device for testing the high temperature resistant package of the protected semiconductor chip according to claim 1, wherein: liquid level scale marks (20) are installed at one end of the front surface of the cooling box (19), and dark waterproof paint is coated on the surface of the box body (1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202022725959.5U CN213423231U (en) | 2020-11-23 | 2020-11-23 | Protection type semiconductor chip high temperature resistant packaging testing arrangement |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202022725959.5U CN213423231U (en) | 2020-11-23 | 2020-11-23 | Protection type semiconductor chip high temperature resistant packaging testing arrangement |
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Publication Number | Publication Date |
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CN213423231U true CN213423231U (en) | 2021-06-11 |
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CN202022725959.5U Active CN213423231U (en) | 2020-11-23 | 2020-11-23 | Protection type semiconductor chip high temperature resistant packaging testing arrangement |
Country Status (1)
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CN (1) | CN213423231U (en) |
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2020
- 2020-11-23 CN CN202022725959.5U patent/CN213423231U/en active Active
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