CN212648245U - Cascade device - Google Patents
Cascade device Download PDFInfo
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- CN212648245U CN212648245U CN202021934893.4U CN202021934893U CN212648245U CN 212648245 U CN212648245 U CN 212648245U CN 202021934893 U CN202021934893 U CN 202021934893U CN 212648245 U CN212648245 U CN 212648245U
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Abstract
The utility model discloses a cascade device, cascade device includes the substrate, is located epitaxial structure on the substrate, is located a plurality of passivation layers and a plurality of electrode on the epitaxial structure, epitaxial structure is including being located the channel layer on the substrate and being located the barrier layer on the channel layer, the last enhancement region and the exhaust region that are equipped with of epitaxial structure, the electrode is including being located source electrode, drain electrode, intermediate electrode, first grid, the second grid on the epitaxial structure, second grid and source electrode electric connection, source electrode, drain electrode, first grid are as the source electrode, drain electrode and the grid of cascading device respectively. The utility model effectively separates the interaction between the low-voltage enhancement type part and the high-voltage depletion type part in the cascade device by introducing the middle electrode in the cascade device; the problem of increased grid leakage current caused by dry etching of the low-voltage part of the grid is solved, the overall withstand voltage of the device is improved, and the device can be suitable for high-voltage application scenes.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor, concretely relates to cascade device.
Background
Aluminum gallium nitride/gallium nitride high electron mobility transistors have been receiving attention in different application scenarios due to their excellent power switching characteristics. In 2018, Anker released the first product based on gallium nitride power devices, which opened the introduction of gallium nitride power devices in consumer electronics. Compared with the traditional silicon-based scheme, the fast charging scheme based on the gallium nitride power device has the advantages of smaller volume, higher power, higher efficiency and lower heat productivity. These characteristics all benefit from the lower on-resistance and parasitic capacitance of gallium nitride devices. However, the current commercial gan power devices are over-designed due to the reliability of the devices, and the advantages of the materials are not fully exploited.
Conventional gallium nitride power devices rely on p-type gate technology to achieve an enhanced mode of operation. In the process of implementing a p-type gate, a two-step process is generally adopted: firstly, defining a p-type gallium nitride or aluminum gallium nitride part of a grid electrode region by utilizing dry etching or selective growth; and then the gate metal region is redefined through a second mask lithography step. This approach presents a number of problems to the device and process: firstly, the mask photoetching procedure in two steps requires excessive design of p-type gallium nitride or aluminum gallium nitride in a grid region, namely the line width of the p-type gallium nitride or the aluminum gallium nitride is required to be larger than the line width of grid metal, so that the on-resistance of a device and the capacitance of a grid are increased; secondly, in the process of etching and opening the gate metal in the second step, the p-type gallium nitride surface of the gate region is damaged, which may cause the increase of the gate leakage current of the device or cause the reliability problem of the device; finally, from a process perspective, the two-step mask lithography process can present challenges to the accuracy of the lithography, while increasing the cost of the process.
In view of the above problems, the EPC company in the united states proposes a gan-enhanced device based on a self-aligned gate technology, which is different from the conventional two-step method, in that the technology firstly plates a gate metal on the whole device epitaxy, and then defines the gate metal and the p-type gan or algan on the lower layer thereof by etching in one step, thereby realizing the self-alignment of the p-type gan or algan and the gate metal. The process technology can effectively reduce the gate width of the device and maximize the advantages of a gallium nitride enhanced device based on a p-type gate technology; meanwhile, the process cost is saved due to the reduction of the process steps. However, since a dry etching process is still required in the process of defining the gate metal and the p-type gan or algan, the gate of the device, especially the side close to the drain, is still inevitably damaged by etching. Compared with the traditional device based on the p-type gate technology of the two-step method, the device based on the self-alignment technology has the advantages that the gate metal of the device directly contacts the edge of p-type gallium nitride or aluminum gallium nitride etching damage, and therefore the gate leakage current is larger than that of the traditional device. As such, in practical applications, gan enhancement devices based on self-aligned gate technology are not suitable for high voltage (650V) applications.
Therefore, in view of the above technical problems, it is necessary to provide a cascode device.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a cascade device to promote the whole withstand voltage of gallium nitride enhancement mode device based on self-aligning grid technique, realize the use of device under the scene is used to the high pressure.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a cascade device comprises a substrate, an epitaxial structure located on the substrate, a plurality of passivation layers located on the epitaxial structure and a plurality of electrodes, wherein the epitaxial structure comprises a channel layer located on the substrate and a barrier layer located on the channel layer, an enhancement region and a depletion region are arranged on the epitaxial structure, the electrodes comprise a source electrode, a drain electrode, a middle electrode, a first grid electrode and a second grid electrode, the middle electrode is located between the source electrode and the drain electrode and between the enhancement region and the depletion region, the first grid electrode is located on the enhancement region and between the source electrode and the middle electrode, the second grid electrode is electrically connected with the source electrode, and the source electrode, the drain electrode and the first grid electrode are respectively used as the source electrode, the drain electrode and the grid electrode of the cascade device.
In one embodiment, the passivation layer includes:
a first passivation layer over the epitaxial structure and the source, drain and intermediate electrodes;
the second passivation layer is positioned above the first passivation layer, and the thickness of the second passivation layer is smaller than that of the first passivation layer;
and a plurality of third passivation layers positioned above the second passivation layers and the first and second gates.
In one embodiment, the first passivation layer is one or a combination of silicon nitride layer and silicon oxide layer, and the thickness is 50nm to 250 nm; the second passivation layer is one or a combination of more of a silicon nitride layer, an aluminum oxide layer and a silicon oxide layer, and the thickness of the second passivation layer is 10 nm-100 nm; the third passivation layer is one or the combination of more of a silicon nitride layer or a silicon oxide layer, and the thickness of each layer is 50 nm-1000 nm.
In one embodiment, the enhancement region includes a first groove penetrating all of the first passivation layer and a p-type doped layer located in the first groove, and the first gate is located on the p-type doped layer; the depletion region comprises a second groove penetrating through all the first passivation layers, and a second passivation layer is filled between the second grid electrode and the second groove.
In one embodiment, the first gate and the p-type doped layer are formed based on a self-aligned gate technology, the first gate is located right above the p-type doped layer, and the cross-sectional shape of the first gate is identical to that of the p-type doped layer.
In one embodiment, the p-type doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer.
In one embodiment, the cascade device further comprises one or more metal connection layers electrically connected to the first gate and the source of the cascade device.
In one embodiment, the substrate is one or a combination of silicon, sapphire and silicon carbide; the channel layer and barrier layer are group III nitrides.
In one embodiment, the channel layer is a gallium nitride layer and the barrier layer is an aluminum gallium nitride layer.
In one embodiment, the epitaxial structure further comprises a buffer layer between the channel layer and the substrate, wherein the buffer layer is one or more of an aluminum nitride layer, a gallium nitride layer and an aluminum gallium nitride layer.
Compared with the prior art, the utility model has the advantages of it is following:
the utility model effectively separates the interaction between the low-voltage enhancement type part and the high-voltage depletion type part in the cascade device by introducing the middle electrode in the cascade device;
by combining the characteristics of the cascade device and shielding and protecting the enhancement type part through the depletion type part, the enhancement type part is not influenced by high voltage, so that the problem that grid leakage current is increased due to dry etching of a grid of a low-voltage part is solved, the overall withstand voltage of the device is improved, and the device can be suitable for high-voltage application scenes.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a cascade device according to an embodiment of the present invention;
fig. 2 is an equivalent circuit diagram of a cascade device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiments, and the structural, method, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.
Referring to fig. 1, a cascade device according to an embodiment of the present invention mainly includes a low-voltage enhancement device 110 and a high-voltage depletion device 120 that are monolithically integrated.
Specifically, the cascade device includes a substrate 210, an epitaxial structure on the substrate, a plurality of passivation layers on the epitaxial structure, and a plurality of electrodes.
The epitaxial structure includes a channel layer 230 on a substrate 210 and a barrier layer 240 on the channel layer 230, and preferably, the epitaxial structure in this embodiment further includes a buffer layer 220 between the channel layer 230 and the substrate 210.
Specifically, the substrate 210 is a combination of one or more of silicon, sapphire, silicon carbide, and the like; the buffer layer 220 is one or a combination of more of an aluminum nitride layer, a gallium nitride layer, an aluminum gallium nitride layer and the like; the channel layer 230 and barrier layer 230 are group iii nitrides, preferably the channel layer is a gallium nitride layer and the barrier layer is an aluminum gallium nitride layer.
The passivation layer in this embodiment includes:
a first passivation layer 251 located above the epitaxial structure and the source, drain and intermediate electrodes, preferably, the first passivation layer is one or a combination of more of a silicon nitride layer or a silicon oxide layer, and the like, and has a thickness of 50nm to 250 nm;
a second passivation layer 252, which is located above the first passivation layer and has a thickness smaller than that of the first passivation layer, and preferably, the second passivation layer is one or a combination of more of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, and the like, and has a thickness of 10nm to 100 nm;
and a plurality of third passivation layers 253 located above the second passivation layer and the first and second gates, preferably, the third passivation layer is one or a combination of silicon nitride layer or silicon oxide layer, each layer has a thickness of 50nm to 1000nm, which is exemplified by one third passivation layer in the embodiment.
The epitaxial structure in this embodiment is provided with an enhanced region and a depletion region, the electrodes include a source electrode 261, a drain electrode 262 and an intermediate electrode 264 on the epitaxial structure, a first gate electrode 263 located on the enhanced region and between the source electrode and the intermediate electrode, and a second gate electrode 265 located on the depletion region and between the intermediate electrode and the drain electrode, and the second gate electrode 265 is electrically connected to the source electrode 261.
The source, the drain and the gate of the low-voltage enhancement device 110 in this embodiment are respectively a source 261, an intermediate electrode 264 and a first gate 263, and the source, the drain and the gate of the high-voltage depletion device 120 are respectively an intermediate electrode 264, a drain 262 and a second gate 265. The source S, the drain D and the gate G of the entire cascode device are the source 261, the drain 262 and the first gate 263, respectively.
In this embodiment, the middle electrode 264 serves as both the drain of the low-voltage enhancement device 110 and the source of the high-voltage depletion device 120.
The drain electrode and the source electrode of the low-voltage enhancement type device can be in an Au-free metallization structure such as Ti/Al/TiN, or in an Au-based metallization structure such as Ti/Al/Ni/Au; the grid electrode can be a metal structure without Au, such as TiN/Al/TiN, or an Au-based metal structure, such as Ti (Ni)/Au.
The enhancement region in the low-voltage enhancement device includes a first groove (not numbered) penetrating all the first passivation layer 251 and a p-type doped layer 270 located in the first groove, the p-type doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer, the first gate 263 is arranged in contact with the p-type doped layer 270, and the first gate realizes an enhancement mode of operation by a structure based on p-type gallium nitride or p-type aluminum gallium nitride.
The low voltage portion in this embodiment is a gan enhancement device based on a self-aligned gate technology, the first gate and the p-type doped layer are formed based on the self-aligned gate technology, the first gate is located right above the p-type doped layer, and the cross-sectional shape of the first gate is identical to the cross-sectional shape of the p-type doped layer.
The drain electrode and the source electrode of the high-voltage depletion mode device can be in an Au-free metallization structure such as Ti/Al/TiN, or in an Au-based metallization structure such as Ti/Al/Ni/Au; the grid metal can be a metal structure without Au, such as TiN/Al/TiN, or a metal structure based on Au, such as Ti (Ni)/Au.
The depletion region in the high-voltage depletion mode device comprises a second groove (not numbered) penetrating through all the first passivation layer 251, a second passivation layer 252 is filled between a second gate and the second groove, the gate can realize a depletion mode operation by a metal-insulating layer-semiconductor based structure, a dielectric layer is a second passivation layer, the material is silicon nitride, aluminum oxide or silicon oxide, and the like, and the thickness is 10nm to 100 nm.
In this embodiment, the second gate 265 of the high voltage depletion mode device is electrically connected to the source 261 of the low voltage enhancement mode device through one or more metal connection layers 2651. Wherein the metal connecting layer can be a metal structure without Au, such as Ti/Al/TiN, or a metal structure based on Au, such as Ti (Ni)/Au. In addition, the high-voltage depletion mode device can also comprise one or more layers of source field plates, and one or more layers of metal connecting layers are used as field plate metals.
Fig. 2 is an equivalent circuit diagram of the cascode device in the present embodiment, which includes:
the low-voltage enhancement type device 110 and the high-voltage depletion type device 120, the low-voltage enhancement type device 110 includes a first gate 1101, a first source 1102 and a first drain 1103, the high-voltage depletion type device 120 includes a second gate 1201, a second source 1202 and a second drain 1203, the first drain 1103 of the low-voltage enhancement type device 110 is electrically connected to the second source 1202 of the high-voltage depletion type device 120 to serve as an intermediate electrode a (264 in fig. 1) of the cascade circuit, the first source 1102 of the low-voltage enhancement type device 110 is electrically connected to the second gate 1201 of the high-voltage depletion type device 120 to serve as a source S of the cascade circuit, the first gate 1101 of the low-voltage enhancement type device 120 serves as a gate G of the cascade circuit, and the second drain 1203 of the high-voltage depletion type device 120 serves as a drain D of the.
In the prior art, the gallium nitride enhanced device based on the self-aligned gate technology is difficult to use in high-voltage (650V level) application due to unavoidable etching damage and other process reasons. The utility model discloses combine classic cascade structure, realize the protection to the enhancement device based on self-aligning grid technique through the monolithic integration high pressure depletion type device, reduce the withstand voltage requirement of the latter.
Moreover, compare the dual gate structure of traditional monolithic integration, the utility model discloses introduced extra intermediate electrode between two grids of low pressure enhancement device and high pressure depletion device, regard as the drain electrode of low pressure enhancement device and the source electrode of high pressure depletion device jointly. The introduction of the intermediate electrode can effectively isolate the interaction between the low-voltage enhancement device and the high-voltage depletion device, optimize the electric field distribution between two grids in the traditional double-grid structure, and further improve the stability of the cascade device.
Through above structure, the utility model provides a cascade device only need possess and be less than 30V withstand voltage, whole device alright in order to normally work in high pressure (650V) is used, has reduced technology problems such as sculpture damage by a wide margin to the influence based on self-alignment grid technical device. The structure can also fully exert the advantages of the self-aligned gate technology, and compared with the traditional gallium nitride enhanced device and a double-gate structure, the structure realizes smaller parasitic capacitance and higher switching speed.
According to the technical scheme provided by the utility model, the utility model discloses following beneficial effect has:
the utility model effectively separates the interaction between the low-voltage enhancement type part and the high-voltage depletion type part in the cascade device by introducing the middle electrode in the cascade device;
by combining the characteristics of the cascade device and shielding and protecting the enhancement type part through the depletion type part, the enhancement type part is not influenced by high voltage, so that the problem that grid leakage current is increased due to dry etching of a grid of a low-voltage part is solved, the overall withstand voltage of the device is improved, and the device can be suitable for high-voltage application scenes.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A cascade device is characterized by comprising a substrate, an epitaxial structure positioned on the substrate, a plurality of passivation layers positioned on the epitaxial structure and a plurality of electrodes, wherein the epitaxial structure comprises a channel layer positioned on the substrate and a barrier layer positioned on the channel layer, the epitaxial structure is provided with an enhancement region and a depletion region, the electrodes comprise a source electrode, a drain electrode, a middle electrode, a first grid electrode and a second grid electrode, the middle electrode is positioned on the epitaxial structure, the middle electrode is positioned between the source electrode and the drain electrode and between the enhancement region and the depletion region, the first grid electrode is positioned on the enhancement region and between the source electrode and the middle electrode, the second grid electrode is electrically connected with the source electrode, and the source electrode, the drain electrode and the first grid electrode are respectively used as the source electrode, the drain electrode and the grid electrode of the cascade device.
2. The tandem device of claim 1, wherein the passivation layer comprises:
a first passivation layer over the epitaxial structure and the source, drain and intermediate electrodes;
the second passivation layer is positioned above the first passivation layer, and the thickness of the second passivation layer is smaller than that of the first passivation layer;
and a plurality of third passivation layers positioned above the second passivation layers and the first and second gates.
3. The tandem device of claim 2 wherein the first passivation layer is one or a combination of silicon nitride layer or silicon oxide layer with a thickness of 50nm to 250 nm; the second passivation layer is one or a combination of more of a silicon nitride layer, an aluminum oxide layer and a silicon oxide layer, and the thickness of the second passivation layer is 10 nm-100 nm; the third passivation layer is one or the combination of more of a silicon nitride layer or a silicon oxide layer, and the thickness of each layer is 50 nm-1000 nm.
4. The cascade device of claim 2, wherein the enhancement region comprises a first recess through all of the first passivation layer and a p-doped layer located within the first recess, the first gate being located on the p-doped layer; the depletion region comprises a second groove penetrating through all the first passivation layers, and a second passivation layer is filled between the second grid electrode and the second groove.
5. The cascade device of claim 4, wherein the first gate and the p-doped layer are formed based on a self-aligned gate technique, wherein the first gate is directly above the p-doped layer and wherein the cross-sectional shape of the first gate is substantially the same as the cross-sectional shape of the p-doped layer.
6. The cascade device of claim 4, wherein the p-doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer.
7. The cascode device of claim 1, further comprising one or more metal connection layers electrically connecting the first gate and the source of the cascode device.
8. The tandem device of claim 1 wherein the channel layer and barrier layer are group iii nitrides.
9. The cascade device of claim 8, wherein the channel layer is a gallium nitride layer and the barrier layer is an aluminum gallium nitride layer.
10. The tandem device of claim 1 wherein the epitaxial structure further comprises a buffer layer between the channel layer and the substrate, the buffer layer being a combination of one or more of an aluminum nitride layer, a gallium nitride layer, and an aluminum gallium nitride layer.
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| CN202021934893.4U CN212648245U (en) | 2020-09-07 | 2020-09-07 | Cascade device |
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| CN202021934893.4U CN212648245U (en) | 2020-09-07 | 2020-09-07 | Cascade device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111916449A (en) * | 2020-09-07 | 2020-11-10 | 苏州英嘉通半导体有限公司 | Cascade device |
| WO2024082980A1 (en) * | 2022-10-20 | 2024-04-25 | 华为技术有限公司 | Chip, control chip, switching power supply and power adapter |
-
2020
- 2020-09-07 CN CN202021934893.4U patent/CN212648245U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111916449A (en) * | 2020-09-07 | 2020-11-10 | 苏州英嘉通半导体有限公司 | Cascade device |
| WO2024082980A1 (en) * | 2022-10-20 | 2024-04-25 | 华为技术有限公司 | Chip, control chip, switching power supply and power adapter |
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