CN212302465U

CN212302465U - Compact debugging interface, connector thereof and electronic system

Info

Publication number: CN212302465U
Application number: CN202021140857.0U
Authority: CN
Inventors: 倪勇
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2020-06-18
Filing date: 2020-06-18
Publication date: 2021-01-05
Anticipated expiration: 2030-06-18

Abstract

A compact debugging interface, a connector thereof and an electronic system are provided. The connector of the compact debugging interface comprises a first group of pins and a selection pin; each pin of the first group of pins is used for transmitting a plurality of signals of the first debugging port and the second debugging port; the selection signal transmitted by the selection pin indicates that a plurality of signals of a first debugging end or a second debugging port are electrically connected to a first group of pins, wherein the number of the pins of the first group of pins is less than the sum of the number of the signals of the first debugging port and the second debugging port.

Description

Compact debugging interface, connector thereof and electronic system

Technical Field

The present application relates to a memory device, and more particularly, to a compact debug interface, a connector thereof, and an electronic system.

Background

FIG. 1 illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.

The interface 103 is used to couple the storage device to a host and is adapted to exchange data with the host by means of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The storage device further comprises power management means for providing power to the various components of the storage device. The power supply circuit of the storage device is shown in chinese patent applications 201210258780.0 and 201510347811.3 as an example of a power management apparatus. The host provides power to the storage device 102 through the interface 103 to operate the storage device 102. The storage device 102 also includes a backup power supply that provides emergency power to the storage device 102 in the event of a host power interruption or failure to the storage device 102. So that the storage device 102 can continue to execute the IO command that is not completed, and also record the operating status of the storage device by using the power provided by the backup power source, so that the storage device can continue to operate normally after the power supply is restored through the interface 103.

The backup power source is rechargeable, such as a rechargeable battery or capacitor. The standby power supply comprises a charging interface. The charging interface is coupled to the interface 103. When the interface 103 supplies power to the storage device, the standby power supply is charged through the charging interface.

The control unit further comprises a debug interface. For exchanging debugging information between the control unit and the outside. The debug interface conforms to, for example, a Serial interface (UART), I2C, JTAG, MCTP (Management Component Transport Protocol), Management Component Transport Protocol, among othershttps://www.dmtf.org/sites/default/files/standards/ documents/DSP0236_1.3.1.pdfAvailable), etc.

SUMMERY OF THE UTILITY MODEL

The debug interface is mainly used in the development stage of the storage device, and for the mass production stage of the storage device, only the physical connector for coupling the interface of the host is usually reserved outside the storage device for reducing the cost. Some storage devices reserve pins for the debug interface in the physical connector that couples the host.

As the control components of memory devices become increasingly complex, including, for example, multiple processor cores and even multiple processor cores of different architectures, each processor core uses a respective debug interface. This results in the control unit exhibiting a plurality of different kinds of debug interfaces. Some memory devices also include a second or update control component, such as a processor core also in the power management apparatus and having a debug interface. Each of the plurality of debug interfaces needs to be coupled to an external debug device through a physical port of the memory device. The physical connectors coupling the hosts cannot accommodate the multiple debug interfaces required.

Additional physical ports need to be provided electronically to accommodate the leads for the various debug interfaces. In addition to being used for storage devices, the additional physical ports provided are also applicable to other electronic devices for debugging control components or processor cores thereof within the electronic device. The additional physical ports provided need to be compact, couple the various debug interfaces to the external debugger in as small a volume as possible, and do not significantly increase the cost of the memory device. Compact physical interfaces also require debug interfaces that adapt to multiple protocols. These debug interfaces each have, for example, different electrical characteristics.

According to a first aspect of the present application, there is provided a connector of a first compact debug interface according to the first aspect of the present application, comprising a first set of pins and a selection pin; each pin of the first group of pins is used for transmitting a plurality of signals of the first debugging port and the second debugging port; the selection signal transmitted by the selection pin indicates that a plurality of signals of a first debugging end or a second debugging port are electrically connected to a first group of pins, wherein the number of the pins of the first group of pins is less than the sum of the number of the signals of the first debugging port and the second debugging port.

According to a connector of a first compact commissioning interface of a first aspect of the present application, a second connector according to the first aspect of the present application is provided, wherein the connector is arranged at an electronic device for connecting the electronic device to a commissioning device; the first debug port and the second debug port are debug ports of the electronic device.

According to the second connector of the first aspect of the present application, there is provided the third connector of the first aspect of the present application, wherein the debug device provides the selection signal to the selection pin.

According to one of the first to third connectors of the first aspect of the present application, there is provided the fourth connector of the first aspect of the present application, further comprising a reference voltage pin; the signal of the reference voltage pin indicates an interface level used by the first debug port or the second debug port.

According to a fourth connector of the first aspect of the present application, there is provided the fifth connector of the first aspect of the present application, wherein the electronic device provides an interface level used by the first debug port or the second debug port to the reference voltage pin; the debugging obtains the interface level from the reference voltage pin and adjusts the signals provided to the first group of pins according to the interface level, so that the signals provided to the first group of pins are compatible with the interface level.

According to one of the first to fifth connectors according to the first aspect of the present application, there is provided the sixth connector according to the first aspect of the present application, further comprising a second group of pins; and each pin of the second group of pins is used for transmitting a plurality of signals of the third debugging port and the fourth debugging port.

According to a sixth connector of the first aspect of the present application, there is provided the seventh connector of the first aspect of the present application, wherein the selection signal transmitted by the selection pin indicates that a plurality of signals of the third debug terminal or the fourth debug port are electrically connected to the second pin group.

According to one of the first to seventh connectors of the first aspect of the present application, there is provided the eighth connector of the first aspect of the present application, further comprising a second reference voltage pin; the signal of the second reference voltage pin indicates an interface level used by the third debug port or a fourth debug port.

According to one of the first to eighth connectors according to the first aspect of the present application, there is provided the ninth connector according to the first aspect of the present application, further comprising a power supply pin; the power pin is used for transmitting power.

According to one of the first to ninth connectors of the first aspect of the present application, there is provided the tenth connector of the first aspect of the present application, wherein a mechanical form of the connector conforms to an HDMI specification or a PCIe specification.

According to a second aspect of the present application, there is provided a first compact debug interface according to the second aspect of the present application, comprising a connector and a pin compression and decompression unit; the connector is one of first to tenth connectors according to the first aspect of the present application; the pin compression and decompression unit couples the first set of pins with the select pin.

According to the first compact debug interface of the second aspect of the present application, there is provided the second compact debug interface of the second aspect of the present application, wherein the pin compression and decompression unit is a multi-channel switch; the multi-channel switch electrically connects one of the first debug port or the second debug port to the first set of pins in response to a select signal of the select pin.

According to a second compact debug interface of the second aspect of the present application, there is provided a third compact debug interface of the second aspect of the present application, the multi-channel switch further coupled to the reference voltage pin; in response to a selection signal of the selection pin, the multi-channel switch provides an interface level used by one of the first debug port or the second debug port indicated by the selection signal to the reference voltage pin.

According to a third compact debug interface of the second aspect of the present application, there is provided a fourth compact debug interface of the second aspect of the present application, wherein in response to a selection signal of the selection pin, the multi-channel switch electrically connects one of the third debug port or the fourth debug port indicated by the selection signal to the second group of pins; the multi-channel switch provides an interface level used by one of the third debug port or the fourth debug port indicated by the selection signal to a second reference voltage pin.

According to the first compact debug interface of the second aspect of the present application, there is provided a fifth compact debug interface of the second aspect of the present application, wherein the pin compression and decompression unit is a multi-channel switch; the multi-channel switch electrically connects the first set of pins to one of a first set of leads or a second set of leads in response to a select signal of the select pin.

According to a fifth compact debug interface of the second aspect of the present application, there is provided a sixth compact debug interface of the second aspect of the present application, the multi-channel switch further coupled to the reference voltage pin; in response to a select signal of the select pin, the multi-channel switch provides an interface level used by one of the first set of leads or the second set of leads indicated by the select signal to the reference voltage pin.

According to a sixth compact debug interface of the second aspect of the present application, there is provided a seventh compact debug interface of the second aspect of the present application, wherein the first set of leads couples the first debug port and the second set of leads couples the second debug port.

According to one of the first to seventh compact debug interfaces of the second aspect of the present application, there is provided the eighth compact debug interface of the second aspect of the present application, further comprising a voltage adaptation unit; the voltage adapting unit is coupled with the reference voltage pin and the first group of pins, and adjusts the interface level of the signals provided for the first group of pins according to the signals of the reference voltage pin.

According to an eighth compact debug interface of the second aspect of the present application, there is provided a ninth compact debug interface of the second aspect of the present application, further comprising a second voltage adaptation unit; the second voltage adaptation unit is coupled with a second reference voltage pin and a first pin group, and adjusts the interface level of the signal provided for the second pin group according to the signal of the second reference voltage pin.

According to an eighth or ninth compact debug interface of the second aspect of the present application, there is provided a tenth compact debug interface of the second aspect of the present application, wherein the compression and decompression unit is arranged at the electronic device; the voltage adaptation unit is arranged at the commissioning device.

According to a third aspect of the present application, there is provided a first electronic system according to the third aspect of the present application, comprising a compact debug interface, an electronic device, and a debug device; the electronic device is coupled with the debugging device through the compact debugging interface; the compact debug interface is one of the first to tenth compact debug interfaces according to the second aspect of the present application.

According to a first electronic system of the third aspect of the present application, there is provided a second electronic system according to the third aspect of the present application, wherein

The electronic equipment comprises a control component, a host interface and the compact debugging interface; the control component comprises the first debug port and the second debug port; the host interface is coupled to the control component and is further configured to couple to a host for accessing the electronic device.

According to the third aspect of the present invention, there is provided a third electronic system, wherein the debug apparatus includes a second pin compression and decompression unit, a first port and a second port, wherein the first port is a port corresponding to the first debug port as a communication peer end, and the second port is a port corresponding to the second debug port as a communication peer end; the second pin compression and decompression unit selects one of the first port and the second port to couple to a first set of pins of the connector.

According to a third electronic system of the third aspect of the present application, there is provided a fourth electronic system of the third aspect of the present application, wherein the debugging device further comprises a voltage adaptation unit; the voltage adaptation unit is coupled with the second pin compression and decompression unit, the reference voltage pin and the first group of pins, and adjusts the interface level of the signal provided by the second pin compression and decompression unit to the first group of pins according to the signal of the reference voltage pin; the signal provided by the second pin compression and decompression unit to the first pin set is a signal of one of the first port and the second port.

According to a third or fourth electronic system of the third aspect of the present application, there is provided the fifth electronic system of the third aspect of the present application, wherein the debugging apparatus further includes a selection control unit; the selection control unit provides a first selection signal to a selection pin of the connector and provides a second selection signal to the second pin compression and decompression unit; the first selection signal indicates that one of the first debugging port and the second debugging port is selected, the second selection signal indicates that one of the first port and the second port is selected, and the debugging port indicated by the first selection signal and the end indicated by the second selection signal are opposite ends for communicating with each other and follow the same communication protocol.

According to one of the third to fifth electronic systems of the third aspect of the present application, there is provided the sixth electronic system of the third aspect of the present application, wherein the debugging apparatus further includes selecting the first connector and the second connector; the first connector couples the first port and the second connector couples the second port; in response to the first connector being connected to the second host, the selection control unit provides a first selection signal indicating selection of the first port; the selection control unit provides a first selection signal indicating selection of the second port in response to the second connector being connected to the second host.

According to one of the third to sixth electronic systems of the third aspect of the present application, there is provided a seventh electronic system of the third aspect of the present application, wherein the debugging device further includes a third port, a fourth port, and a second voltage adapting unit; the second voltage adapting unit is coupled with the second pin compressing and decompressing unit, the second reference voltage pin and the second group of pins, and adjusts the interface level of the signal provided by the second pin compressing and decompressing unit to the second pin group according to the signal of the second reference voltage pin; the signal provided by the second pin compression and decompression unit to the second pin group is a signal of one of the third port and the fourth port.

According to a seventh electronic system of the third aspect of the present application, there is provided the eighth electronic system of the third aspect of the present application, wherein the second selection signal indicates selection of one of the first port and the second port, and also indicates selection of one of the third port and the fourth port; the third port and the third debugging port are opposite ends for communication with each other and follow the same communication protocol, and the fourth port and the fourth debugging port are opposite ends for communication with each other and follow the same communication protocol.

According to a fourth aspect of the present application, there is provided a first method of commissioning an electronic device according to the fourth aspect of the present application, comprising: connecting a debugging device with the electronic device through a connector, wherein the electronic device comprises a plurality of debugging ports; the debugging equipment selects one of the debugging ports by connecting a selection pin of the connector; and the port of the debugging equipment accesses the selected debugging port through the signal carried by the first group of pins.

According to a fourth aspect of the present invention, there is provided a method of debugging an electronic device according to the second aspect of the present invention, wherein the number of pins of the first set of pins of the connector connecting the debugging device is smaller than the sum of the number of pins of the plurality of debugging ports.

A third method of commissioning an electronic device according to the fourth aspect of the present application is provided according to the fourth aspect of the present application, wherein in response to the commissioning device selecting one of the plurality of commissioning ports via a selection pin of the connector, the selected commissioning port is electrically connected with the first set of pins.

According to a third method of commissioning an electronic device according to the fourth aspect of the present application, there is provided a method of commissioning an electronic device according to the fourth aspect of the present application, wherein in response to the commissioning device selecting one of the plurality of commissioning ports via a selection pin of the connector, a first port of the commissioning device and the first set of pins are also electrically connected, wherein the first port and the selected commissioning port are opposite to each other in communication and follow the same communication protocol.

According to a fourth method of commissioning an electronic device according to the fourth aspect of the present application, there is provided the fifth method of commissioning an electronic device according to the fourth aspect of the present application, wherein in response to the commissioning device selecting one of the plurality of commissioning ports via a selection pin of the connector, an interface level of the selected commissioning port is also provided to a reference voltage pin of the connector; and the debugging equipment regulates signals provided for the first group of pins according to the interface level acquired by the reference voltage pins.

According to one of the methods of commissioning an electronic device of the fourth aspect of the present application, there is provided a method of commissioning an electronic device of the sixth aspect of the present application, further comprising: the debugging equipment selects another one of the debugging ports through a selection pin of the connector; the port of the debug device accesses the selected another debug port via signals carried by the first set of pins.

According to one of the methods of debugging an electronic device of the fourth aspect of the present application, there is provided the method of debugging an electronic device of the seventh aspect of the present application, wherein the electronic device is coupled to a first host and operates before connecting a debugging device to the electronic device through a connector; the method further comprises the following steps: connecting a second host to one of a plurality of second connectors of the debugging device; and selecting one of the plurality of debugging ports according to one of a plurality of second connectors connected with the second host, wherein the port coupled with the second connector connected with the second host and the selected debugging port are mutually opposite to each other in communication and follow the same communication protocol.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a schematic diagram of a prior art memory device;

FIG. 2A illustrates a block diagram of a coupled electronic device and a debugging device, according to an embodiment of the present application;

FIG. 2B illustrates a block diagram of a coupled storage device and debug device, according to yet another embodiment of the present application;

FIG. 2C illustrates a block diagram of a coupled storage device and debug device according to yet another embodiment of the present application;

FIG. 2D illustrates a block diagram of a coupled storage device and debug device, according to another embodiment of the present application;

FIG. 3A illustrates a block diagram of a coupled storage device and debug device, according to yet another embodiment of the present application;

FIG. 3B illustrates a block diagram of a coupled storage device and debug device, according to yet another embodiment of the present application;

FIG. 4A illustrates a block diagram of a coupled storage device, debug device, and debug host, according to an embodiment of the present application;

FIG. 4B illustrates a block diagram of a coupled storage device, debug device and debug host, according to yet another embodiment of the present application;

FIG. 5 illustrates a block diagram of a coupled storage device, debug device and debug host, according to yet another embodiment of the present application; and

FIG. 6 illustrates a flow diagram for accessing a debug port according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2A illustrates a block diagram of a coupled electronic device and a debugging device according to an embodiment of the application.

The electronic device comprises a control unit comprising two debug ports, denoted port 1A and port 2A, wherein "a" represents one of the two ports coupled to each other. Correspondingly, port 1B is coupled to and in communication with port 1A, and port 2B is coupled to and in communication with port 2A.

According to an embodiment of the application, the electronic device further includes a connector and a pin compression/decompression unit. The connector is a physical port for physically connecting the debugging device with the electronic device. The connector includes a plurality of pins. Pins of the connector are coupled to a pin compression/decompression unit. The pin compression/decompression unit also couples port 1A with port 2A. The number of wires required by the ports 1A and 2A is larger than the number of wires provided by the connector to the pin compression/decompression unit, so that a compressed port is provided, and the compression of the number of wires is realized. For example, the connector includes 19 pins that are coupled to a pin compression/decompression unit. Port 1A is connected to the pin compression/decompression unit by 18 wires, while port 2A is connected to the pin compression/decompression unit by 15 wires.

The pin compression/decompression unit of the electronic device "compresses" the pins required for port 1A and port 2A and connects them to the connector. So that one or more pins of the connector carry leads from both port 1A and port 2A. Meanwhile, the pin compression/decompression unit "decompresses" the pins provided by the connector and connects the decompressed pins to the port 1A and the port 2A.

In one embodiment, the pin compression/decompression unit time-shares signals of port 1A and port 2A. For example, first time, a pin of the connector is connected to a lead of port 1A, so that port 1A communicates with the debugging device through the connector. At a second time, different from the first time, the pins of the connector are connected to the leads of port 2A so that port 2A communicates with the debugging equipment through the connector.

In yet another embodiment, one or more flag pins in the connector indicate the selection of ports 1A and 2A. When the signal transmitted by the marking pin indicates the port 1A, other pins of the connector are connected with the lead wire of the port 1A, so that the port 1A communicates with debugging equipment through the connector; and when the signal transmitted by the flag pin indicates port 2A, the other pins of the connector are connected to the leads of port 2A, so that port 1A communicates with the debugging equipment through the connector.

The debugging device comprises a pin compression/decompression unit and a plurality of ports (marked as a port 1B and a port 2B). The leads of port 1B and port 2B are coupled to a pin compression/decompression unit. The pin compression/decompression unit of the debugging device is coupled with the connector of the electronic device. The pin compression/decompression unit of the debugging device provides the pins required by the port 1B and the port 2B to the connector of the electronic device after being compressed. Meanwhile, the pin compression/decompression unit of the debugging device "decompresses" the pins provided by the connector of the electronic device and connects the decompressed pins to the port 1B and the port 2B.

It is understood that fig. 2A shows two ports (1A and 2A), but embodiments of the present application may include other numbers of ports.

In an alternative embodiment, the debug apparatus includes a single port and does not include a pin compression/decompression unit. A single port of the debugging device couples a connector of the electronic device and indicates to the electronic device the debugging port to access by providing a specified selection signal to the connector of the electronic device. Thereby, a simplified debugging device can be used when only a single debugging port or the same type of debugging port needs to be accessed. The single port of the simplified debugging device is coupled to the connector, and the simplified debugging device also provides a designated selection signal to the connector of the electronic device to indicate to the electronic device the debugging port to be accessed.

According to an embodiment of the present application, a connector having standard physical dimensions is provided. The connector is provided with a specified pin count and arrangement. Pins of the provided connector include a pin set, a select pin, and optionally a reference voltage pin. The pins in the pin group transmit bidirectional signals and are used for bearing signals required by the debugging interface. The pin group carries signals required by two or more debugging interfaces, and the pin number of the pin group is less than the sum of the signals required by all the debugging interfaces carried by the pin group, or the pin number of the pin group is not more than the signal number of the debugging interface with the largest signal number in all the debugging interface groups carried by the pin group.

A selection pin of the provided connector unidirectionally passes signals. The two devices to which the provided connector couples are referred to as an electronic device and a commissioning device, respectively. Signals carried by select pins of the connector are provided by the debug device to the electronic device and are used to indicate one or more of all debug interfaces carried by the pin set.

The reference voltage pin of the provided connector unidirectionally transmits signals, and the signals carried by the reference voltage pin are provided by the electronic equipment to the electronic equipment and used for indicating the interface voltage used by the pin group for currently transmitting the signals. Optionally, the reference voltage value transmitted by the reference voltage pin is the same as the interface voltage used by the pin group to transmit the signal currently, so that the debugging device generates the signal transmitted on the pin group according to the reference voltage value transmitted by the reference voltage pin.

According to an embodiment of the application, further comprising a multi-channel switch coupled to the connector. Optionally, the multi-channel switch couples a pin set of the connector and couples each pin of the pin set to two or more leads. The multi-channel switch determines the lead to which each pin of the pin set is coupled based on a selection signal from a selection pin of the connector. The debug device is thereby instructed to connect the group of pins to a designated set of leads by applying a select signal to the select pins, the set of leads being coupled to one or more debug ports of the electronic device such that the debug device is provided access to the one or more debug ports.

The provided connectors have standard physical dimensions so that electronic devices using the provided connectors can be accessed by a variety of commissioning devices. Electronic devices may also have different configurations and provide different numbers of debug interfaces, and the debug device is used to access a variety of electronic devices. The connector and multi-channel switch provided provide a greater number of leads (compared to the number of pins of the connector) to the electronic device, thereby supporting a greater number of debug ports.

FIG. 2B illustrates a block diagram of a coupled storage device and debug device, according to yet another embodiment of the present application.

The storage device 210 is coupled to a host 220 through a host interface 230. The host 220 provides storage commands to the storage device 210 through the host interface 230. The storage device 210 is also coupled to a debug device 270 through a connector 240.

Alternatively, the storage device 210 is only coupled to the host 220 when operating normally. Debug device 270 is coupled to connector 240 to access the internal state of the memory device using debug device 270, as needed for debugging due to a failure or other reason. Still alternatively, during the development phase, the commissioning device 270 is always coupled with the storage device 210 through the connector 240.

Storage device 210 includes host interface 230, control unit 214, connector 240, multi-channel switch 220, debug port (1A)224, and debug interface (2A) 228. The debug port (1A)224 and the debug interface (2A)228 are each a debug interface for the control unit 214.

The connector 240 includes a plurality of pins, which are respectively referred to as a pin group and a selection pin. The pin group comprises a plurality of pins used for transmitting all pins required by the debugging port. For example, a pin set includes a number of pins capable of receiving the pins required for a port conforming to one of the USB, I2C, and JTAG protocols. The selection pin transmits a selection signal.

The multi-channel switch 220 couples the pin set of the connector 240 to one of the debug port (1A)224 and the debug port (2A)228 as indicated by the select signal of the select pin. For example, in response to the select signal being a first value, the leads of debug port (1A)224 are coupled to the pin set so that debug device 270 observes that connector 240 is transmitting signals for debug port 1A (224); in response to the select signal being the second value, the leads of debug port (2A)228 are coupled to the pin set so that debug device 270 observes that connector 240 is transmitting signals for debug port 2A (228). Thus, multi-channel switch 220 "compresses" all of the pins of debug port (1A)224 and debug port (2A)228 to the number of pins accommodated by the pin set.

The connector 240 provides a reduced pin count. While multi-channel switch 220 provides control unit 214 with a decompressed number of pins sufficient to accommodate all of the pins required for all of the debug interfaces of control unit 214.

On the other hand, when debug device 270 transmits signals to memory device 210, signals received by the pin set of connector 240 are provided to multi-channel switch 220. The select signal is also coupled to multi-channel switch 220. In response to the selection signal being asserted, the multi-channel switch provides signals received from the pin group to one of debug port (1A)224 and debug port (2A) 228. Thus, the pin groups of connector 240 transmit "compressed" signals, while multi-channel switch 220 provides "decompressed" signals to debug port (1A)224 and debug port (2A) 228.

According to an embodiment of the application, the debug device 270 is the sender of the selection signal and the storage device 210 is the receiver of the selection signal for the selection pin of the connector 240. Thus, debug port (1A)224 and debug port (2A)228 each operate as they are without knowledge of the state of the select signal. Thus, in some cases, for example, debug port (2A)228 is not connected to connector 240, but debug port (2A)228 still generates a signal. The debug port with which to communicate is selected by debug device 270 by applying a select signal to a select pin of connector 240.

Debug device 270 includes port (1B)274, port (2B)278, and multi-channel switch 280. Port (1B)274 is the port communicating with debug port 1A (224), and port 2B (278) is the port communicating with debug port 2A (228). Multichannel switch 280 selects the set of pins for which the signals of one of ports (1B)274 and 2B (278) are coupled to connector 240.

Alternatively, the number and the kind of the ports included in the debug device 270 need not correspond to the debug ports of the storage device 210 one-to-one. For example, the debug device 270 is a general purpose debug device that includes a variety of debug interfaces. When the commissioning device 270 is used to commission the storage device 210, one or more of the interfaces are selected to access the storage device 210.

FIG. 2C illustrates a block diagram of a coupled storage device and debug device according to yet another embodiment of the present application.

In contrast to the embodiment of fig. 2B, in fig. 2C, the connector 240 further includes one or more reference voltage pins. The reference voltage pin transmits a reference voltage signal. Storage device 210 is the provider of the reference voltage signal and debug device 270 is the receiver of the reference voltage signal. The voltages required by each of debug port (1A)224 and debug port (2A)228 depend on control unit 214, and not on debug device 270. To communicate with debug port (1A)224 and debug port (2A)228, debug apparatus 270 needs to know and use the respective interface voltages of debug port (1A)224 and debug port (2A) 228.

By way of example, the interface voltage of debug port (1A)224 is 3.3V, while the interface voltage of debug port (2A)228 is 1.8V. Debug device 270 applies a select signal of a first value to a select pin of connector 240 for communication with debug port (1A)224, and in response, the multi-channel switch applies a reference voltage indicative of a 3.3V interface voltage to the reference voltage pin, such that multi-channel switch 280 transmits signals with the set of pins using the 3.3V reference voltage. Debug device 270 applies a select signal of a second value to a select pin of connector 240 for communication with debug port (2A)228, and in response, the multi-channel switch applies a reference voltage indicative of a 1.8V interface voltage to the reference voltage pin, such that multi-channel switch 280 transmits signals with the set of pins using the 1.8V reference voltage.

In fig. 2C, the commissioning device further comprises a selection control unit 282. Selection control unit 282 applies a control signal to multi-channel switch 280 to instruct multi-channel switch 280 to select one of port (1B)274 and port (2B)278 to be coupled to connector 240. The selection control unit 282 also generates a selection signal that is provided to a selection pin of the connector 240. The selection signal corresponds to selection of the port (1B)274 and the port (2B)278 by the selection control unit 282. The selection control switch 282 is, for example, a key or a jumper, so that the user can operate the selection control switch 282 to instruct the debugging device 270 to use one of the port (1B)274 and the port (2B) 278. Still alternatively, the selection control unit 282 is controlled by a computer coupled to the commissioning device 270.

FIG. 2D illustrates a block diagram of a coupled storage device and debug device, according to another embodiment of the present application.

The storage device 212 is coupled to a host 220 through a host interface 230. The host 220 provides storage commands through the host interface 230 to the storage device 212. The storage device 212 is also coupled to a debug device 270 through a connector 240.

In contrast to the embodiment of fig. 2C, in fig. 2D, the control unit 214 of the storage device 212 shows only a single debug interface (1A) 214. The memory device 212 does not include a multi-channel switch. Instead, debug interface (1A)214 is coupled directly to the pin set of connector 240. The memory device need not respond to a select signal provided by a select pin of the connector.

Optionally, the memory device provides a reference voltage to a reference voltage pin of connector 240 to indicate the interface voltage of debug port (1A) 224.

Still optionally, the memory device does not provide a reference voltage to connector 240. The debug device 270 sets the interface voltage for port (1B)274 according to the protocol that port 1B (274) follows, and sets the interface voltage for port (2B)278 according to the protocol that port 2B (278) follows. So that debug device 270 does not use the reference voltage obtained from the reference voltage pin of connector 240.

Fig. 3A illustrates a block diagram of a coupled storage device and debug device according to yet another embodiment of the present application.

The storage device 310 is coupled to the host 320 through a host interface 330. The storage device 310 is also coupled to a debug device 370 through a connector 340.

The storage device 310 includes a control unit 314 and four debug interfaces (denoted as debug interface (1A)322, debug interface (2A)324, debug interface (3A)326, and debug interface (4A)328, respectively). The sum of the number of pins of the four debug interfaces of memory device 310 is greater than the number of pins of connector 340. The four debug interfaces of memory device 310 are coupled to connector 340 through multi-channel switch 320. Connector 340 includes pin set 1, pin set 2, a select pin, and two reference voltage pins. Pins of pin set 1 couple debug port (1A)322 and debug port (2A)324 through multi-channel switch 320; pins of pin set 2 couple debug port (3A)326 with debug port (4A)328 through multi-channel switch 320.

The select signal provided by the select pin indicates that the multi-channel switch couples pin set 1 to one of debug port (1A)322 and debug port (2A)324, and pin set 2 to one of debug port (3A)326 and debug port (4A) 328. The two reference voltage pins of the connector 340 respectively indicate the interface voltage of pin set 1 and the interface voltage of pin set 2.

The debug device 370 includes a multi-channel switch 380, port (1B)374, and port (2B) 378. Multi-channel switch 380 couples port (1B)374 and port (2B)378 to pin set 1 and/or pin set 2 of connector 340. The debug device 370 also provides a select signal to a select pin of the connector 340. Optionally, the multi-channel switch also receives a reference voltage provided by connector 340.

Port (1B) communicates with debug port (1A)322 of memory device 310, while port (2B) communicates with debug port (2A) 324. Optionally, the debug device 370 communicates with a different debug port (3A)326 or debug port (4A) 328. Still alternatively, debug port (3A)326 and/or debug port (4A)328 are communicated using other debug equipment.

Fig. 3B illustrates a block diagram of a coupled storage device and debug device according to still another embodiment of the present application.

The storage device 312 is coupled to the host 320 through a host interface 330. The storage device 312 is also coupled to a debug device 370 through a connector 340.

In contrast to the example of FIG. 3A, in the embodiment of FIG. 3B, the storage device 312 includes two control components (314 and 318). The control unit 314 includes a debug interface (1A) (322) and a debug interface (2A)324, and the control unit 318 includes a debug interface (3A)326 and a debug interface (4A) 328. By way of example, the control component 314 is a master device and the control component 318 is a slave device. Alternatively, the control unit 314 and the control unit 318 are chips independent of each other.

FIG. 4A illustrates a block diagram of a coupled storage device, debug device, and debug host, according to an embodiment of the present application.

The storage device 410 is coupled to a host 420 through a host interface 430. Storage device 410 is also coupled to debug device 470 by connector 440. The host 490 for debugging couples the debugging device 470 and accesses the debugging port of the memory device 410 through the debugging device 470.

The storage device 410 includes a control unit 414 and four debug interfaces (denoted as debug interface (1A)422, debug interface (2A)424, debug interface (3A)426, and debug interface (4A)428, respectively). The sum of the number of pins of the four debug interfaces of memory device 410 is greater than the number of pins of connector 440. The four debug interfaces of memory device 410 are coupled to connector 440 through multi-channel switch 420.

The connector 440 includes pin set 1, pin set 2, a select pin, and two reference voltage pins.

Debug device 470 includes multi-channel switch 480, port (1B)474, and port (2B) 478. Multi-channel switch 480 couples port (1B)474 and port (2B)478 to pin set 1 and/or pin set 2 of connector 440. The commissioning device 470 further comprises a selection control unit 482. The selection control unit 482 provides a selection signal to a selection pin of the connector 440. The selection control unit 482 also provides a selection signal to the multi-channel switch 480 to instruct the multi-channel switch 480 to select either port (1B)474 or port (2B)478 to be coupled to the connector 440. The selection signal provided by the selection control unit 482 to the multi-channel switch 480 corresponds to the selection signal it provides to the connector 440. Optionally, the multi-channel switch 480 also receives a reference voltage provided by the connector 440.

Host 490 for debugging may removably connect port (1B)474 and/or port (2B) 478. For example, the host 490 is connected to the port (2B)478 via the USB protocol, and the selection control unit 482 is a key switch. The user connects host 490 to port (2B)478 and sets selection control unit 482 so that multi-channel switch 480 couples port 2B (478) to connector 440. Selection control unit 482 also instructs multi-channel switch 420 to couple pin set 1 to debug port (2A)424 through the selection pins of connector 440 so that host 490 can access debug port (2A)424 through port (2B) 478.

It will be appreciated that removal of host 490 and/or debug device 470 may not affect the operation of storage device 410, nor the storage services provided by storage device 410 to host 420.

FIG. 4B illustrates a block diagram of a coupled storage device, debug device and debug host, according to yet another embodiment of the present application.

The storage device 410 is coupled to a host 420 through a host interface 430. Storage device 410 is also coupled to debug device 472 through connector 440. The host 490 for debugging couples the debugging device 472 and accesses the debugging port of the memory device 410 through the debugging device 472.

Compared to fig. 4A, the debug device 472 differs from the debug device 470 in that it further comprises a connector 484. The connector 484 is, for example, a USB connector. Connector 484 couples port 1B (474) and port 2B (478), and host 490 couples port 1B (474) and port 2B (478) via connector 484. Selection control unit 482 also couples 1B (474) and port 2B (478), and selects one of 1B (474) and port 2B (478) to electrically connect to connector 484. For example, in response to the selection control unit 482 outputting the first value, port 1B (474) electrically connects the connector 484, and port 2B (478) disconnects the connector 484; in response to the selection control unit 482 outputting the second value, port 1B (474) is disconnected from the connector 484, and port 2B (478) is electrically connected to the connector 484. Accordingly, in response to the selection control unit 482 outputting the first value, the multi-channel switch 480 electrically connects port 1B (474) to the connector 440, and in response to the selection control unit 482 outputting the second value, the multi-channel switch 480 electrically connects port 2B (478) to the connector 440.

The selection control unit 482 is, for example, a key. Optionally, the selection control unit 482 is further coupled to the host 490, such that the host 490 controls the value output by the selection control unit 482 through an electrical signal.

Thus, only a single connector or port of the host is used to access both ports (1B and 2B) of the debug device without having to frequently plug and unplug the wires to change the debug port used. Further, the selection control unit 482 may enable the port 1B (474) to couple, for example, the debug port 1A (422) and the debug port 3A (426) of the memory device 410 (e.g., both follow the JTAG protocol if the port 1B and the debug port 3A belong to the same class of port), and the port 2B (478) to couple, for example, the debug port 2A (424) and the debug port 4A (428) of the memory device 410 (e.g., both follow the I2C protocol if the port 2B and the debug port 4A belong to the same class of port) by providing signals to the selection pins of the connector 440.

FIG. 5 illustrates a block diagram of a coupled storage device, debug device and debug host, according to yet another embodiment of the present application.

The storage device 510 is coupled to the host 520 through a host interface 530. The storage device 510 is also coupled to a debug device 570 by a connector 540. The host (590 and 592) for debugging couples the debugging device 570, and accesses the debugging port of the storage device 510 through the debugging device 570.

The storage device 510 includes a control unit 514 and four debug interfaces (denoted as debug interface (1A)522, debug interface (2A)524, debug interface (3A)526, and debug interface (4A)528, respectively). The sum of the number of pins of the four debug interfaces of memory device 510 is greater than the number of pins of connector 540. The connector 540 includes pin set 1, pin set 2, a select pin, and two reference voltage pins. Optionally, the sum of the number of pins of the four debug interfaces of the memory device 510 is greater than the sum of the number of pins of pin group 1 and pin group 2 of the connector 540.

The four debug interfaces of memory device 510 are coupled to connector 540 through multi-channel switch 520. The multi-channel switch 520 electrically connects the pins of pin group 1 and/or pin group 2 to the leads of the four debug interfaces (debug interface (1A)522, debug interface (2A)524, debug interface (3A)526, and debug interface (4A)528) in a one-to-one correspondence. Because the number of pins is not consistent with the number of pins, the multi-channel switch 520 electrically connects the pins of the pin group 1 and/or the pin group 2 to 1, 2 or 3 of the four debugging ports according to the indication of the selection signal of the selection pin of the connector, and electrically disconnects the pins of the pin group 1 and/or the pin group 2 from other debugging ports.

The debug device 570 includes a multi-channel switch 580, port (1B)572, port (2B)574, port (3B)576, and port (4B) 578. Multichannel switch 580 couples port (1B)572, port (2B)574, port (3B)576, and port (4B)578 to pin set 1 and/or pin set 2 of connector 540.

The commissioning device 570 further comprises a plurality of level adaptation units (shown as 560, 561, 562, 563, 564, and 565). The level adaptation unit adapts the level of the output signal of the multi-channel switch 580 such that the level provided to the pins of the connector 540 meets the requirements of the transport protocol it carries. As an example, debug port 1A (522) uses 1.8V interface levels, while debug port 2A (524) uses 3.3V interface levels. Debug port 1A (522) and/or debug port 2A (524) provide the interface levels used by themselves to the reference voltage pins of connector 540. The reference voltage pin is coupled to one or more of the level adaptation units (560, 561, 562, 563, 564, and 565). Still by way of example, the select pin indicates that pin set 1 is electrically connected to debug port 1A (522), and multi-channel switch 520 also provides the interface level of debug port 1A (522) to the level adaptation units (560, 561, and 562) via the reference voltage pin. And multi-channel switch 580 couples the signal output by debug port 1B (572) to pin set 1 through level adaptation units (560, 561, and 562). The level adaptation units (560, 561, and 562) adjust the signal output from debug port 1B (572) to have an interface level of 1.8V in response to receiving the reference voltage of 1.8V, so that debug port 1A (522) can communicate with debug port 1B (572) with the same interface level. Still by way of example, selection control unit 582 disconnects debug port 1B (572) from pin set 1, and wishes to communicate with debug port 2A (524) using debug port 2B (574). By providing a select signal to the select pin, multi-channel switch 520 electrically connects debug port 2A (524) to pin set 1, while electrically disconnecting debug port 1A (522) from pin set 1. The multi-channel switch 520 also provides the interface level of debug port 2A (524) to the level adaptation units (560, 561, and 562) through the reference voltage pin. And multi-channel switch 580 couples the signal output by debug port 2B (574) to pin set 1 through level adaptation units (560, 561, and 562). The level adaptation units (560, 561, and 562) adjust the signal output from debug port 2B (574) to have an interface level of 3.3V in response to receiving the reference voltage of 3.3V, so that debug port 2A (524) can communicate with debug port 2B (574) with the same interface level. It will be appreciated that the level adaptation units (560, 561 and 562) also adjust the signal from pin set 1 output having a 3.3V interface level to an interface level acceptable to multi-channel switch 580 and/or debug port 2B (574) in response to receiving the 3.3V reference voltage.

Thus, according to embodiments of the present application, the debug device 570 has access to multiple interfaces through the connector 540, and also to multiple interfaces having different interface levels.

The commissioning device 570 further comprises a selection control unit 582. A selection control unit 582 provides a selection signal to a selection pin of connector 540. Selection control unit 582 also provides selection signals to multi-channel switch 580 to instruct multi-channel switch 580 to select port (1B)572, port (2B)574, port (3B)576 and/or port (4B)578 to couple to connector 540. The selection control unit 582 provides the selection signal to the multi-channel switch 580 corresponding to the selection signal it provides to the connector 540. Thus, the port selected by multi-channel switch 580 (e.g., port 1B (572)) corresponds to the port selected by multi-channel switch 520 (e.g., port 1A (522)).

The commissioning device also includes a plurality of connectors (shown in fig. 5 as connector 584 and connector 588). The connector 584 is, for example, a USB connector, and the USB588 is, for example, a UART connector. The debugging host 590 couples connector 584 and the debugging host 592 couples connector 588. Connector 584 couples port 1B (572) with port 2B (574), and connector 588 couples port 3B (576) with port 4B (578). Host 590 accesses port 1B or port 2B through connector 584 and, for example, accesses debug port 1A of the storage device through port 1B and debug port 2A of the storage device through port 2B.

Referring also to FIG. 5, a storage device 510 is operatively coupled to a host 520. The control section 514 outputs debug information and/or log information representing the operating state through each debug port according to the designated operating mode (610). It will be appreciated that even if the debug device 570 is not coupled through the connector 540, the control component 514 still generates debug information and/or information, however, optionally, the generated debug information/log information is not output through the debug port.

To obtain debug information, a debug device 570 is coupled to connector 540(620), and optionally a host (590 or 592) for debugging is also coupled to debug device 570. The debug port to be connected is selected by setting the selection control unit 582 of the debug apparatus (630). As an example, the selection control unit 582 is a key, and pressing the key represents accessing the debug port 1A (522) and the debug port 2A (524), and flipping the key represents accessing the debug port 3A (526) and the debug port 4A (528). In response to the key being pressed, multi-channel switch 580 connects the leads of port 1B and port 2B to pin set 1 and pin set 2, and debug device 570 also provides a select signal to a select pin of connector 540, such that multi-channel switch electrically connects pin set 1 to debug port 1A (522) and pin set 2 to debug port 2A (524). And debug port 1A (522) also provides the interface levels it uses to debug device 570 through the reference voltage pins of connector 540, while debug port 2A (524) provides the interface levels it uses to debug device 570 through the reference voltage pins of connector 540. Thus, the signal that the debug device 570 is coupled to pin group 1 assumes the interface level of debug port 1A (522), while the signal that the debug device 570 is coupled to pin group 2 assumes the interface level of debug port 2A (524).

Since multi-channel switch 520 and multi-channel switch 580 establish an electrical connection from debug port 1A (522) through pin set 1 of connector 540 to port 1B (572), host 590 obtains debug information (640) provided by debug port 1A (522) by accessing port 1B (572). And the host also sends debug commands to debug port 1A (522) by sending data to port 1B (572). Optionally, step 630 and step 640 are also repeated. At step 630, the host for debugging is coupled to one of the connectors (584 and 586) and/or the ports (1B, 2B, 3B, and 4B) and the debugging ports (1A, 2A, 3A, and 4A) to be accessed are selected by the selection control unit 582, and at step 640, the connected ports are accessed to acquire debugging information.

Multichannel switch 520 and multichannel switch 580 make an electrical connection from debug port 2A (524) through pin set 2 of connector 540 to port 2B (574). For example, host 590 obtains debug information provided by debug port 2A (524) via access port 2B (574).

In an alternative embodiment, the debug device 570 detects which of a plurality of connectors (584, 588) is connected to the host, and the multi-channel switch 580 selects the port connected to the connector 540 based on the detection. For example, if a host is connected to connector 584, port 1B (572) and/or port 2B (574) are connected to connector 540; if a host is connected to connector 588, port 3B (576) and/or port 4B (578) are connected to connector 540.

According to the connector provided by the embodiment of the application, the debugging port of the electronic equipment is exposed to the external debugging equipment, and the plurality of debugging ports can be displayed, wherein the sum of the number of the leads of the displayed debugging ports is larger than the number of the pins of the pin group of the connector. Thereby providing a greater number of debug ports out with a limited number of pins. The limited pin count limits the size of the connector, thereby helping to reduce the volume of the electronic device and reducing cost. The connector also includes a select pin that provides a select signal to the debugged electronic device. The select pin is used to indicate a selection of the plurality of debug ports provided. Optionally, the connector further comprises a reference voltage pin to provide a reference voltage to the debug device. The reference voltage pin is used to indicate an interface level used by a selected port of the electronic device.

According to the embodiment of the application, the compact debugging interface comprises a connector and a multi-channel switch. The compact debug interface is disposed in an electronic device, and the multi-channel switch couples the pin sets of the connector and presents the sets of pins to the electronic device. Each set of leads couples, for example, one of the debug ports of the electronic device. The selection pin of the connector is also coupled to the multi-channel switch and instructs the multi-channel switch to connect one of the plurality of sets of leads to the set of leads.

Optionally, the connector implemented according to the present application further includes a power pin for supplying power to the electronic device. By way of example, power is supplied by a standby power supply of the electronic device through a power pin. The host interface of the electronic host also comprises a power pin, and power is supplied to each part of the electronic equipment through the power pin of the host interface.

Although the present application has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.

Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A connector of a compact debugging interface comprises a first group of pins and a selection pin;

each pin of the first group of pins is used for transmitting a plurality of signals of the first debugging port and the second debugging port;

the selection signal transmitted by the selection pin indicates that a plurality of signals of a first debugging end or a second debugging port are electrically connected to a first group of pins, wherein the number of the pins of the first group of pins is less than the sum of the number of the signals of the first debugging port and the second debugging port.

2. The connector of claim 1, further comprising a reference voltage pin;

the signal of the reference voltage pin indicates an interface level used by the first debug port or the second debug port.

3. The connector of claim 1 or 2, further comprising a second set of pins;

each pin of the second group of pins is used for transmitting a plurality of signals of the third debugging port and the fourth debugging port;

the select pin transmits a select signal indicating that a plurality of signals of the third debug port or the fourth debug port are electrically connected to the second pin group.

4. A compact debug interface includes a connector and a pin compression and decompression unit;

the connector is according to one of claims 1-3;

the pin compression and decompression unit couples the first set of pins with the select pin.

5. The compact debug interface of claim 4, said pin compression and decompression unit being a multi-channel switch;

the multi-channel switch electrically connects the first set of pins to one of a first set of leads or a second set of leads in response to a select signal of the select pin;

the multi-channel switch is also coupled with the reference voltage pin;

in response to a select signal of the select pin, the multi-channel switch provides an interface level used by one of the first set of leads or the second set of leads indicated by the select signal to the reference voltage pin.

6. The compact debug interface of claim 4 or 5, further comprising a voltage adaptation unit;

the voltage adapting unit is coupled with the reference voltage pin and the first group of pins, and adjusts the interface level of the signals provided for the first group of pins according to the signals of the reference voltage pin.

7. An electronic system comprises a compact debugging interface, an electronic device and a debugging device;

the electronic device is coupled with the debugging device through the compact debugging interface;

the compact debug interface is according to any of claims 4-6.

8. The electronic system of claim 7, wherein

The debugging equipment comprises a second pin compression and decompression unit, a first port and a second port, wherein the first port is a port which is corresponding to the first debugging port and is used as a communication opposite end, and the second port is a port which is corresponding to the second debugging port and is used as a communication opposite end;

the second pin compression and decompression unit selects one of the first port and the second port to couple to a first set of pins of the connector.

9. The electronic system of claim 8, wherein

The debugging equipment further comprises a selection control unit;

the selection control unit provides a first selection signal to a selection pin of the connector and provides a second selection signal to the second pin compression and decompression unit;

the first selection signal indicates that one of the first debugging port and the second debugging port is selected, the second selection signal indicates that one of the first port and the second port is selected, and the debugging port indicated by the first selection signal and the end indicated by the second selection signal are opposite ends for communicating with each other and follow the same communication protocol.

10. An electronic system according to claim 8 or 9, wherein

The debugging device further comprises a first connector and a second connector which are selected;

the first connector couples the first port and the second connector couples the second port;

in response to the first connector being connected to the second host, the selection control unit provides a first selection signal indicating selection of the first port;

the selection control unit provides a first selection signal indicating selection of the second port in response to the second connector being connected to the second host.