CN211785912U

CN211785912U - Field-effect tube applied to current-limiting protection loop and failure detection circuit

Info

Publication number: CN211785912U
Application number: CN201922166185.4U
Authority: CN
Inventors: 叶继明; 谢永涛; 南怀志
Original assignee: Henan Gdlion Measurement & Control Technology Co ltd
Current assignee: Henan Gdlion Measurement & Control Technology Co ltd
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-10-27
Anticipated expiration: 2029-12-06

Abstract

The utility model provides a be applied to field effect transistor and failure detection circuit among current-limiting protection return circuit, use current-limiting protector and detect whether inefficacy in alternating current return circuit, including last MOSFET pipe, lower MOSFET pipe, the live wire of the drain electrode wiring circuit of top tube, the drain electrode wiring load of low tube, another termination zero line of load, the source electrode of the source electrode low tube of top tube links together ground connection, the top tube grid is connected with first microcontroller, the low tube grid is connected with the second microcontroller, when the alternating current is in positive half a week, the top tube forward switches on, the low tube is reverse switched on by inside backward diode effect, when the alternating current is in negative half a week, the low tube forward switches on, the top tube is reverse switched on by inside backward diode effect; and a failure detection circuit is additionally arranged, and the microprocessor is used for detecting whether the port can receive the pulse signal sent by the pulse applying port to judge whether the port fails.

Description

Field-effect tube applied to current-limiting protection loop and failure detection circuit

Technical Field

The utility model belongs to the technical field of current limiting protector MOSFET pipe, concretely relates to be applied to field effect transistor and failure detection circuit in current-limiting protection return circuit.

Background

In the field of electric fire monitoring and detecting application, when an electric circuit has overload or short-circuit fault, the current-limiting protector can quickly cut off a power supply circuit within 150 microseconds, so that fire caused by that electric sparks generated by short circuit ignite surrounding objects or the circuit spontaneously ignites is avoided. The current-limiting protector adopts MOSFET tubes as off-off control devices, the MOSFET tubes have zero-point ohm internal resistance, the MOSFET tubes are in a conducting state when in normal work, and if the line current is too large or the short-circuit state current is reached, the microcontroller sends an instruction to enable the MOSFET tubes to be immediately switched off. Thus avoiding fire hazard caused by electric sparks generated by overlarge current or short circuit of the electric circuit. The MOSFET tube can only be used for controlling a direct current circuit originally, a circuit is difficult to design by using the MOSFET tube in an alternating current loop to control the circuit, the MOSFET tube is divided into three electrodes of a drain electrode (D), a grid electrode (G) and a source electrode (S), the situation is different when the MOSFET tube has failure conditions, if the MOSFET tube fails and is in short circuit, when the current suddenly increases and the power supply needs to be quickly cut off, the microprocessor applies low level to cut off the MOSFET tube, but the short circuit exists, the current can still pass through, and the protection effect is not achieved.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a be applied to field effect transistor and inefficacy detection circuit in current-limiting protection return circuit for make use current-limiting protector MOSFET pipe and detect whether it became invalid in exchanging the return circuit.

The technical proposal of the utility model for solving the technical problem is that: a field effect transistor applied to a current-limiting protection loop comprises an upper MOSFET Q1, a lower MOSFET Q2, a drain D1 of an upper tube Q1, a drain D2 of a lower tube Q2, a source S1 of the upper tube, a source S2 of the lower tube, a gate G1 of the upper tube, a gate G2 of the lower tube, a first microcontroller GC1 and a second microcontroller GC2, wherein the drain D1 of the upper tube Q1 is connected with a live wire L of a circuit, the drain D2 of the lower tube Q2 is connected with a load RL, and the other end of the load is connected with a neutral wire N. The source S1 of the upper tube and the source S2 of the lower tube are connected together and to the system ground GND, the gate G1 of the upper tube is connected to the first microcontroller GC1, and the gate G2 of the lower tube is connected to the second microcontroller GC 2.

A failure detection circuit based on a field effect transistor applied to a current-limiting protection loop comprises a capacitor C1, a capacitor C2, a sampling resistor R1, a first pulse applying port pulse 1, a second pulse applying port pulse 2 and a microprocessor detection port Test, wherein the first pulse applying port pulse 1 is connected with a drain D1 of an upper tube Q1 through a capacitor C1, the second pulse applying port pulse 2 is connected with a drain D2 of a lower tube Q2 through a capacitor C2, a source S1 of the upper tube and a source S2 of the lower tube are connected together, the upper tube and the lower tube are connected with a system ground GND through a sampling resistor R1, and the sampling resistor is provided with a microprocessor detection port Test.

The utility model has the advantages that: two MOSFET tubes are used on the basis of the original one MOSFET tube, the drain D1 of the upper MOSFET tube Q1 is connected with the live wire L of a circuit, the drain D2 of the lower MOSFET tube Q2 is connected with the load RL, the other end of the load is connected with the zero line N, the grid G1 of the upper tube is connected with the first microcontroller GC1, and the grid G2 of the lower tube is connected with the second microcontroller GC2, so that when the alternating current is in the positive half cycle, the upper tube Q1 is conducted in the forward direction, the lower tube Q2 is conducted in the reverse direction under the action of an internal reverse diode, when the alternating current is in the negative half cycle, the lower tube Q2 is conducted in the forward direction, and the upper tube Q1 is conducted in the reverse direction under the action of the internal reverse diode, therefore, the alternating current can; a failure detection circuit consisting of a capacitor C1, a capacitor C2, a first pulse applying port pulse 1, a second pulse applying port pulse 2 and a microprocessor detection port Test is additionally arranged on an MOSFET used in an alternating current circuit, so that whether the microprocessor detection port Test can receive pulse signals sent by the first pulse applying port pulse 1 and the second pulse applying port pulse 2 or not is judged to be failed.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in the first drawing, the present invention includes an upper MOSFET Q1, a lower MOSFET Q2, a drain D1 of an upper transistor Q1, a drain D2 of a lower transistor Q2, a source S1 of the upper transistor, a source S2 of the lower transistor, a gate G1 of the upper transistor, a gate G2 of the lower transistor, a first microcontroller GC1, and a second microcontroller GC2, wherein the drain D1 of the upper transistor Q1 is connected with a live line L, the drain D2 of the lower transistor Q2 is connected with a load RL, and the other end of the load is connected with a neutral line N. The source S1 of the upper tube and the source S2 of the lower tube are connected together and to the system ground GND, the gate G1 of the upper tube is connected to the first microcontroller GC1, and the gate G2 of the lower tube is connected to the second microcontroller GC 2.

Based on a failure detection circuit applied to a MOSFET in a current-limiting protection loop, the failure detection circuit comprises a capacitor C1, a capacitor C2, a sampling resistor R1, a first pulse applying port pulse 1, a second pulse applying port pulse 2 and a microprocessor detection port Test, wherein the first pulse applying port pulse 1 is connected with a drain D1 of an upper tube Q1 through a capacitor C1, the second pulse applying port pulse 2 is connected with a drain D2 of a lower tube Q2 through a capacitor C2, a source S1 of the upper tube and a source S2 of the lower tube are connected together, the upper tube and the lower tube are connected with a system ground GND through the sampling resistor R1, and the sampling resistor is provided with the microprocessor detection port Test.

The capacitors C1 and C2 can block the high voltage from one side of the MOSFET tube, so as to prevent the microprocessor from being burned out due to the high voltage, and the capacitors C1 and C2 have the function of coupling the pulse signals from the first pulse applying port pulse 1 and the second pulse applying port pulse 2.

When the alternating current is switched on in advance, positive voltages are applied to GC1 and GC2, when the alternating current is in a positive half cycle, an upper tube Q1 is conducted in a forward direction, and a lower tube Q2 is conducted in a reverse direction under the action of an internal reverse diode; when the AC current is in the negative half cycle, the lower tube Q2 is conducting in the forward direction, and the upper tube Q1 is conducting in the reverse direction under the action of an internal reverse diode. Thus, the alternating current can be conducted in both the positive half cycle and the negative half cycle.

When the alternating current is turned off in advance, a low level is applied to both GC1 and GC2, when the alternating current is in a positive half cycle, the lower tube Q2 is in a reverse conducting state, but the upper tube Q1 is in a positive cut-off state, and current cannot pass through; when the alternating current is in the negative half cycle, the upper tube Q1 is in a reverse conducting state, but the lower tube Q2 is in a positive direction cutoff state, and the current cannot pass through. By utilizing the principle, when the loop current is increased or short-circuit fault occurs, after the microprocessor detects that the current exceeds the limit, the microprocessor immediately applies low level to G1 and G2, the upper tube and the lower tube are simultaneously cut off in a very short time, and the current is instantly changed into zero, so that the power supply circuit is effectively protected, and the occurrence of fire is avoided.

The complete work flow for detecting whether the MOSFET transistors Q1 and Q2 fail is as follows: when the alternating current is at the zero crossing point, no voltage exists between the drain D1 of the upper tube Q1 and the drain D2 of the lower tube Q2, and no alternating current flows from the upper tube Q1 and the lower tube Q2. The first microcontroller GC1 applies a low level to turn off the upper tube Q1, the third microcontroller for sending a pulse signal sends a pulse signal of 5 microseconds from the first pulse applying port pulse 1, the third microcontroller is connected with the first pulse applying port pulse 2, at this time, if the upper tube Q1 does not fail, the pulse signal cannot be transmitted to the microprocessor detecting port Test through the capacitor C1 and the upper tube Q1 due to the turn-off of the upper tube Q1, and if the signal on Test cannot be detected, it is determined that the upper tube Q1 does not fail; on the contrary, when the pulse signal is transmitted to the Test, the existence of the sampling resistor R1 enables the pulse signal to generate a weak voltage at the Test, and if the weak voltage signal can be detected at the Test, it indicates that the pulse signal passes through the upper tube Q1, and it can be determined that the upper tube Q1 is short-circuited and failed.

After a further period of time, the second microcontroller GC2 applies a low level to turn off the down tube Q2, the fourth microcontroller for sending a pulse signal sends a pulse signal of 5 microseconds from the second pulse applying port pulse 2, the fourth microcontroller is connected to the second pulse applying port pulse 2, and if the pulse signal cannot be detected in Test, it is determined that the down tube Q2 has not failed; on the contrary, if the pulse signal can be detected at Test, it is determined that the lower tube Q2 is short-circuited and failed.

The time interval for sending the pulse signal can be set according to actual conditions.

During normal operation of the upper tube Q1 and the lower tube Q2, the voltage cannot be detected when the microprocessor detects the Test of the port Test because both Q1 and Q2 are in a conducting state. If one of Q1 or Q2 fails to open circuit, the microprocessor Test port Test can detect the voltage, and then the MOSFET open circuit failure can be judged.

No matter whether the MOSFET is short-circuit failure or open circuit failure, the failure detection circuit can detect the failure, and once the MOSFET failure is detected, an alarm is sent to inform a manager to process, so that the line loss protection effect caused by the failure of the device is avoided.

Two MOSFET tubes are used on the basis of the original one MOSFET tube, the drain D1 of the upper MOSFET tube Q1 is connected with the live wire L of a circuit, the drain D2 of the lower MOSFET tube Q2 is connected with the load RL, the other end of the load is connected with the zero line N, the grid G1 of the upper tube is connected with the first microcontroller GC1, and the grid G2 of the lower tube is connected with the second microcontroller GC2, so that when the alternating current is in the positive half cycle, the upper tube Q1 is conducted in the forward direction, the lower tube Q2 is conducted in the reverse direction under the action of an internal reverse diode, when the alternating current is in the negative half cycle, the lower tube Q2 is conducted in the forward direction, and the upper tube Q1 is conducted in the reverse direction under the action of the internal reverse diode, therefore, the alternating current can; a failure detection circuit consisting of a capacitor C1, a capacitor C2, a first pulse applying port pulse 1, a second pulse applying port pulse 2 and a microprocessor detection port Test is additionally arranged on an MOSFET used in an alternating current circuit, so that whether the microprocessor detection port Test can receive pulse signals sent by the first pulse applying port pulse 1 and the second pulse applying port pulse 2 or not is judged to be failed.

Claims

1. A field effect transistor applied to a current-limiting protection loop is characterized in that: the high-voltage power supply comprises an upper MOSFET Q1, a lower MOSFET Q2, a drain D1 of an upper transistor Q1, a drain D2 of a lower transistor Q2, a source S1 of the upper transistor, a source S2 of the lower transistor, a gate G1 of the upper transistor, a gate G2 of the lower transistor, a first microcontroller GC1 for detecting whether current is over-limited and sending a level signal to the gate G1 of the upper transistor, a second microcontroller GC2 for detecting whether current is over-limited and sending a level signal to the gate G2 of the lower transistor, wherein the drain D1 of the upper transistor Q1 is connected with a live wire L of a circuit, the drain D2 of the lower transistor Q2 is connected with a load RL, the other end of the load is connected with a neutral wire N, the source S1 of the upper transistor and the source S2 of the lower transistor are connected together, a system ground GND is connected, the gate G1 of the upper transistor is connected with a first microcontroller GC1, and the.

2. The failure detection circuit of claim 1, wherein the circuit comprises: the circuit comprises a capacitor C1, a capacitor C2, a first pulse applying port pulse 1, a second pulse applying port pulse 2 and a microprocessor detection port Test, wherein the first pulse applying port pulse 1 is connected with a drain D1 of an upper tube Q1 through a capacitor C1, the second pulse applying port pulse 2 is connected with a drain D2 of a lower tube Q2 through a capacitor C2, a source S1 of the upper tube and a source S2 of the lower tube are connected together and connected with a system ground GND, and the microprocessor detection port Test is arranged between a connection point of the source S1 of the upper tube and the source S2 of the lower tube and the system ground GND.

3. The failure detection circuit of claim 2, wherein the failure detection circuit comprises: the circuit also comprises a sampling resistor R1 which is connected with the system ground GND through a sampling resistor R1, and the microprocessor detection port Test is arranged on the sampling resistor.