CN211509069U - Router - Google Patents
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- CN211509069U CN211509069U CN202020532624.9U CN202020532624U CN211509069U CN 211509069 U CN211509069 U CN 211509069U CN 202020532624 U CN202020532624 U CN 202020532624U CN 211509069 U CN211509069 U CN 211509069U
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Abstract
The utility model discloses a router belongs to the computer network field. The router comprises a main control board and a service board, wherein the main control board comprises a first main control programmable device module, a second main control programmable device module and a main control CPU module which are in communication connection with each other, and the first main control programmable device module and the second main control programmable device module are in communication connection with a main control connector; the service board comprises a service CPU module, a first service programmable device module and a second service programmable device module which are in communication connection with each other, and the service CPU module, the first service programmable device module and the second service programmable device module are all in communication connection with the service connector; the main control connector and the service connector are in communication connection through a control path.
Description
Technical Field
The utility model relates to a computer network field, concretely relates to router.
Background
At present, the revolution of information technology is changing day by day, which has a profound influence on the development of the fields of national politics, economy, society, military and the like, and the information security becomes a major strategic problem of the security and development of the concerned countries; in order to guarantee the reliability and the safety of the communication network, the key for network construction is to improve the autonomous controllability of the router. Through the development of over ten years, China realizes the localization of network equipment in the whole network domain and can provide serialized route switching products. However, core hardware such as a network processor of a home-made router and the like are foreign products, and information safety hidden dangers exist, so that autonomy of the router is urgently needed to be achieved based on a home-made processor (CPU), and basic guarantee is provided for national network and information safety.
SUMMERY OF THE UTILITY MODEL
To the above insufficiency among the prior art, the utility model aims at providing a router to improve communication network's security.
In order to achieve the purpose of the invention, the utility model adopts the technical scheme that:
the router comprises a main control board and a service board, wherein the main control board comprises a first main control programmable device module, a second main control programmable device module and a main control CPU module which are in communication connection with each other, and the first main control programmable device module and the second main control programmable device module are in communication connection with a main control connector;
the service board comprises a service CPU module, a first service programmable device module and a second service programmable device module which are in communication connection with each other, and the service CPU module, the first service programmable device module and the second service programmable device module are all in communication connection with the service connector;
the main control connector and the service connector are in communication connection through a control path.
Furthermore, the number of the main control boards is 2, all the main control connectors are in communication connection with each other through control paths, and all the main control connectors are in communication connection with the service connectors through control paths.
Furthermore, the number of the service boards is 2 or 3, all the service connectors are in communication connection with each other through data paths, and all the main control connectors are in communication connection with all the service connectors through control paths.
Further, the master control CPU module comprises a master control Feiteng processor in communication connection with the master control connector, and the master control Feiteng processor is in communication connection with the SSD, the first DRAM memory, the first BIOS chip, the serial port, the management port and the USB port respectively.
Further, the first main control programmable device module comprises a main control FPGA chip which is in communication connection with the main control connector and the main control Feiteng processor.
Furthermore, the second main control programmable device module comprises a main control EPLD chip which is respectively in communication connection with the main control connector, the main control Feiteng processor and the main control FPGA chip, and the main control EPLD chip is respectively in communication connection with the main control power circuit, the main control synchronous clock circuit, the reset button and the main control LED indicator lamp.
Further, the service CPU module comprises a service Feiteng processor which is in communication connection with the service connector, and the service Feiteng processor is in communication connection with the second DRAM memory and the second BIOS chip respectively.
Further, the first service programmable device module comprises a service FPGA chip which is in communication connection with the service connector and the service Feiteng processor, and the service FPGA chip is in communication connection with the third DRAM memory and the TCAM memory respectively.
Further, the second service programmable device module comprises a service EPLD chip respectively in communication connection with the service connector, the service soar processor and the service FPGA chip, and the service EPLD chip is respectively in communication connection with the service power supply circuit, the service synchronous clock circuit and the service LED indicator lamp.
Further, to expand the interface type of the service board, the router further includes an expansion interface module in communication connection with the service FPGA chip and the service EPLD chip, respectively.
The utility model has the advantages that: the function of the router is realized based on the main control board and the service board, so that the dependence of the router on import devices is reduced, the autonomy level of network equipment is improved, and the safety of a communication network is improved. Meanwhile, potential safety hazards such as backdoor, loophole and trap caused by imported devices are avoided, the safety of a communication network is guaranteed, and support is provided for autonomous production and guarantee of network equipment in China.
Drawings
FIG. 1 is a functional block diagram of a router in an exemplary embodiment;
FIG. 2 is a schematic block diagram of a main control board in the embodiment shown in FIG. 1;
fig. 3 is a schematic block diagram of the service board in the embodiment shown in fig. 1.
Detailed Description
The following detailed description of the present invention will be made with reference to the accompanying drawings so as to facilitate the understanding of the present invention by those skilled in the art. It should be understood that the embodiments described below are only some embodiments of the invention, and not all embodiments. All other embodiments obtained by a person skilled in the art without any inventive step, without departing from the spirit and scope of the present invention as defined and defined by the appended claims, fall within the scope of protection of the invention.
As shown in fig. 1, the router includes a main control board and a service board. As shown in fig. 2, the main control board includes a first main control programmable device module, a second main control programmable device module, and a main control CPU module, which are in communication connection with each other, and both the first main control programmable device module and the second main control programmable device module are in communication connection with the main control connector.
As shown in fig. 3, the service board includes a service CPU module, a first service programmable device module, and a second service programmable device module, which are communicatively connected with each other, and the service CPU module, the first service programmable device module, and the second service programmable device module are all communicatively connected with the service connector.
As shown in fig. 1, the master connector and the service connector are communicatively connected via a control path.
In implementation, as shown in fig. 1, the number of the main control boards in this scheme is 2, all the main control connectors are in communication connection with each other through the control path, and all the main control connectors are in communication connection with the service connector through the control path.
As shown in fig. 1, the number of the service boards is 2 or 3, all the service connectors are communicatively connected to each other through a data path, and all the master control connectors and all the service connectors are communicatively connected to each other through a control path.
The main control connector and the service connector are connected through the backplane connector to achieve conduction of the control path and the data path.
As shown in fig. 2, the master CPU module includes a master fly-away processor in communication connection with the master connector, and the master fly-away processor is in communication connection with the SSD, the first DRAM memory, the first BIOS chip, the serial port, the management port, and the USB port, respectively.
As shown in fig. 2, the first master control programmable device module includes a master control FPGA chip communicatively connected to the master control connector and the master control soar processor.
As shown in fig. 2, the second master control programmable device module includes a master control EPLD chip respectively in communication connection with the master control connector, the master control soar processor, and the master control FPGA chip, and the master control EPLD chip is respectively in communication connection with the master control power supply circuit, the master control synchronous clock circuit, the reset button, and the master control LED indicator.
Specifically, the main control Feiteng processor is connected with a main control FPGA chip through an SGMII interface and a PCI interface; the main control Feiteng processor is connected with the main control EPLD chip through an ESPI interface, a GPIO interface and a MISC interface; and the main control FPGA chip is connected with the main control EPLD chip through a GPIO interface.
As shown in fig. 3, the service CPU module includes a service-fly-processor communicatively connected to the service connector, and the service-fly-processor is communicatively connected to the second DRAM memory and the second BIOS chip, respectively.
As shown in fig. 3, the first service programmable device module includes a service FPGA chip communicatively connected to the service connector and the service flyover processor, and the service FPGA chip is communicatively connected to the third DRAM memory and the TCAM memory, respectively.
As shown in fig. 3, the second service programmable device module includes a service EPLD chip respectively connected to the service connector, the service boomerang processor, and the service FPGA chip in communication, and the service EPLD chip is respectively connected to the service power supply circuit, the service synchronous clock circuit, and the service LED indicator in communication.
Specifically, the service Feiteng processor is connected with a service FPGA chip through a PCIE interface, an SGMII interface and a GPIO interface; the service Feiteng processor is connected with the service EPLD chip through an ESPI interface; and the service FPGA chip is connected with the service EPLD chip through the GPIO interface.
As shown in fig. 3, for expanding the interface type of the service board, the router further includes an expansion interface module in communication connection with the service FPGA chip and the service EPLD chip, respectively. Different types of interface daughter cards, such as gigabit, terabyte, POS, etc., can be extended. Specifically, the expansion interface module is connected with a service FPGA chip through an SGMII interface and an XAUI interface; the expansion interface module is connected with the service EPLD chip through an ESPI bus.
The main control CPU module is a management control module of the router and comprises routing protocol, routing table management and configuration management functions. The first main control programmable device module mainly realizes the exchange function of the control path and is responsible for the exchange function of control management path data between the main control board and between the main control board and the service board. The second main control programmable device module mainly has the case management function and comprises the management function of double main controls, the synchronous clock management function, the power supply management function and the service board management function.
The service CPU module is a forwarding and forwarding control module of the router, and has the main functions of line card and interface card management, table item management and data plane service processing. The first service programmable device module mainly has the functions of data processing acceleration, control path switching and flow management. The second service programmable device module mainly has a line card management function, assists the main control to complete the chassis management function, and comprises the line card power-on and power-off, reset, clock synchronization and LED indicator lamp control.
The working process and principle of the router are as follows:
after the equipment is powered on, the main control EPLD chip and the service EPLD chip are started firstly, and then the equipment completes the hardware starting of the whole machine under the control of the main control EPLD chip and the service EPLD chip. After the hardware of the main control card and the service card is powered on and started, the main control CPU module reads the software mirror image in the SSD to complete the starting of the main control software system. After the main control software system is started, the service card acquires the service card software mirror image from the file system of the main control software through the control channel to finish the starting of the service card. After the main control card software system and the service card software system are started, the main control card and the service card are synchronized, and then the whole software configuration loading is completed, so that the equipment is started.
After the equipment finishes the software and hardware starting, the network data flow enters the expansion interface module through the service interface in the expansion interface module, frame synchronization, FCS processing and the like are finished in the expansion interface module, then the network data flow is sent to a service FPGA chip of the service board through an internal SGMII/XAUI passage, and then the service FPGA chip finishes the uplink processing of flow splitting, flow filtering, route table checking, route forwarding decision and the like; and determining an output interface of the message and a service board where the output interface is located according to the route forwarding decision information, if the output service board is the local board, directly entering a service FPGA chip of the local board for downlink processing, if the output service board is not the local board, entering the service FPGA chip of the target service board for downlink processing after passing through a service processor and a backplane connector, wherein the downlink processing of the service FPGA chip comprises flow management, flow scheduling, packet encapsulation and the like, then reaching the expansion interface module through an internal SGMII/XAUI passage, and finally sending through the output interface corresponding to the expansion interface module. The service FPGA chip distinguishes different information in the data stream according to the specific field, sends data information, protocols or control information which cannot be identified to a service CPU module in the board, performs flow classification and route searching in the service CPU module, performs downlink processing on the service FPGA chip of the data information sent to a target board, and then sends the data information through the expansion interface module; and the protocol or control information is sent to the target main control FPGA chip through the service FPGA chip, the service connector and the backplane connector, and finally sent to the main control CPU module for processing through the main control FPGA chip.
Claims (10)
1. A router is characterized by comprising a main control board and a service board, wherein the main control board comprises a first main control programmable device module, a second main control programmable device module and a main control CPU module which are in communication connection with each other, and the first main control programmable device module and the second main control programmable device module are in communication connection with a main control connector;
the service board comprises a service CPU module, a first service programmable device module and a second service programmable device module which are in communication connection with each other, and the service CPU module, the first service programmable device module and the second service programmable device module are in communication connection with the service connector;
and the main control connector and the service connector are in communication connection through a control path.
2. The router according to claim 1, wherein the number of the master control boards is 2, all the master control connectors are communicatively connected to each other through a control path, and all the master control connectors are communicatively connected to the service connector through a control path.
3. The router of claim 2, wherein the number of the service boards is 2 or 3, all the service connectors are communicatively connected to each other through a data path, and all the master connectors and all the service connectors are communicatively connected to each other through a control path.
4. The router of claim 1, wherein the master CPU module comprises a master fly-away processor communicatively coupled to the master connector, and wherein the master fly-away processor is communicatively coupled to the SSD, the first DRAM memory, the first BIOS chip, the serial port, the management port, and the USB port, respectively.
5. The router of claim 4, wherein the first master programmable device module comprises a master FPGA chip communicatively coupled to a master connector and a master Feiteng processor.
6. The router of claim 5, wherein the second master programmable device module comprises a master EPLD chip communicatively coupled to the master connector, the master fly processor, and the master FPGA chip, respectively, the master EPLD chip communicatively coupled to the master power circuit, the master synchronizing clock circuit, the reset button, and the master LED indicator light, respectively.
7. The router of any of claims 1-6, wherein the traffic CPU module comprises a traffic flyover processor communicatively coupled to the traffic connector, the traffic flyover processor communicatively coupled to the second DRAM memory and the second BIOS chip, respectively.
8. The router of claim 7, wherein the first service programmable device module comprises a service FPGA chip communicatively coupled to a service connector and a service Feiteng processor, the service FPGA chip communicatively coupled to a third DRAM memory and a TCAM memory, respectively.
9. The router of claim 8, wherein the second service programmable device module comprises a service EPLD chip communicatively coupled to the service connector, the service flyover processor, and the service FPGA chip, respectively, the service EPLD chip communicatively coupled to the service power circuit, the service synchronization clock circuit, and the service LED indicator light, respectively.
10. The router of claim 9, further comprising an expansion interface module communicatively coupled to the service FPGA chip and the service EPLD chip, respectively.
Priority Applications (1)
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CN202020532624.9U CN211509069U (en) | 2020-04-10 | 2020-04-10 | Router |
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CN202020532624.9U CN211509069U (en) | 2020-04-10 | 2020-04-10 | Router |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114116588A (en) * | 2021-12-01 | 2022-03-01 | 湖南戎腾网络科技有限公司 | ATCA board card |
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2020
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114116588A (en) * | 2021-12-01 | 2022-03-01 | 湖南戎腾网络科技有限公司 | ATCA board card |
CN114116588B (en) * | 2021-12-01 | 2024-02-13 | 湖南戎腾网络科技有限公司 | ATCA board card |
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