CN211236890U - Detection apparatus for stack overflow and electronic equipment - Google Patents
Detection apparatus for stack overflow and electronic equipment Download PDFInfo
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Abstract
The utility model provides a detection device and electronic equipment that stack spilled over. The device, comprising: the device comprises a memory protection unit, a stack register and a stack boundary configuration register; wherein: the memory protection unit is in communication connection with the stack boundary configuration register and is used for acquiring stack boundary information from the stack boundary configuration register; the memory protection unit is in communication connection with the stack register and is used for acquiring a stack top address from the stack register; and the memory protection unit is further used for judging whether stack overflow occurs according to the stack boundary information and the stack top address. Therefore, the stack out overflow abnormity can be timely and accurately judged under the condition of not modifying the kernel.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a stack overflow detection apparatus and an electronic device.
Background
Stack overflow, whether with or without an operating system, is one of the important causes of system instability, and therefore it is necessary to detect in a timely manner whether a stack overflow condition exists.
At present, two types of methods for detecting stack overflow are available, 1) judging whether the value of a stack register exceeds a preset address boundary; 2) the stack space is initialized by a special value, and whether the out-of-range event exists is judged by judging whether the initial value of the stack boundary changes.
However, the foregoing method requires that the central processing unit can detect the value of the stack register in real time during running, and when the central processing unit is in an Operating System (OS) scenario, because the value of the stack register may be any value, it is not possible to accurately determine whether stack overflow occurs. When the OS is not in the OS scene, it is impossible to determine whether stack overflow occurs in real time.
SUMMERY OF THE UTILITY MODEL
The utility model provides a fingerprint identification device and electronic equipment can in time accurately judge that the pop-up overflows unusually under the condition of not modifying the kernel.
In a first aspect, an embodiment of the present invention provides a method for detecting stack overflow; the method comprises the following steps:
determining whether the current access memory address is an illegal access event or not according to stack boundary information in a stack boundary configuration register;
if the current access memory address meets the preset condition, judging whether the current access memory address meets the preset condition; wherein the preset conditions include: the current access memory address is positioned between the stack top address and the stack bottom address indicated by the stack register;
and if the preset condition is met, determining that the stack overflows.
In one possible design, further comprising:
sending a trigger signal to an interrupt controller;
and interrupting the memory access of the central processing unit according to the trigger signal.
In one possible design, further comprising:
stack boundary information in a stack boundary configuration register is set.
In one possible design, the setting stack boundary information in the stack boundary configuration register includes:
writing the stack boundary information in the stack boundary configuration register through a central processing unit; wherein the stack boundary information includes: the starting address of the stack boundary, the ending address of the stack boundary and the stack bottom address; the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
In one possible design, determining whether a current access memory address is an illegal access event according to stack boundary information in a stack boundary configuration register includes:
and if the current access memory address is positioned between the initial address of the stack boundary and the end address of the stack boundary, determining that the current access address is an illegal access event.
In one possible design, further comprising:
and when the current access memory address is between the stack top address and the stack bottom address indicated by the stack register, setting the state of the stack overflow state register as an overflow state.
In one possible design, further comprising:
and storing the corresponding context information in an overflow state through the stack overflow state register.
In a second aspect, an embodiment of the present application provides an apparatus for detecting stack overflow, including:
the device comprises a memory protection unit, a stack register and a stack boundary configuration register; wherein:
the memory protection unit is in communication connection with the stack boundary configuration register and is used for acquiring stack boundary information from the stack boundary configuration register;
the memory protection unit is in communication connection with the stack register and is used for acquiring a stack top address from the stack register;
and the memory protection unit is further used for judging whether stack overflow occurs according to the stack boundary information and the stack top address.
In one possible design, the memory protection unit is specifically configured to:
determining whether the current access address of the central processing unit is an illegal access event or not according to the stack boundary information;
if the current access address is an illegal access event, judging whether the current access address is between a stack top address and a stack bottom address indicated by a stack register;
and if the current access address is between the stack top address and the stack bottom address indicated by the stack register, determining that the stack is overflowed.
In one possible design, further comprising: the interrupt controller is in communication connection with the memory protection unit;
the memory protection unit is further configured to: sending a trigger signal to an interrupt controller;
and the interrupt controller is used for interrupting the memory access of the central processing unit according to the trigger signal.
In one possible design, the memory protection unit obtains the stack top address from the stack register through a stack register access port exposed by a central processing unit; or, the stack top address is acquired from the stack register through a debugging port.
In one possible design, the stack boundary configuration register is to store stack boundary information; the stack boundary information includes: the starting address of the stack boundary, the ending address of the stack boundary and the stack bottom address; the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
In one possible design, the stack boundary configuration register is communicatively coupled to a central processor, which writes the stack boundary information to the stack boundary configuration register.
In one possible design, the illegal access event refers to a current access memory address being located between a start address of the stack boundary and an end address of the stack boundary.
In one possible design, further comprising: a stack overflow status register in communication connection with the memory protection unit;
the memory protection unit is further configured to set the state of the stack overflow status register to an overflow state when the current access memory address is between the stack top address and the stack bottom address indicated by the stack register.
In one possible design, the stack overflow status register is used to store corresponding context information in an overflow state.
In a third aspect, an embodiment of the present application provides an electronic device, including the apparatus for detecting stack overflow described in any one of the second aspects.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory; the memory stores an algorithm program, and the processor is configured to call the algorithm program in the memory and execute the stack overflow detection method according to any one of the first aspect.
In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, including: program instructions which, when run on a computer, cause the computer to execute the program instructions to implement the method of stack overflow detection as claimed in any one of the first aspects.
The utility model provides a detection device and electronic equipment that stack overflows through setting up stack register and stack boundary configuration register with memory protection unit communication connection for memory protection unit can follow stack boundary information is acquireed to stack boundary configuration register; acquiring a stack top address from the stack register; and judging whether stack overflow occurs or not according to the stack boundary information and the stack top address. The utility model discloses the detection of having used multipurposely memory access authority and stack scope determines the condition that the stack spilled over whether appear to can in time accurately judge whether there is the stack to spill over on the basis that does not change the kernel, reduce the erroneous judgement condition.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive exercise.
FIG. 1 is a schematic diagram of an application scenario of the present application;
FIG. 2 is a schematic diagram illustrating a comparison of address spaces of an illegal access event caused by a stack overflow and a normal illegal access event provided in the present application;
fig. 3 is a flowchart of a stack overflow detection method according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a stack overflow detection apparatus according to a second embodiment of the present application;
fig. 5 is a schematic structural diagram of a stack overflow detection apparatus according to a third embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application.
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate concepts presented by the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings in the embodiments of the present invention are combined below to clearly and completely describe the technical solutions in the embodiments of the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail with reference to the following specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Taking a system with an operating system as an example, during the running process of the operating system, stack overflow is an important cause of system instability, and therefore, whether stack overflow exists needs to be detected in time. The method for detecting stack overflow mainly comprises two types, 1) judging whether the value of a stack register exceeds a preset address boundary; 2) the stack space is initialized by a special value, and whether the out-of-range event exists is judged by judging whether the initial value of the stack boundary changes.
However, the above method requires that the central processing unit can detect the value of the stack register in real time during running, and when the stack register is in an OS scene, the value of the stack register can be any value, so that the real-time performance and accuracy of detection cannot be guaranteed, and a situation of stack overflow misjudgment occurs.
In view of the above technical problems, the present application provides a method and an apparatus for detecting stack overflow, an electronic device, and a storage medium, which comprehensively utilize memory access rights and stack range detection to determine whether stack overflow occurs, so that whether stack overflow occurs can be timely and accurately determined without changing a kernel, and misdetermination conditions are reduced. The kernel in the present application may be a core arithmetic Unit in a product such as a Microcontroller Unit (MCU), a Central Processing Unit (CPU), and the like, and is used to complete operations such as calculation, receiving/storing commands, data Processing, and the like.
Fig. 1 is a schematic diagram illustrating an application scenario of the present application, and as shown in fig. 1, when an internal core accesses a stack, a current access address is obtained, and stack boundary information is obtained from a stack boundary configuration register. The stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed. And if the current access address is in the memory space range corresponding to the stack boundary, namely the kernel accesses the protected memory space, determining that the current access address is illegal. And then further judging that the current access memory address is between the stack top address and the stack bottom address indicated by the stack register. If the current access memory address is between the stack top address and the stack bottom address indicated by the stack register, stack overflow is determined to occur, at this time, the state of the stack overflow state register can be set to be an overflow state, context information corresponding to the overflow state is stored through the stack overflow state register, and finally, a trigger signal is sent to the interrupt controller, so that the memory access of the central processing unit is interrupted. If the current access memory address is not between the stack top address and the stack bottom address indicated by the stack register, the current access memory address can be determined as a common memory illegal access flow, and the processing can be performed according to the common memory illegal access, so that stack overflow is not involved.
In this embodiment, whether the access to the memory address is an illegal access or not may be implemented by the memory protection unit. If the protected area is not accessed, the internal core can continuously access the internal memory information for legal access. The method for obtaining the stack top address may be that the memory protection unit obtains the stack top address from the stack register through a stack register access port exposed by the central processing unit, or obtains the stack top address from the stack register through a debug port.
It should be noted that the method provided by this embodiment is suitable for MCU/CPU products that need to support stack overflow detection. The number of stack boundary information in the stack boundary configuration register may be plural. For a scene with a plurality of stacks, a plurality of stack boundary addresses can be set, the number of stack bottom addresses is only 1, and the stack bottom addresses need to be dynamically set during each stack switching. In the context of an OS, the value at the bottom of the stack may be dynamically set into the stack boundary configuration register upon kernel task switching.
In this embodiment, a stack boundary is set as a protection address based on a memory protection unit by using memory access right control and stack range check. When the memory is illegally accessed, pausing the kernel access, and judging whether an illegally accessed memory address is between the stack register value and the current stack bottom; if yes, an interrupt trigger signal is sent to the interrupt controller, and meanwhile, a stack overflow status register is set. Therefore, whether stack overflow exists can be accurately judged in time on the basis of not changing the kernel, and misjudgment conditions are reduced.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 2 is a schematic diagram illustrating a comparison of address spaces of an ordinary illegal access event and an illegal access event caused by stack overflow according to the present application. In the prior art, whether stack overflow occurs is generally determined by judging whether a current access address of a CPU is a memory space corresponding to a stack boundary. However, the memory space corresponding to the stack access boundary of the CPU is not necessarily caused by stack overflow, and therefore, the stack overflow misjudgment may occur.
Aiming at the problems in the prior art, the method comprises the steps that a starting address and an ending address of a memory space corresponding to a stack boundary are written into a stack boundary configuration register through a CPU in advance; and the memory space corresponding to the stack boundary is positioned at the end position of the stack memory. And then determining whether the current access memory address is located in the memory space corresponding to the stack boundary or not according to stack boundary information (including the stack boundary starting address and the stack boundary ending address) in the stack boundary configuration register, and determining that the current access memory address is an illegal access event if the current access memory address is located in the memory space corresponding to the stack boundary. Further, whether the current access memory address is located between the stack top address and the stack bottom address of the stack register is judged, and if the current access memory address is located between the stack top address and the stack bottom address of the stack register, an illegal access event caused by stack overflow is determined. Therefore, the detection of the memory access authority and the stack range is comprehensively utilized to judge whether the stack overflow occurs, so that whether the stack overflow occurs is accurately judged in time on the basis of not changing the kernel, and the misjudgment condition is reduced.
Fig. 3 is a flowchart of a stack overflow detection method provided in an embodiment of the present application, and as shown in fig. 3, the method in the embodiment may include:
s101, determining whether the current access memory address is an illegal access event or not according to stack boundary information in the stack boundary configuration register.
The method provided by the embodiment is suitable for Micro Control Unit (MCU) and Central Processing Unit (CPU) products which need to support stack overflow detection. In this embodiment, a CPU is taken as an example for explanation. When the CPU accesses the stack, the current access address can be obtained through the memory protection unit, and the stack boundary information is obtained from the stack boundary configuration register. A Memory Protection Unit (MPU) is one of hardware for effectively protecting system resources equipped in an ARM, and provides a memory area protection function. The stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed. And if the current access address is in the stack boundary, namely the CPU accesses the protected memory space, determining that the current access address is illegal. If the protected memory space is not accessed, the access is legal, and the CPU can be continuously allowed to access the memory information.
In this embodiment, the stack boundary information may be stored in the stack boundary configuration register. The stack boundary information comprises a start address of a stack boundary, an end address of the stack boundary and a stack bottom address; and the bottom address of the stack and the end address of the stack boundary are used to define the range of the stack memory.
Illustratively, the CPU is communicatively coupled to the stack boundary configuration register. Therefore, the stack boundary can be set by the CPU, and the stack boundary information is stored in the stack boundary configuration register.
It should be noted that the number of stack boundary information in the stack boundary configuration register may be multiple. For a scenario with multiple stacks, the start addresses of multiple stack boundaries and the corresponding end addresses of the stack boundaries may be set, but the stack bottom addresses are only 1. Therefore, it is necessary to dynamically set the bottom address every time the stack is switched. In the context of an OS, the value at the bottom of the stack may be dynamically set into the stack boundary configuration register upon kernel task switching.
S102, if the access event is an illegal access event, judging whether the current access memory address meets a preset condition or not.
In this embodiment, when the memory protection unit determines that the current access memory address is an illegal access event, it further determines whether the current access memory address is located between the stack top address and the stack bottom address indicated by the stack register. The obtaining mode of the stack top address may be that the memory protection unit obtains the stack top address from the stack register through a stack register access port exposed by the central processing unit, or obtains the stack top address from the stack register through a debugging port. And if the current access memory address is between the stack top address and the stack bottom address indicated by the stack register, determining that the stack overflows. If the current access memory address is not between the stack top address and the stack bottom address indicated by the stack register, the current access memory address can be determined as a common memory illegal access flow, and the processing can be performed according to the common memory illegal access, so that stack overflow is not involved.
S103, if the preset condition is met, determining that the stack overflows.
In this embodiment, if the current access memory address is located between the stack top address and the stack bottom address indicated by the stack register, the state of the stack overflow status register is set to be an overflow state by the memory protection unit. The stack overflow status register may be configured to store context information corresponding to an overflow status.
In this embodiment, after it is determined that stack overflow occurs, the state of the stack overflow status register is set to be an overflow state, and context information in the overflow state is stored to store field information of stack overflow, and the field information can be called by the CPU, so that the CPU can conveniently perform program debugging.
After step S101 to step S103 are executed, a trigger signal may be sent to the interrupt controller through the memory protection unit, so that the interrupt controller interrupts the memory access of the central processing unit according to the trigger signal.
In this embodiment, if the preset condition is satisfied, the memory protection unit sends a trigger signal to the interrupt controller. For example, a Non-Maskable Interrupt request such as NMI (Non Maskable Interrupt) may be sent to the Interrupt controller.
In this embodiment, after the interrupt controller receives the trigger signal from the memory protection unit, the memory access of the CPU may be interrupted.
In this embodiment, whether a current access memory address is an illegal access event is determined according to stack boundary information in a stack boundary configuration register; if the access event is an illegal access event, judging whether the current access memory address meets a preset condition; wherein the preset conditions include: the current access memory address is positioned between the stack top address and the stack bottom address indicated by the stack register; and if the preset condition is met, determining that the stack overflows. The method and the device comprehensively utilize the detection of the memory access authority and the stack range to judge whether the stack overflow occurs, so that whether the stack overflow occurs can be accurately judged in time on the basis of not changing the kernel, and the misjudgment condition is reduced.
Fig. 4 is a schematic structural diagram of a stack overflow detection apparatus provided in the second embodiment of the present application, and as shown in fig. 4, the stack overflow detection apparatus in this embodiment may include: a memory protection unit 31, a stack register 33, and a stack boundary configuration register 34;
the memory protection unit 31 is communicatively connected to the stack boundary configuration register 34, and is configured to obtain stack boundary information from the stack boundary configuration register 34;
the memory protection unit 31 is communicatively connected to the stack register 33, and is configured to obtain a stack top address from the stack register 33;
the memory protection unit 31 is further configured to determine whether stack overflow occurs according to the stack boundary information and the stack top address.
Optionally, the memory protection unit 31 is specifically configured to:
determining whether the current access address of the central processing unit is an illegal access event or not according to the stack boundary information;
if the access event is an illegal access event, judging whether the current access address is between the stack top address and the stack bottom address indicated by the stack register;
if the current access address is between the top and bottom stack addresses indicated by the stack register 33, a stack overflow is determined.
Optionally, the memory protection unit 31 is in communication connection with an interrupt controller 32; when stack overflow is determined, the memory protection unit 31 sends a trigger signal to the interrupt controller 32;
and the interrupt controller 32 is used for interrupting the memory access of the central processing unit according to the trigger signal.
In the embodiment, the method is suitable for MCU/CPU products needing to support stack overflow detection. A Memory Protection Unit (MPU) is one of hardware for effectively protecting system resources equipped in an ARM, and provides a memory area protection function.
In one possible design, the memory protection unit 31 obtains the top address of the stack from the stack register 33 through the exposed stack register access port of the central processing unit; alternatively, the top-of-stack address is retrieved from the stack register 33 through the debug port.
In one possible design, further comprising: a stack boundary configuration register 34 communicatively coupled to the memory protection unit, the stack boundary configuration register 34 for storing stack boundary information.
In one possible design, the central processor is communicatively coupled to the stack boundary configuration register 34 for writing stack boundary information to the stack boundary configuration register 34; the stack boundary information includes: the starting address of the stack boundary, the ending address of the stack boundary and the stack bottom address; the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
In a possible design, the memory protection unit 31 is further configured to determine whether the currently accessed memory address is an illegal access event according to the stack boundary information in the stack boundary configuration register. The stack boundary refers to a protected memory space preset in the memory, and the memory space is not allowed to be accessed.
In one possible design, an illegal access event refers to a current access memory address being between the start address of the stack boundary and the end address of the stack boundary.
The device for detecting stack overflow in this embodiment may execute the technical solution in the method shown in fig. 3, and for the specific implementation process and technical principle, reference is made to the relevant description in the method shown in fig. 3, which is not described herein again.
In this embodiment, whether a current access memory address is an illegal access event is determined according to stack boundary information in a stack boundary configuration register; if the access event is an illegal access event, judging whether the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the stack overflow is between the top address and the bottom address indicated by the stack register, the stack overflow is determined. The method and the device comprehensively utilize the detection of the memory access authority and the stack range to judge whether the stack overflow occurs, so that whether the stack overflow occurs can be accurately judged in time on the basis of not changing the kernel, and the misjudgment condition is reduced.
Fig. 5 is a schematic structural diagram of a stack overflow detection apparatus provided in the third embodiment of the present application, and as shown in fig. 5, the stack overflow detection apparatus of the present embodiment may further include, on the basis of fig. 4: a stack overflow status register 35 communicatively coupled to the memory protection unit 31;
the memory protection unit 31 is further configured to set the state of the stack overflow status register 35 to an overflow state when the current access memory address is between the stack top address and the stack bottom address indicated by the stack register.
In one possible design, a stack overflow status register 35 is used to store the corresponding context information in an overflow state.
The device for detecting stack overflow in this embodiment may execute the technical solution in the method shown in fig. 3, and for the specific implementation process and technical principle, reference is made to the relevant description in the method shown in fig. 3, which is not described herein again.
In this embodiment, whether a current access memory address is an illegal access event is determined according to stack boundary information in a stack boundary configuration register; if the access event is an illegal access event, judging whether the current access memory address is between the stack top address and the stack bottom address indicated by the stack register; if the stack overflow is between the top address and the bottom address indicated by the stack register, the stack overflow is determined. The method and the device comprehensively utilize the detection of the memory access authority and the stack range to judge whether the stack overflow occurs, so that whether the stack overflow occurs can be accurately judged in time on the basis of not changing the kernel, and the misjudgment condition is reduced.
Fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application, and as shown in fig. 6, the electronic device 40 according to the present embodiment may include: a processor 41 and a memory 42.
A memory 42 for storing programs; the Memory 42 may include a volatile Memory (RAM), such as a Random Access Memory (SRAM), a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), and the like; the memory may also comprise a non-volatile memory, such as a flash memory. The memory 42 is used to store computer programs (e.g., applications, functional modules, etc. that implement the above-described methods), computer instructions, etc., which may be stored in one or more of the memories 42 in a partitioned manner. And the above-mentioned computer program, computer instructions, data, etc. can be called by the processor 41.
The computer programs, computer instructions, etc. described above may be stored in one or more memories 42 in partitions. And the above-mentioned computer program, computer instructions, data, etc. can be called by the processor 41.
A processor 41 for executing the computer program stored in the memory 42 to implement the steps of the method according to the above embodiments.
Reference may be made in particular to the description relating to the preceding method embodiment.
The processor 41 and the memory 42 may be separate structures or may be integrated structures integrated together. When the processor 41 and the memory 42 are separate structures, the memory 42 and the processor 41 may be coupled by a bus 43.
The electronic device of this embodiment may execute the technical solution in the method shown in fig. 3, and for the specific implementation process and the technical principle, reference is made to the relevant description in the method shown in fig. 3, which is not described herein again.
In this embodiment, whether a current access memory address is an illegal access event is determined according to stack boundary information in a stack boundary configuration register; if the access event is an illegal access event, judging whether the current access memory address meets a preset condition; wherein the preset conditions include: the current access memory address is positioned between the stack top address and the stack bottom address indicated by the stack register; and if the preset condition is met, determining that the stack overflows. The method and the device comprehensively utilize the detection of the memory access authority and the stack range to judge whether the stack overflow occurs, so that whether the stack overflow occurs can be accurately judged in time on the basis of not changing the kernel, and the misjudgment condition is reduced.
In addition, embodiments of the present application further provide a computer-readable storage medium, in which computer-executable instructions are stored, and when at least one processor of the user equipment executes the computer-executable instructions, the user equipment performs the above-mentioned various possible methods.
Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In addition, the application specific integrated circuit may be located in the user equipment. Of course, the processor and the storage medium may reside as discrete components in a communication device.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as Read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and so on.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. An apparatus for detecting stack overflow, comprising: the device comprises a memory protection unit, a stack register and a stack boundary configuration register; wherein:
the memory protection unit is in communication connection with the stack boundary configuration register and is used for acquiring stack boundary information from the stack boundary configuration register;
the memory protection unit is in communication connection with the stack register and is used for acquiring a stack top address from the stack register;
and the memory protection unit is further used for judging whether stack overflow occurs according to the stack boundary information and the stack top address.
2. The apparatus of claim 1, wherein the memory protection unit is specifically configured to:
determining whether the current access address of the central processing unit is an illegal access event or not according to the stack boundary information;
if the current access address is an illegal access event, judging whether the current access address is between a stack top address and a stack bottom address indicated by a stack register;
and if the current access address is between the stack top address and the stack bottom address indicated by the stack register, determining that the stack is overflowed.
3. The apparatus of claim 1, further comprising: the interrupt controller is in communication connection with the memory protection unit;
the memory protection unit is further configured to: sending a trigger signal to an interrupt controller;
and the interrupt controller is used for interrupting the memory access of the central processing unit according to the trigger signal.
4. The apparatus of claim 1, wherein the memory protection unit obtains the top address from the stack register through a stack register access port exposed by a central processing unit; or, the stack top address is acquired from the stack register through a debugging port.
5. The apparatus of claim 2, wherein the stack boundary configuration register is to store stack boundary information; the stack boundary information includes: the starting address of the stack boundary, the ending address of the stack boundary and the stack bottom address; the stack bottom address and the end address of the stack boundary are used to define the range of the stack memory.
6. The apparatus of claim 5, wherein the stack boundary configuration register is communicatively coupled to a central processing unit, the central processing unit writing the stack boundary information to the stack boundary configuration register.
7. The apparatus of claim 5, wherein the illegal access event is that a currently accessed memory address is located between a start address of the stack boundary and an end address of the stack boundary.
8. The apparatus of any one of claims 1-7, further comprising: a stack overflow status register in communication connection with the memory protection unit;
the memory protection unit is further configured to set the state of the stack overflow status register to an overflow state when the current access memory address is between the stack top address and the stack bottom address indicated by the stack register.
9. The apparatus of claim 8, wherein the stack overflow status register is configured to store corresponding context information in an overflow state.
10. An electronic device, comprising: the apparatus for detection of stack overflow of any one of claims 1-9.
Priority Applications (1)
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