CN210721442U - Master-slave system with master device and slave device capable of being replaced in self-adaptive mode - Google Patents

Master-slave system with master device and slave device capable of being replaced in self-adaptive mode Download PDF

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Publication number
CN210721442U
CN210721442U CN201921529429.4U CN201921529429U CN210721442U CN 210721442 U CN210721442 U CN 210721442U CN 201921529429 U CN201921529429 U CN 201921529429U CN 210721442 U CN210721442 U CN 210721442U
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master
slave
master device
masters
devices
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郎宁
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Daochong Electronic Technology Zhejiang Co ltd
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Daochong Electronic Technology Jiaxing Co ltd
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Abstract

The utility model provides a master-slave system that master device and slave device can self-adaptation be replaced belongs to electron technical field. The method solves the problems of poor redundancy and robustness of the master-slave system in the prior art. The master-slave system comprises at least two masters used as master/slave devices, a plurality of non-masters only used as slave devices and a bus network, wherein each master device and each non-master device are connected with the bus network, each master device determines and selects one master device as a master device of the whole system through sequential, designated or random selection, and other master devices except the master device are temporarily used as slave devices until problems occur to the master device. The system has simple structure and low cost, and can effectively improve the redundancy and the robustness of the master-slave system.

Description

Master-slave system with master device and slave device capable of being replaced in self-adaptive mode
Technical Field
The utility model belongs to the technical field of electron, a master slaver system that master device and slave device can self-adaptation be replaced is related to.
Background
Conventional master-slave circuit topologies are widely used. As shown in fig. 1, the master-slave topology refers to that in an electronic product system composed of N devices (N > ═ 2), there are one master device and N-1 slave devices, and the master device is responsible for overall control of the whole system and interaction between the master device and the slave devices.
At present, most master-slave circuits adopt the master-slave topological mechanism, and the master-slave topological mechanism is characterized in that: the interaction between the system and the outside is only completed by the main device; in the system, the slave device cannot actively initiate interaction, and only passively waits for the master device to send an interaction command and then gives a response, so that the slave device and the slave device cannot interact with each other. The interaction of the entire system with the outside world is also typically, but not necessarily, accomplished through the master device. The system architecture has the advantages of being concise, simple both internally and externally (only the master device needs to be considered to realize the management of the whole system), easy to master and use, and low in comprehensive cost (the master device has higher cost than the slave devices, and the more the master devices are used, the higher the system cost is). A system built using the I2C bus is a typical master-slave circuit topology.
However, the biggest disadvantage of the conventional master-slave circuit topology is that the system depends heavily on the master device, once the master device works abnormally, the whole system is also broken down, and the redundancy and the robustness of the whole system are very weak.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention is to provide a master-slave system with a master device and a slave device capable of being adaptively replaced, so as to solve the deficiencies of the prior art.
The purpose of the utility model can be realized by the following technical proposal: a master-slave system capable of adaptively replacing a master device and a slave device is characterized by comprising at least two masters used as master devices/slave devices, a plurality of non-masters only used as slave devices and a bus network, wherein each master device and each non-master device are connected with the bus network, each master device determines to select one master device as a master device of the whole system through sequential, designated or random selection, and other masters except the master device temporarily serve as slave devices until problems occur to the master device.
Master device capable of adaptively replacing master device and slave deviceIn the slave system, the corresponding sorting numbering is carried out on each of the masters as follows: m1-MxX is not less than 2; and performing corresponding sequencing numbering on each unownable device as follows: n is a radical of1-Nx,N≥2。
In the master-slave system with the master device and the slave device capable of being adaptively replaced, a clock circuit for generating a clock signal, a data memory for presetting data information and an interrupt signal generator for inputting an interrupt signal of 'election master device' are also connected to the bus network.
In the master-slave system in which the master device and the slave device can be adaptively replaced, the interrupt signal generator is forced to start generating an interrupt signal of 'electing the master device' when the problem occurs in the master device serving as the master device.
In the master-slave system with the master device and the slave device capable of being adaptively replaced, each masterable device and each non-masterable device temporarily used as the slave device can generate own identification codes, the masterable device used as the master device starts an interactive instruction, then each identification code is reported one by one, and the corresponding masterable device and each non-masterable device temporarily used as the slave device respond one by one to interact.
Compared with the prior art, the master-slave system with the master device and the slave device capable of being adaptively replaced has the following advantages: the advantages of simple inside and outside of the conventional master-slave circuit topological structure are maintained, the redundancy of the whole system is effectively improved, and the robustness of the system is improved. The redundancy of a system is proportional to the number of masters in the system.
Drawings
Fig. 1 is a schematic diagram of a master-slave system in the prior art.
Fig. 2 is a schematic diagram of a master-slave system in which a master device and a slave device can be adaptively replaced in the embodiment.
Fig. 3 is a system state diagram when a masterable device, which is the master device in the embodiment, fails.
FIG. 4 is a flow chart of the operation of the master-slave system in which the master device and the slave device can be adaptively replaced in the embodiment.
Detailed Description
The following are specific embodiments of the present invention and the accompanying drawings are used to further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.
As shown in fig. 2 and fig. 3, the master-slave system for adaptively replacing the master device and the slave device comprises at least two masters serving as master devices/slave devices, a plurality of non-masters serving as slave devices only, and a bus network, wherein each master device and each non-master device are connected with the bus network, and the bus network is further connected with a clock circuit for generating a clock signal, a data memory for presetting credit-data information, and an interrupt signal generator for inputting an interrupt signal of a "electing master device". The interrupt signal generator is forced to start generating an interrupt signal of 'election master' when the masterable device as the master goes wrong. The respective order numbering is performed on each masterable device as: m1-MxX is not less than 2; and performing corresponding sequencing numbering on each unownable device as follows: n is a radical of1-Ny,y≥2。
Each masterable device and each non-masterable device which temporarily serve as a slave device can generate own identification codes, the masterable device serving as the master device starts an interactive instruction, then each identification code is reported one by one, and the corresponding masterable device and each non-masterable device which temporarily serve as the slave device respond one by one to interact.
As shown in fig. 4, the operation process of the system includes initialization, device identification, operation, master failure judgment and adaptive replacement of the master.
In an actual system configuration, each of the masters determines to select one of them as a master of the entire system by sequential, assigned, or random selection, and the masters other than the master temporarily become slave devices until the master becomes defective. Specifically, the method comprises the following steps:
(1) selecting the master device in sequence, namely selecting the master device in sequence or in a reverse sequence and other modes according to the numbering sequence;
(2) the designation means that a certain device is designated as a master device in advance by some artificial means. The method for implementing the assignment method is many and can be divided into a hardware method and a software method:
an example of an implementation of the hardware approach is to force an input pin of the target master device to a particular state, such as high, and the corresponding pins of the other devices to low, or vice versa. The limitation of the use of the hardware approach is the requirement that the device must be configured with such a pin, and the device does not necessarily have such a pin.
One example of an implementation of a software method is to set a certain memory location of a target master device to a certain value and the corresponding memory locations of other devices to other values. The use limit of the software method is lower than that of the hardware method, and the software method can be satisfied generally. Another example of an implementation of the software approach is to write the target master device into the execution code with the master device functionality and the other devices into the general execution code.
(3) The random method is characterized in that human intervention is not needed, a system automatically generates a main device, the method has the advantages of fully automatic realization process and more time.
One implementation of the stochastic method is as follows: assuming that M masters in the system are connected through a group of buses at least containing clock information and data information and simultaneously connected with an interrupt signal of an 'election master', when the whole system is powered on for initialization processing for the first time, the system provides the interrupt signal as a total synchronous signal of all the devices, each device independently generates a random number once receiving the interrupt signal, and if the random numbers generated by one or more devices are a specific value (0, or the maximum value, or any other specified value), the candidate master is considered to be found; if the random numbers of all devices are not the specific value, the interrupt cycle is ended, and a new cycle is started until the candidate master device appears.
The random approach may result in collisions, i.e., multiple candidate masters may be present simultaneously within a certain period. There are many ways to resolve such conflicts, and one example of implementation is: and adopting a second step random method to enable all devices entering the candidate list to generate random numbers again until the specified value is obtained.
It should be noted that the software method designation and the random method selection are common selection methods in the art, and therefore, redundant description is not repeated.
After the master device is selected, the master device must take over control of the entire system and identify other devices in the system. While each device may be numbered artificially as well, other devices may be identified and numbered by the master device.
There are many methods for identifying the master device and the slave device, and the embodiment briefly introduces one of the following methods: the master device and the slave device can simultaneously generate random numbers, the master device sends out a handshake signal as the device number according to the sequence of natural numbers, and when the random numbers of the master device and the slave device are the same as the device number, the device responds to complete handshake. The master device makes a registration and the slave device creates its own identification number. If there is a concern about collisions, a multi-step random approach may also be employed.
The device identification numbers of the non-master-slave devices are generally predetermined and not configurable, but can be identified by the method described above.
The interaction process of the master device and the slave device comprises the following steps:
the master device starts an interactive instruction, then reports the identification codes of the slave devices one by one, and the corresponding slave devices respond one by one. There are types of interaction that are applicable in systems with multiple masters and only with masters.
When the master device is abnormal, the master device and the slave device can be replaced by the master device, and the two methods are also provided: a random method and a weighted method.
When the system judges that the main device is abnormal, the random method forcibly starts the main device election interrupt signal, each device enters the main device election flow again, and the original main device automatically exits election due to failure.
Weight method: because the system has completed initialization and the devices have been numbered, a new master device can be designated in the natural order of numbering from small to large or from large to small. An example of one implementation is: after the original master device fails, the system automatically generates a master device election interrupt signal, and when the interrupt frequency is the same as the serial number of a certain device, the device is called as the master device. Because the devices are numbered, the new master device need only identify the original numbers one by one, or read the information (if readable) from the original master device, in a natural sequential manner.
The above-described method of replacing the master device is also common in the art and therefore need not be elaborated upon.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications, additions and substitutions for the specific embodiments described herein may be made by those skilled in the art without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.

Claims (5)

1. A master-slave system capable of adaptively replacing a master device and a slave device is characterized by comprising at least two masters used as master devices/slave devices, a plurality of non-masters only used as slave devices and a bus network, wherein each master device and each non-master device are connected with the bus network, each master device determines to select one master device as a master device of the whole system through sequential, designated or random selection, and other masters except the master device temporarily serve as slave devices until problems occur to the master device.
2. The master-slave system of claim 1, wherein the master device and the slave device are adaptively replaced, and the respective sequence numbers are performed on each of the masters: m1-MxX is not less than 2; and performing corresponding sequencing numbering on each unownable device as follows: n is a radical of1-Nx,N≥2。
3. A master-slave system according to claim 1 or 2, wherein a clock circuit for generating a clock signal, a data memory for storing information and data, and an interrupt signal generator for inputting an interrupt signal of an "electing master" are connected to the bus network.
4. A master-slave system for adaptively replacing a master device and a slave device according to claim 3, wherein the interrupt signal generator is configured to force an interrupt signal for "electing the master device" when a problem occurs in the master device.
5. The master-slave system according to claim 1 or 2, wherein each of the masters and slaves temporarily serving as slaves is capable of generating its own identification code, each of the masters and the slaves being capable of initiating an interaction command as a master, and then reporting each identification code one by one, and each of the masters and the slaves being capable of responding one by one to perform interaction.
CN201921529429.4U 2019-09-16 2019-09-16 Master-slave system with master device and slave device capable of being replaced in self-adaptive mode Active CN210721442U (en)

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CN201921529429.4U CN210721442U (en) 2019-09-16 2019-09-16 Master-slave system with master device and slave device capable of being replaced in self-adaptive mode

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CN210721442U true CN210721442U (en) 2020-06-09

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Denomination of utility model: A master-slave system with adaptive replacement of master and slave devices

Effective date of registration: 20210713

Granted publication date: 20200609

Pledgee: Agricultural Bank of China Limited by Share Ltd. South Lake branch

Pledgor: DAOCHONG ELECTRONIC TECHNOLOGY (JIAXING) Co.,Ltd.

Registration number: Y2021330000843

CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: 314001 rooms 303, 305 and 306, building 13, phase III, Chinese Academy of Sciences, No. 906, Asia Pacific Road, Daqiao Town, Nanhu District, Jiaxing City, Zhejiang Province

Patentee after: Daochong Electronic Technology (Zhejiang) Co.,Ltd.

Address before: 314006 room 508-1, building 16, No. 906, Asia Pacific Road, Nanhu District, Jiaxing City, Zhejiang Province (phase III of Chinese Academy of Sciences)

Patentee before: DAOCHONG ELECTRONIC TECHNOLOGY (JIAXING) Co.,Ltd.