CN209929300U

CN209929300U - Package structure

Info

Publication number: CN209929300U
Application number: CN201920840615.3U
Authority: CN
Inventors: 冷寒剑; 吴宝全; 龙卫
Original assignee: Shenzhen Huiding Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2019-06-03
Filing date: 2019-06-03
Publication date: 2020-01-10
Anticipated expiration: 2029-06-03

Abstract

The present application provides a packaging structure. The package structure provided by the present application includes: a package substrate and a redistribution layer disposed on the package substrate, wherein the package substrate includes: a plurality of device regions, and a channel set is provided in the device region, and the channel set is used for connecting electronic In the device, the redistribution layer is used to lead the channel set to a predetermined area on the package substrate, so that all or part of the channels in the channel set form a series circuit in the predetermined area, and the series circuit is used for connecting with the electrostatic discharge terminal. The encapsulation structure provided by the present application can perform electrostatic protection on the channels that need to be protected during the encapsulation process.

Description

Packaging structure

Technical Field

The application relates to the technical field of chip packaging, in particular to a packaging structure.

Background

With the development of science and technology, the requirement on the communication speed of the chip is higher and higher, and therefore, higher requirements are also put forward on the structure of the chip package.

At present, in order to ensure the stability of the performance and the service life of the chip, an electrostatic discharge (ESD) protection circuit must be added to each channel of the external connection of the chip, so as to prevent Static from bringing instant super-strong charges to the inside of the chip and causing Static death to the chip.

However, the ESD protection circuit can cause a large parasitic to the located channel, and the parasitic of the ESD protection circuit can seriously affect the communication speed of the chip during the chip operation.

SUMMERY OF THE UTILITY MODEL

The application provides a packaging structure to realize in the electronic device packaging process, carry out electrostatic protection to the passageway that electronic device need protect, and reduce electronic device and continue to receive the parasitic influence of ESD protection circuit after the encapsulation is accomplished.

The application provides a packaging structure, includes: the packaging structure comprises a packaging substrate and a rewiring layer arranged on the packaging substrate;

the package substrate includes: a plurality of device regions;

the device comprises a packaging substrate, a redistribution layer and a channel collection, wherein the channel collection is arranged in the device area and used for being connected with an electronic device, the redistribution layer is used for leading the channel collection out to a preset area on the packaging substrate, so that all or part of channels in the channel collection form a series circuit in the preset area, and the series circuit is used for being connected with an electrostatic discharge end.

In one possible design, the package substrate further includes: a device isolation region disposed between adjacent ones of the device regions;

the preset region is the device separation region;

wherein the series circuit is disconnected upon performing a separation operation on the device separation region; or,

the preset area is a partial area in the device area;

wherein the series circuit is opened after the electronic device completes a packaging operation.

In one possible design, an insulating layer is disposed on the package substrate;

a windowing structure is arranged on the insulating layer;

the rewiring layer is arranged on one surface, far away from the packaging substrate, of the insulating layer;

and the redistribution layer establishes connection with the channels in the channel set through the windowing structure.

In one possible design, a channel lead-out pad is disposed on the package substrate, the channel lead-out pad being used to establish a connection between the channel and the electronic device;

the channel leading-out pad is connected with the rewiring layer through the windowing structure.

In one possible design, a channel window is provided on the package substrate, and the channel lead-out pad is provided on the channel window so as to establish a connection between the channel lead-out pad and the channel.

In one possible design, the esd protection terminal is a ground terminal or an esd protection module port.

In one possible design, the redistribution layer is a metal material layer or a non-metal conductive material layer.

In one possible design, the redistribution layer is a single layer or a multi-layer structure.

In one possible design, the package substrate is a wafer, a substrate, or a flexible circuit board.

In one possible design, the redistribution layer is provided with a protective coating.

The application provides a packaging structure, through the preset region that rewiring layer draws the passageway set to on the encapsulation base to make all or some passageways in the passageway set form the series circuit in the preset region after be connected with the static electricity discharge end, thereby realize carrying out electrostatic protection to the passageway that needs protect.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a package substrate of a package structure according to a second embodiment of the present application;

fig. 3 is a schematic structural diagram of a conductive dielectric layer formed on a package structure according to a second embodiment of the present application;

fig. 4 is a schematic structural diagram of a molding wiring layer of a package structure according to a second embodiment of the present application;

fig. 5 is a schematic structural diagram of a molding insulating layer of a package structure according to a third embodiment of the present application;

fig. 6 is a schematic structural diagram of a package structure forming windowing structure according to a third embodiment of the present application;

fig. 7 is a schematic structural diagram of a conductive dielectric layer formed on a package structure according to a third embodiment of the present application;

fig. 8 is a schematic structural diagram of a molding wiring layer of a package structure according to a third embodiment of the present application;

fig. 9 is a schematic flowchart of a packaging method according to a fourth embodiment of the present application;

fig. 10 is a schematic flowchart of a packaging method according to a fifth embodiment of the present application;

fig. 11 is a schematic flowchart of a packaging method according to a sixth embodiment of the present application.

With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application. As shown in fig. 1, the package structure provided in this embodiment includes: a package substrate and a redistribution layer 302 disposed on the package substrate.

The package substrate includes a plurality of device regions 102, and it should be understood that the package substrate may be a wafer, a substrate, or a flexible circuit board, and the specific form of the package substrate is not limited in this embodiment. In order to explain the principle of the present embodiment in detail, the wafer 101 may be taken as a package substrate for illustration. And for device region 102 may be a portion of the package substrate that is used to package a chip or any other device.

Also, a set of channels is provided within the device region 102, wherein the set of channels within the device region 102 are used to connect electronic devices. It should be understood that the vias in the set of vias herein may be any connecting vias in a package structure, and may be on the wafer 101, or may be processed by the package, or may be on the substrate.

And for rerouting layer 302, it is understood that a conductive layer patterned on the surface of wafer 101 may be used to rearrange the set of vias in device region 102. In this embodiment, the specific number of layers of the redistribution layer 302 is not limited, and it is only required to ensure that a channel set on the device region 102, for example, a subset of channels to be protected, which need to be subjected to electrostatic protection, in the channel set can be led out to a preset region on the wafer 101 through the redistribution layer 302, so that all or part of the channels in the subset of channels to be protected form a series circuit in the preset region.

It should be understood that the channel set may be a channel lead-out pad on the wafer 101, may be a pad structure obtained by performing secondary packaging processing on the original wafer 101 on the basis of a channel lead-out pad on the wafer 101, and may also be a channel lead-out pad on other types of substrates or flexible circuit boards.

It should be noted that during the packaging process of electronic devices, for example, during the packaging process of chips, static electricity is generated from the external environment (such as devices, materials, and people), and the static electricity easily causes instant super-strong charges to the inside of the chips. Therefore, electrostatic discharge protection of the vias within the device region 102 for establishing connections with the chip is required. In the prior art, an ESD protection circuit is separately set for each channel to be protected, and after the package is cut to form a chip module, the ESD protection circuits still parasitize on each channel. The parasitic ESD protection circuits consume power of the chip module during operation, and cause reverse inductance during operation of the chip module, thereby reducing driving voltages of the channels and further affecting communication speed of the chip module.

In this embodiment, in order to perform electrostatic protection on the channels to be protected, a set of channels, for example, all or part of the channels of a subset of the channels to be protected that need to be protected by electrostatic protection in the set of channels, may form a series circuit in a preset area on the wafer 101 through the redistribution layer 302, and connect the series circuit with an electrostatic discharge terminal (e.g., an ESD protection module port or a ground).

The preset area may be any position on the wafer 101, and may be specifically determined according to an actual packaging process and a layout form of the channel set. Specifically, the preset region may be a region outside the device region 102, or may be a partial region in the device region, and it is only necessary to ensure that, after the electronic device is packaged, when the dielectric layer is disconnected in the series circuit in the preset region, the normal operation of the electronic device is not affected.

For example, the predetermined region may be the device isolation region 105, the device isolation region 105 is disposed between the adjacent device regions 102, all or part of the channels of the subset of channels to be protected, which need to be subjected to electrostatic protection, in the channel set are led out to the device isolation region 105 through the redistribution layer 302, and then all the channels are connected in series or partially connected in series together in the device isolation region 105 to form the common potential. And then the series circuit is connected with the port with the ESD protection module or the ground wire, so that zero potential is formed. Therefore, when the chip is influenced by electrostatic discharge, the charges move to a lower potential preferentially, and all the charges are conducted away along a channel with an ESD protection circuit or a ground wire, so that the internal circuit of the chip is protected from the influence of the electrostatic discharge. The redistribution layer 302 may be a metal material, such as aluminum, copper, nickel, palladium, gold, etc., and any conductive material such as a non-metal conductive material may also be used.

The device separation area 105 may be an area formed by the electronic device edges 103 of two adjacent device areas 102, wherein the device separation area 105 may be a scribe line between chips. After the chip packaging is completed, the chips are separated through a chip separation process.

Therefore, the packaging structure provided by the embodiment can reduce the influence of ESD on the chip in the packaging process. And after the packaging is finished, the chip is cut into single pieces, and the series circuit formed in the cutting channel is cut off through the cutting process, so that each channel is separated again to restore the function of the chip. And when the chip is subsequently mounted on a board, the ESD protection work of the chip is continuously finished by the board-level ESD protection process.

For another example, the preset region may also be a partial region in the device region 102, specifically, the preset region may be a middle portion of the device region 102 or another region where the redistribution layer 302 may be disposed, and may be adaptively designed according to a specific arrangement of the channel set in the device region 102. Specifically, all or part of the channels of the subset of channels to be protected, which need to be subjected to electrostatic protection, in the channel set may be led out to a partial region within the device region 102 through the redistribution layer 302, and then all the channels may be connected in series or partially connected in series together within the partial region within the device region 102 to form a common potential. And then the series circuit is connected with the port with the ESD protection module or the ground wire, so that zero potential is formed. Therefore, when the chip is influenced by electrostatic discharge, the charges move to a lower potential preferentially, and all the charges are conducted away along a channel with an ESD protection circuit or a ground wire, so that the internal circuit of the chip is protected from the influence of the electrostatic discharge.

After the electronic device is packaged, the series circuit may be cut off by a conductive dielectric layer cutting process, such as laser cutting. Then, the device region 102 is subjected to a slicing process, and each chip is separated through a chip separation process.

Therefore, the packaging structure provided by the embodiment can reduce the influence of ESD on the chip in the packaging process. And after the packaging is finished, the series circuit is cut off through a conductive medium layer cutting process, so that each channel is independently opened again to recover the chip function. And when the chip is subsequently mounted on a board, the ESD protection work of the chip is continuously finished by the board-level ESD protection process.

In this embodiment, the redistribution layer leads out the to-be-protected channel subset, which needs to be subjected to electrostatic protection, in the channel set to a preset region on the package substrate, so that all or part of channels in the to-be-protected channel subset are connected with the electrostatic discharge end after forming a series circuit in the preset region, thereby implementing electrostatic protection on the to-be-protected channels.

In addition, after the electronic device is packaged, each channel can be independently opened again by disconnecting the multi-channel series circuit, so that the chip function is recovered.

In order to elaborate the package structure provided by the present application, a wafer may be selected as a package substrate, and a packaging method of the package structure is described as follows:

fig. 2 is a schematic structural diagram of a package substrate of a package structure according to a second embodiment of the present application. As shown in fig. 2, wafer 101 includes a plurality of device regions 102, and device isolation regions 105 disposed between adjacent device regions 102.

Also, a set of channels is provided within the device region 102, wherein the set of channels within the device region 102 are used to connect electronic devices. It is understood that the channels in the channel set herein may be any connecting channels in the package structure, for example, channels for packaging a chip to establish a connection with the chip.

Wafer 101 is provided with channel extraction pads 104, where channel extraction pads 104 are used to establish a connection between the channel and the electronic device.

The device separation area 105 may be an area formed by the electronic device edges 103 of two adjacent device areas 102, wherein the device separation area 105 may be a scribe line between chips. After the chip packaging is completed, the cutting channels are cut through a chip separation process, so that each chip is separated.

It should be noted that, referring to fig. 1 and 2, the wafer 101 to be processed needs to first confirm whether the channel extraction pad 104 is operated with the pad window 103. If the incoming material has completed the windowing process, the wafer 101 only needs to be cleaned for use. If the windowing process is not finished, the packaging factory needs to perform windowing by a dry etching process or a wet etching process, and the metal pad is leaked.

Fig. 3 is a schematic structural diagram of a conductive dielectric layer formed on a package structure according to a second embodiment of the present application. As shown in fig. 3, conductive dielectric layer 301 may be formed directly on wafer 101 if wafer 101 is shipped with a predetermined insulation level and parasitic level that is achievable with the insulation layer itself on its surface.

While the conductive dielectric layer 301 may be formed by sputtering, evaporation, electroplating, chemical plating, or conductive film bonding, the specific process and material of the conductive dielectric layer 301 are not limited in this embodiment, and the theoretical conductive requirement may be satisfied. Alternatively, conductive dielectric layer 301 is typically on the order of microns, e.g., 1-8 microns.

Fig. 4 is a schematic structural diagram of a redistribution layer formed by a package structure according to a second embodiment of the present application. After forming the conductive dielectric layer, as shown in fig. 4, patterning process is performed on the conductive dielectric layer 301 to form a redistribution layer 302. It should be noted that the patterning process performed on the conductive dielectric layer 301 may be performed by using a method of applying glue first, then performing photolithography, and then performing dry etching, or a method of applying glue first, then performing photolithography, and then performing wet etching, or a patterning process such as laser direct writing, and the specific processing process performed on the conductive dielectric layer 301 is not limited in this embodiment.

With continued reference to fig. 1, the redistribution layer 302 formed through the patterning process may introduce all or a part of the vias in the set of vias into the device isolation region 105 to form a series circuit, and then connect the series circuit with an electrostatic discharge terminal (e.g., a via provided with an ESD protection circuit or a ground). Thereby directing all channels that need to implement ESD protection to device isolation area 105 and then connecting all channels in series or locally in series within device isolation area 105 to form a common potential. And then the series circuit is connected with a channel with ESD protection or a ground wire, so that zero potential is formed. Therefore, when the chip is influenced by electrostatic discharge, the charges move to a lower potential preferentially, and all the charges are conducted away along a channel with an ESD protection circuit or a ground wire, so that the internal circuit of the chip is protected from the influence of the electrostatic discharge.

Fig. 5 is a schematic structural diagram of a molding insulating layer of a package structure according to a third embodiment of the present application. Referring to fig. 2 and 5, if the wafer 101 leaves the factory and the insulating layer on the surface of the wafer cannot meet the predetermined insulating standard and parasitic standard, an insulating layer 201 is further disposed on the wafer 101.

Specifically, the insulating layer 201 may be formed on the wafer 101, wherein the insulating layer 201 may be formed on the surface of the wafer 101 by spin coating, plasma spraying, printing, film pasting, or the like.

Fig. 6 is a schematic structural diagram of a package structure forming windowing structure according to a third embodiment of the present application. As shown in fig. 6, in order to form an effective connection, after the insulating layer 201 is formed, a window structure 202 needs to be provided on the insulating layer.

Specifically, as for the completion process of the windowing structure 202, the windowing structure 202 may be processed on the insulating layer 201 by a process of photolithography and etching to expose the channel extraction pad 104.

In addition, it should be noted that the forming process of the insulating layer 201 and the windowing structure 202 is not specifically limited, and the material of the insulating layer 20 is not specifically limited, only that the surface insulation of the device region 102 is ensured, and the channel extraction pad 104 is exposed. Optionally, the thickness of the insulating layer 201 is typically in the order of microns, for example, 5 microns.

Fig. 7 is a schematic structural diagram of a conductive dielectric layer formed on a package structure according to a third embodiment of the present application. As shown in fig. 7, after forming insulating layer 201 on wafer 101 and completing fenestration 202, a conductive dielectric layer 301 may also be formed on a side of insulating layer 201 away from wafer 101.

Fig. 8 is a schematic structural diagram of a redistribution layer formed by a package structure according to a third embodiment of the present application. After the conductive dielectric layer is formed, a patterning process is performed on the conductive dielectric layer 301 to form a redistribution layer 302, as shown in fig. 8. It should be noted that the patterning process performed on the conductive dielectric layer 301 may be performed by using a method of applying glue first, then performing photolithography, and then performing dry etching, or a method of applying glue first, then performing photolithography, and then performing wet etching, or a patterning process such as laser direct writing, and the specific processing process performed on the conductive dielectric layer 301 is not limited in this embodiment.

On the basis of the above embodiment, in order to protect the formed redistribution layer 302, a protective coating may be further disposed on the redistribution layer 302, and then whether the protective coating is windowed or not and the subsequent processes may be set according to actual packaging requirements.

Fig. 9 is a schematic flowchart of a packaging method according to a fourth embodiment of the present application. As shown in fig. 9, the packaging method provided in this embodiment includes:

step 401, a channel set is disposed on a device region of a package substrate.

The package substrate includes a plurality of device regions, and it is understood that the package substrate may be a wafer, a substrate, or a flexible circuit board, and the specific form of the package substrate is not limited in this embodiment. In order to explain the principle of the present embodiment in detail, a wafer may be taken as a package substrate for illustration. And for the device region may be a portion of the package substrate that is used to package a chip or any other device.

Specifically, a set of channels is disposed within the device region, wherein the set of channels within the device region are used to connect electronic devices. It should be understood that the vias in the via set herein may be any connecting vias in a package structure, and may be on a wafer, or processed from a package, or on a substrate.

Optionally, the channel set may be a channel lead-out pad on a wafer, or a pad structure obtained by performing secondary packaging processing on the basis of a channel lead-out pad on an original wafer, or a channel lead-out pad on another type of substrate or a flexible circuit board.

Step 402, a redistribution layer is disposed on a device region of a package substrate.

In particular, a redistribution layer is understood to be a conductive layer patterned on the surface of a wafer, which can be used to rearrange the set of vias in the device region. In this embodiment, the specific number of layers of the redistribution layer is not limited, and it is only required to ensure that a subset of channels to be protected, which need to be subjected to electrostatic protection, in a channel set in the device region can be led out to a preset region on the wafer through the redistribution layer, so that all or part of the channels in the subset of channels to be protected form a series circuit in the preset region.

Step 403, packaging the electronic device on the device region.

After the redistribution layer is disposed on the device region of the package substrate, the electronic device may be packaged on the device region.

Because static electricity is generated from the external environment (e.g., equipment, materials, personnel, etc.) during the packaging process of electronic devices, for example, chips, the static electricity easily causes transient super-strong charges to the inside of the chips. Therefore, electrostatic discharge protection of the vias in the device region for establishing connections to the chip is required. In the prior art, an ESD protection circuit is separately set for each channel to be protected, and after the package is cut to form a chip module, the ESD protection circuits still parasitize on each channel. The parasitic ESD protection circuits consume power of the chip module during operation, and cause reverse inductance during operation of the chip module, thereby reducing driving voltages of the channels and further affecting communication speed of the chip module.

In this embodiment, in order to perform electrostatic protection on the channels that need to be protected, all or part of the channels in the channel set that need to be protected and are to be protected may form a series circuit in a preset area on the wafer through the redistribution layer, and the series circuit may be connected to an electrostatic discharge terminal (e.g., an ESD protection module port or a ground).

Fig. 10 is a schematic flowchart of a packaging method according to a fifth embodiment of the present application. As shown in fig. 10, the packaging method provided in this embodiment includes:

step 501, a channel set is arranged on a device area of a package substrate.

It should be noted that, for a detailed description of step 501 in this embodiment, reference is made to the related description in step 401 of fig. 9, and details are not repeated here.

Step 502 forms a conductive dielectric layer on a package substrate.

The package substrate includes a plurality of device regions, and device separation regions disposed between adjacent device regions. It should be understood that the package substrate may be a wafer, a substrate or a flexible circuit board, and the specific form of the package substrate is not limited in this embodiment. In order to explain the principle of the present embodiment in detail, a wafer may be taken as a package substrate for illustration.

Specifically, the wafer includes a plurality of device regions, and device isolation regions disposed between adjacent device regions.

And a set of channels is disposed within the device region, wherein the set of channels within the device region is for connecting electronic devices. It is understood that the channels in the channel set herein may be any connecting channels in the package structure, for example, channels for packaging a chip to establish a connection with the chip.

The wafer is provided with channel extraction pads for establishing a connection between the channel and the electronic device.

The device separation area may be an area formed by edges of electronic devices of two adjacent device areas, wherein the device separation area may be a scribe line between chips. After the chip packaging is completed, the cutting channels are cut through a chip separation process, so that each chip is separated.

The conductive dielectric layer can be formed directly on the wafer if the wafer is shipped with a predetermined insulation level and parasitic level that the surface of the wafer is accessible from the insulating layer itself.

In the description of the values, the conductive dielectric layer may be formed by sputtering, evaporation, electroplating, chemical plating, and conductive film pasting, but in this embodiment, the specific process and material of the conductive dielectric layer are not limited, and the theoretical conductive requirement may be satisfied. Alternatively, the conductive dielectric layer is typically on the order of microns, e.g., 1-8 microns.

Step 503, patterning the conductive dielectric layer to form a redistribution layer.

After the conductive dielectric layer is formed, the conductive dielectric layer is patterned to form a redistribution layer. It should be noted that the patterning process performed on the conductive dielectric layer may be performed by using a method of first applying glue, then performing photolithography, and then performing dry etching, or a method of first applying glue, then performing photolithography, and then performing wet etching, or a patterning process such as laser direct writing, and the specific processing process performed on the conductive dielectric layer is not limited in this embodiment.

Step 504, packaging the electronic device on the device region.

The redistribution layer formed through the patterning process can encapsulate all or part of the preset area on the channel packaging substrate of the channel subset to be protected, which needs to be subjected to the electrostatic protection, in the channel set to form a series circuit.

The preset area may be any position on the package substrate, and may be specifically determined according to an actual packaging process and a layout form of the channel set. Specifically, the preset region may be a region outside the device region, or may be a partial region in the device region, and it is only necessary to ensure that, after the electronic device is packaged, when the dielectric layer is disconnected in the series circuit in the preset region, the normal operation of the electronic device is not affected.

For example, the predetermined region may be a device isolation region, and the device isolation region is disposed between adjacent device regions 102, all or part of the channels of the subset of channels to be protected, which need to be subjected to electrostatic protection, in the channel set are led out to the device isolation region through the redistribution layer, and then all the channels are connected in series or partially connected in series in the device isolation region 105, so as to form a common potential. And then the series circuit is connected with the port with the ESD protection module or the ground wire, so that zero potential is formed. Therefore, when the chip is influenced by electrostatic discharge, the charges move to a lower potential preferentially, and all the charges are conducted away along a channel with an ESD protection circuit or a ground wire, so that the internal circuit of the chip is protected from the influence of the electrostatic discharge. The redistribution layer 302 may be a metal material, such as aluminum, copper, nickel, palladium, gold, etc., and any conductive material such as a non-metal conductive material may also be used.

For another example, the preset region may also be a partial region in the device region, specifically, the preset region may be a middle portion of the device region or another region where the redistribution layer layout may be performed, and the adaptive design may be performed according to a specific arrangement of the channel set in the device region. And then all or part of channels of a channel subset to be protected, which need to be subjected to electrostatic protection, in the channel set are led out to a partial region in the device region through a rewiring layer, and then all the channels are connected in series or partially connected in series in the partial region in the device region to form a common potential. And then the series circuit is connected with the port with the ESD protection module or the ground wire, so that zero potential is formed. Therefore, when the chip is influenced by electrostatic discharge, the charges move to a lower potential preferentially, and all the charges are conducted away along a channel with an ESD protection circuit or a ground wire, so that the internal circuit of the chip is protected from the influence of the electrostatic discharge.

In this embodiment, by forming the redistribution layer, a subset of channels to be protected, which need to be subjected to electrostatic protection in the channel set, may be led out to a preset region on the package substrate, so that all or part of the channels in the subset of channels to be protected are connected to the electrostatic discharge end after forming a series circuit in the preset region, thereby implementing electrostatic protection on the channels that need to be protected.

On the basis of the fourth embodiment, in order to segment the chip module obtained by the package structure obtained by the fourth embodiment, it is ensured that the segmented chip module can normally operate. And after the electronic device is packaged, disconnecting all or part of channels in the channel subset to be protected to form a series circuit in a preset area.

Specifically, when the preset region is a device separation region, the device separation region may be set as a scribe line between chips. After the chip packaging is completed, the chips are separated through a chip separation process. After the packaging is finished, the chip is cut into single pieces, and the series circuit formed in the cutting channel is cut off through the cutting process, so that each channel is separated again to restore the function of the chip. And when the chip is subsequently mounted on a board, the ESD protection work of the chip is continuously finished by the board-level ESD protection process.

In addition, when the preset region is a partial region in the device region, the series circuit may be disconnected by a conductive medium layer cutting process, for example, laser cutting, after the electronic device is packaged. Then, the device region is subjected to slicing processing, and each chip is separated through a chip separation process.

Therefore, in the embodiment, the serial circuit for performing electrostatic protection is cut off, so that each channel is opened independently again to recover the chip function, and thus, the packaging structure of the embodiment can reduce or even avoid the parasitic of the ESD protection circuit to each channel, thereby effectively reducing the power consumption of the chip during operation, and also improving the communication speed of the chip.

Fig. 11 is a schematic flowchart of a packaging method according to a sixth embodiment of the present application. As shown in fig. 11, the packaging method provided in this embodiment includes:

step 601, a channel set is arranged on a device area of a package substrate.

It should be noted that for the detailed description of the sealing step 601 in this embodiment, reference is made to the related description in step 401 of fig. 9, and details are not repeated here.

Step 602, an insulating layer is formed on a package substrate.

The wafer may be further selected as a package substrate for illustration, and specifically, if the wafer leaves the factory and the insulating layer on the surface of the wafer cannot meet the preset insulating standard and the parasitic standard, the wafer is further provided with an insulating layer.

Specifically, an insulating layer may be formed on a wafer, wherein the insulating layer may be formed on the surface of the wafer by spin coating, plasma spraying, printing, film pasting, and other processes.

Step 603, a windowing structure is arranged on the insulating layer.

In order to form an effective connection, a window structure needs to be provided on the insulating layer after the insulating layer is formed.

Specifically, as for the completion process of the windowing structure, the windowing structure may be processed on the insulating layer through a photolithography and etching process to expose the channel extraction pad.

In addition, it is worth explaining that the forming process of the insulating layer and the windowing structure is not specifically limited, the material of the insulating layer is not specifically limited, and only the surface insulation of the device region is ensured, and the channel leading-out pad is exposed. Alternatively, the thickness of the insulating layer is typically in the order of microns, and may be, for example, 5 microns.

Step 604 forms a conductive dielectric layer on a side of the insulating layer remote from the package substrate.

After the insulating layer is formed on the wafer and the windowing structure is completed, a conductive dielectric layer can be formed on the side of the insulating layer away from the wafer.

Step 605, the conductive dielectric layer is patterned to form a redistribution layer.

Step 606, encapsulating the electronic device on the device region.

It should be noted that, the specific implementation manner of step 606 in this embodiment refers to the description of step 504 in the embodiment shown in fig. 10, and is not described herein again.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A packaging structure, characterized in that, comprising: a packaging substrate and a redistribution layer arranged on the packaging substrate;

The package substrate includes: several device regions;

A channel set is provided in the device area, the channel set is used for connecting electronic devices, and the redistribution layer is used to lead the channel set to a preset area on the packaging substrate, so that the channel set is All or part of the channels in the preset area form a series circuit, and the series circuit is used for connection with the electrostatic discharge terminal.

2 . The package structure according to claim 1 , wherein the package substrate further comprises: a device separation region disposed between adjacent device regions; 3 .

the preset area is the device separation area;

Wherein, the series circuit is disconnected during the separation operation of the device separation region; or,

The preset area is a partial area within the device area;

Wherein, the series circuit is disconnected after the electronic device completes the packaging operation.

3. The package structure according to claim 1 or 2, wherein an insulating layer is provided on the package substrate;

The insulating layer is provided with a window structure;

The redistribution layer is arranged on the side of the insulating layer away from the package substrate;

The redistribution layer establishes connections with the channels in the channel set through the window structure.

4 . The package structure according to claim 3 , wherein a channel lead-out pad is provided on the package substrate, and the channel lead-out pad is used to establish a connection between the channel and the electronic device; 5 .

The channel lead-out pad is connected to the redistribution layer through the window structure.

5 . The package structure according to claim 4 , wherein a channel opening is provided on the package substrate, and the channel lead-out pad is arranged on the channel opening, so that the channel lead-out pad is formed. 6 . Establish a connection with the channel.

6 . The package structure according to claim 1 or 2 , wherein the electrostatic discharge terminal is a ground terminal or an electrostatic protection module port. 7 .

7 . The package structure according to claim 1 , wherein the redistribution layer is a metal material layer or a non-metal conductive material layer. 8 .

8. The package structure according to claim 1 or 2, wherein the redistribution layer is a single-layer or multi-layer structure.

9. The package structure according to claim 1 or 2, wherein the package substrate is a wafer, a substrate or a flexible circuit board.

10. The package structure according to claim 1 or 2, wherein a protective coating is provided on the redistribution layer.