CN209746550U - detection circuit of radio frequency SOC chip based on digital-analog hybrid simulation platform - Google Patents
detection circuit of radio frequency SOC chip based on digital-analog hybrid simulation platform Download PDFInfo
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- CN209746550U CN209746550U CN201920770585.3U CN201920770585U CN209746550U CN 209746550 U CN209746550 U CN 209746550U CN 201920770585 U CN201920770585 U CN 201920770585U CN 209746550 U CN209746550 U CN 209746550U
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Abstract
the utility model discloses a detection circuitry of radio frequency SOC chip based on digifax hybrid simulation platform, include: the crystal oscillator model is used for providing oscillation frequency for the detection circuit; the SOC chip to be tested simulates a front-end circuit and is used for being connected with the SOC chip mounting MCU and the digital circuit; the SOC chip to be tested is mounted with the MCU and the digital circuit and used for generating a reading signal and decoding a modulation signal of the RFID tag digital circuit; the radio frequency antenna model comprises an SOC chip antenna, an RFID tag antenna and a coupling factor, wherein the coupling factor is a coupling factor model mind of the digital-analog hybrid simulation platform and is used for adjusting the coupling coefficient of the SOC chip antenna and the RFID tag antenna; the RFID tag analog front end circuit is used for being connected with the RFID tag digital circuit; and the RFID label digital circuit model is used for generating the modulation signal. The utility model discloses shorten the research and development time, simplified the verification degree of difficulty.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a detection circuitry of radio frequency SOC chip based on digifax hybrid simulation platform.
background
The intelligent card application system can be spread in a large scale in the 'twelve five' period, wherein the vigorous popularization of the financial IC card and the popularization of the network identity management system can bring huge market demands to the special processing chip of the SOC chip of the intelligent terminal of the Internet of things.
the technology of the internet of things represented by an intelligent terminal (hereinafter, referred to as a reader) of the internet of things (System on Chip) is urgently needed to be applied to identity recognition of people at present, or individual recognition in traffic and logistics application, or cash replacement of an electronic wallet, wherein an intelligent tag is expected to serve as a technical role of replacing a bar code as a commodity identification, the technology of the intelligent terminal of the internet of things (SOC) is related to how to maintain and improve the industrial advantages of the traditional manufacturing industry, technical innovation and industrial upgrading of modern logistics industry, modern trade and modern business are greatly promoted, and novel modern service industries such as modern exhibition industry, modern sports industry, modern culture tourism industry and modern information consumption industry are also serving objects of the intelligent terminal of the internet of things. The automatic identification and automatic payment functions of the system are a symbolic technology and a key means for promoting the traditional service industry to march to the modern service industry.
However, in order to implement wide manufacturing and application of a reader-writer SOC chip and a tag of an RFID (Radio Frequency Identification), a corresponding fast verification method of a high-Frequency Radio Frequency SOC chip needs to be provided.
SUMMERY OF THE UTILITY MODEL
For overcoming current RFID's reader-writer SOC chip research and development time long, it is big to verify the degree of difficulty, the problem of the slow defect of industrialization, the embodiment of the utility model provides a detection circuitry of radio frequency SOC chip based on digital analog hybrid simulation platform, include:
The crystal oscillator model is used for providing oscillation frequency for the detection circuit and comprises an XIN pin and an XOUT pin;
the SOC chip analog front-end circuit to be tested is used for being connected with the SOC chip mounting MCU and the digital circuit, and comprises an OSCIN pin and an OSCOUT pin, wherein the OSCIN pin is connected with a XIN pin, and the XOUT pin is connected with the OSCOUT pin;
the SOC chip to be tested is mounted with the MCU and the digital circuit and used for generating a reading signal and decoding a modulation signal of the RFID tag digital circuit;
The radio frequency ANTENNA model comprises an SOC chip ANTENNA, an RFID tag ANTENNA and coupling factors, wherein the SOC chip ANTENNA comprises TX1 pins, TX2 pins, RX pins and VMID pins and is used for being connected with the SOC chip analog front end circuit to be tested, the RFID tag ANTENNA comprises ANTENNA1 pins and ANTENNA2 pins and is used for being connected with the RFID tag analog front end circuit, and the coupling factors are coupling factor models mind of a digital-analog hybrid simulation platform and are used for adjusting the coupling coefficients of the SOC chip ANTENNA and the RFID tag ANTENNA;
The RFID tag analog front end circuit is used for being connected with the RFID tag digital circuit;
And the RFID label digital circuit model is used for generating the modulation signal.
Further, the above-mentioned crystal oscillator model includes off-chip circuit and on-chip circuit, the on-chip circuit includes the inverter, the inverter includes XIN pin and XOUT pin, the off-chip circuit includes electric capacity C1 and electric capacity C2, electric capacity C1 first end is connected with XIN pin, electric capacity C2 first end is connected with the XOUT pin, electric capacity C1 and C2's second end all ground connection, still be connected with quartz crystal oscillator equivalent circuit between electric capacity C1 first end and the C2 second end.
further, the quartz crystal oscillator equivalent circuit comprises a static capacitor C3 and a series oscillation circuit which are connected in parallel, wherein the series oscillation circuit comprises an equivalent resistor R0, an equivalent inductor L0 and an equivalent capacitor C0 which are connected in series.
Further, TX1 and TX2 of the SOC chip antenna are signal transmitting pins, RX is a signal receiving pin, and VMID is a reference level;
The TX1 is grounded through a resistor R4, an inductor Lin1, a capacitor C4, a resistor R6 and an inductor L1 which are sequentially connected in series, and the TX2 is grounded through a resistor R5, an inductor Lin2, a capacitor C5, a resistor R7 and an inductor L2 which are sequentially connected in series; a capacitor C6 is further connected between the inductor Lin1 and the capacitor C4, a capacitor C7 is further connected between the inductor Lin2 and the capacitor C5, a capacitor C8 is further connected between the capacitor C4 and the resistor R6, a capacitor C9 is further connected between the capacitor C5 and the resistor R7, and the other ends of the capacitor C6, the capacitor C7, the capacitor C8 and the capacitor C9 are grounded;
the RX is sequentially connected with a resistor RRX1 and an inductor CRX1 in series, and the other end of the CRX1 is connected between a resistor R6 and an inductor L1;
VMID and resistance RRX2 series connection, the other end of resistance RRX2 is connected between RX and resistance RRX1, still be connected with inductance CVMID between VMID and the resistance RRX1, inductance CVMID other end ground connection.
further, the RFID tag ANTENNA comprises a capacitor C10 and an inductor Lcard which are connected in series, an ANTENNA1 pin is led out from the first end of the capacitor C10, an ANTENNA2 pin is led out from the other end of the capacitor C10, the ANTENNA1 pin is used for connecting an ant1 interface of the RFID tag analog front-end circuit, and the ANTENNA2 pin is used for connecting an ant2 interface of the RFID tag analog front-end circuit.
Further, the coupling factors include a coupling factor mind1 and a coupling factor mind2, wherein mind1 is used for adjusting coupling coefficients of an inductor L1 and an inductor LCARD, and mind2 is used for adjusting coupling coefficients of an inductor L2 and an inductor LCARD.
Further, the RFID tag analog front-end circuit comprises a rectifying circuit and a load modulation circuit.
Further, the rectifier circuit comprises a limiter, an electrostatic discharge circuit and a multi-stage field effect transistor circuit, and the load modulation circuit comprises the electrostatic discharge circuit and the multi-stage field effect transistor circuit.
further, the operating frequency of the SOC chip antenna and the RFID tag antenna is 13.56 MHz.
The embodiment of the utility model provides a through the detection circuitry of the radio frequency SOC chip of building digital analog hybrid simulation platform for high frequency radio frequency SOC chip can realize verifying on simulation platform, has shortened the research and development time, has simplified the verification degree of difficulty, does benefit to the quick industrialization that realizes the SOC chip.
drawings
in order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a block diagram of the detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform according to the embodiment of the present invention;
Fig. 2 is a circuit diagram of a radio frequency antenna model according to an embodiment of the present invention;
Fig. 3 is a circuit diagram of a rectifier circuit in an RFID tag analog front end circuit according to an embodiment of the present invention;
Fig. 4 is a circuit diagram of a load modulation circuit in an RFID tag analog front end circuit according to an embodiment of the present invention.
Detailed Description
in order to make the technical problem, technical solution and advantageous effects solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to further explain the present invention in detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
When embodiments of the present invention refer to the ordinal numbers "first", "second" (if present), etc., it should be understood that the words are used for distinguishing between them unless they are used to actually convey the sequence in context.
in the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected" (if present) are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1, an embodiment of the present invention discloses a detection circuit of a radio frequency SOC chip based on a digital-analog hybrid simulation platform, including:
the crystal oscillator model is used for providing oscillation frequency for the detection circuit and comprises an XIN pin and an XOUT pin;
the SOC chip analog front-end circuit to be tested is used for being connected with the SOC chip mounting MCU and the digital circuit, and comprises an OSCIN pin and an OSCOUT pin, wherein the OSCIN pin is connected with a XIN pin, and the XOUT pin is connected with the OSCOUT pin;
The SOC chip to be tested is mounted with the MCU and the digital circuit and used for generating a reading signal and decoding a modulation signal of the RFID tag digital circuit;
The radio frequency ANTENNA model comprises an SOC chip ANTENNA, an RFID tag ANTENNA and coupling factors, wherein the SOC chip ANTENNA comprises TX1 pins, TX2 pins, RX pins and VMID pins and is used for being connected with the SOC chip analog front end circuit to be tested, the RFID tag ANTENNA comprises ANTENNA1 pins and ANTENNA2 pins and is used for being connected with the RFID tag analog front end circuit, and the coupling factors are coupling factor models mind of a digital-analog hybrid simulation platform and are used for adjusting the coupling coefficients of the SOC chip ANTENNA and the RFID tag ANTENNA;
the RFID tag analog front end circuit is used for being connected with the RFID tag digital circuit;
And the RFID label digital circuit model is used for generating the modulation signal.
Referring to fig. 2, the crystal oscillator model includes an off-chip circuit and an on-chip circuit, the on-chip circuit includes an inverter, the inverter includes the XIN pin and the XOUT pin, the off-chip circuit includes a capacitor C1 and a capacitor C2, a first end of the capacitor C1 is connected to the XIN pin, a first end of the capacitor C2 is connected to the XOUT pin, second ends of the capacitors C1 and C2 are both grounded, and a quartz crystal oscillator equivalent circuit is further connected between the first end of the capacitor C1 and the second end of the capacitor C2.
The inverter provides the necessary gain and produces a 180 ° phase shift, and the capacitor C1 and the capacitor C2 set the feedback factor of the circuit, in combination with the additional 180 ° phase shift required for the oscillation produced by the inductive reactance of the crystal oscillator, plus the 180 ° phase shift provided by the inverter, the circuit loop gain meets the "barkhausen criterion":
the circuit will start oscillating at ω 0. These two conditions are necessary but not sufficient, and in order to ensure oscillation in the presence of temperature and process variations, the loop gain may typically be chosen to be twice or three times the nominal value.
In the embodiment, the crystal oscillation starting time can be shortened by increasing the W/L value of the PMOS tube and the NMOS tube of the phase inverter.
the quartz crystal oscillator equivalent circuit comprises a static capacitor C3 and a series oscillation circuit which are connected in parallel, wherein the series oscillation circuit comprises an equivalent resistor R0, an equivalent inductor L0 and an equivalent capacitor C0 which are connected in series.
the quartz crystal oscillator is formed by connecting a series oscillation circuit consisting of an equivalent resistor R0, an equivalent inductor L0 and an equivalent capacitor C0 in parallel with a static capacitor C3. In the equivalent circuit, L0, C0 constitute the series resonance circuit, and the resonant frequency is:
And L0, C0 and C3 form a parallel resonant circuit, and the resonant frequency is as follows:
when the working frequency f is less than f0, the crystal is capacitive; when the working frequency f0< f < f ∞ the crystal is inductive; and when the working frequency f is more than f ∞, the crystal is capacitive. The crystal exhibits an inductive property in an oscillation circuit of a crystal oscillator master stage, i.e., an operating frequency satisfying f0< f < f ∞.
TX1 and TX2 of the SOC chip antenna are signal transmitting pins, RX is a signal receiving pin and VMID is a reference level;
The TX1 is grounded through a resistor R4, an inductor Lin1, a capacitor C4, a resistor R6 and an inductor L1 which are sequentially connected in series, and the TX2 is grounded through a resistor R5, an inductor Lin2, a capacitor C5, a resistor R7 and an inductor L2 which are sequentially connected in series; a capacitor C6 is further connected between the inductor Lin1 and the capacitor C4, a capacitor C7 is further connected between the inductor Lin2 and the capacitor C5, a capacitor C8 is further connected between the capacitor C4 and the resistor R6, a capacitor C9 is further connected between the capacitor C5 and the resistor R7, and the other ends of the capacitor C6, the capacitor C7, the capacitor C8 and the capacitor C9 are grounded;
the RX is sequentially connected with a resistor RRX1 and an inductor CRX1 in series, and the other end of the CRX1 is connected between a resistor R6 and an inductor L1;
VMID and resistance RRX2 series connection, the other end of resistance RRX2 is connected between RX and resistance RRX1, still be connected with inductance CVMID between VMID and the resistance RRX1, inductance CVMID other end ground connection.
In this embodiment, the resistor RRX1 and the inductor CRX1 form a receiving end voltage dividing circuit, which is used to divide and amplitude-reduce the voltage of the signal received at the two ends of the inductor L1 to a suitable voltage domain range, and the TX1 and the TX2 can be driven by a single end or by two ends simultaneously, which can meet the antenna matching condition, and match to 13.56 MHZ.
The RFID tag ANTENNA comprises a capacitor C10 and an inductor Lcard which are connected in series, an ANTENNA1 pin is led out from the first end of the capacitor C10, an ANTENNA2 pin is led out from the other end of the capacitor C10, the ANTENNA1 pin is used for being connected with an ant1 interface of an RFID tag analog front-end circuit, and the ANTENNA2 pin is used for being connected with an ant2 interface of the RFID tag analog front-end circuit.
The coupling factors comprise a coupling factor mind1 and a coupling factor mind2, wherein mind1 is used for adjusting coupling coefficients of an inductor L1 and an inductor LCARD, and mind2 is used for adjusting coupling coefficients of an inductor L2 and an inductor Lcard.
The AMS digital-analog simulation platform is mainly used for simulating the functional performance of the radio frequency SOC chip, so that the RFID tag analog front-end circuit of the simulation platform is simplified, and a rectifying circuit and a load modulation circuit are mainly built, so that the RFID tag analog front-end circuit can receive and transmit signals.
Referring to fig. 3, the rectifying circuit includes a limiter, an electrostatic discharge circuit and a multi-stage fet circuit, and referring to fig. 4, the load modulation circuit includes an electrostatic discharge circuit and a multi-stage fet circuit. The RFID label digital circuit model is used for outputting a dout signal in the load modulation circuit.
The embodiment of the utility model provides a through the detection circuitry of the radio frequency SOC chip of building digital analog hybrid simulation platform for high frequency radio frequency SOC chip can realize verifying on simulation platform, has shortened the research and development time, has simplified the verification degree of difficulty, does benefit to the quick industrialization that realizes the SOC chip.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. a detection circuit of a radio frequency SOC chip based on a digital-analog hybrid simulation platform is characterized by comprising:
The crystal oscillator model is used for providing oscillation frequency for the detection circuit and comprises an XIN pin and an XOUT pin;
the SOC chip analog front-end circuit to be tested is used for being connected with the SOC chip mounting MCU and the digital circuit, and comprises an OSCIN pin and an OSCOUT pin, wherein the OSCIN pin is connected with a XIN pin, and the XOUT pin is connected with the OSCOUT pin;
The SOC chip to be tested is mounted with the MCU and the digital circuit and used for generating a reading signal and decoding a modulation signal of the RFID tag digital circuit;
the radio frequency ANTENNA model comprises an SOC chip ANTENNA, an RFID tag ANTENNA and coupling factors, wherein the SOC chip ANTENNA comprises TX1 pins, TX2 pins, RX pins and VMID pins and is used for being connected with the SOC chip analog front end circuit to be tested, the RFID tag ANTENNA comprises ANTENNA1 pins and ANTENNA2 pins and is used for being connected with the RFID tag analog front end circuit, and the coupling factors are coupling factor models mind of a digital-analog hybrid simulation platform and are used for adjusting the coupling coefficients of the SOC chip ANTENNA and the RFID tag ANTENNA;
the RFID tag analog front end circuit is used for being connected with the RFID tag digital circuit;
And the RFID label digital circuit model is used for generating the modulation signal.
2. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform, wherein the crystal oscillator model comprises an off-chip circuit and an on-chip circuit, the on-chip circuit comprises an inverter, the inverter comprises the XIN pin and an XOUT pin, the off-chip circuit comprises a capacitor C1 and a capacitor C2, a first end of the capacitor C1 is connected with the XIN pin, a first end of the capacitor C2 is connected with the XOUT pin, second ends of the capacitors C1 and C2 are both grounded, and a quartz crystal oscillator equivalent circuit is connected between the first end of the capacitor C1 and the second end of the capacitor C2.
3. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform as claimed in claim 2, wherein the quartz crystal oscillator equivalent circuit comprises a static capacitor C3 and a series resonant circuit connected in parallel, the series resonant circuit comprises an equivalent resistor R0, an equivalent inductor L0 and an equivalent capacitor C0 connected in series.
4. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform of claim 3, wherein TX1 and TX2 of the SOC chip antenna are signal transmission pins, RX is a signal reception pin, and VMID is a reference level;
the TX1 is grounded through a resistor R4, an inductor Lin1, a capacitor C4, a resistor R6 and an inductor L1 which are sequentially connected in series, and the TX2 is grounded through a resistor R5, an inductor Lin2, a capacitor C5, a resistor R7 and an inductor L2 which are sequentially connected in series; a capacitor C6 is further connected between the inductor Lin1 and the capacitor C4, a capacitor C7 is further connected between the inductor Lin2 and the capacitor C5, a capacitor C8 is further connected between the capacitor C4 and the resistor R6, a capacitor C9 is further connected between the capacitor C5 and the resistor R7, and the other ends of the capacitor C6, the capacitor C7, the capacitor C8 and the capacitor C9 are grounded;
The RX is sequentially connected with a resistor RRX1 and an inductor CRX1 in series, and the other end of the CRX1 is connected between a resistor R6 and an inductor L1;
VMID and resistance RRX2 series connection, the other end of resistance RRX2 is connected between RX and resistance RRX1, still be connected with inductance CVMID between VMID and the resistance RRX1, inductance CVMID other end ground connection.
5. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform, according to claim 4, wherein the RFID tag ANTENNA comprises a capacitor C10 and an inductor Lcard which are connected in series, a first end of the capacitor C10 leads out an ANTENNA1 pin, the other end of the capacitor C10 leads out an ANTENNA2 pin, the ANTENNA1 pin is used for connecting with an ant1 interface of the RFID tag analog front-end circuit, and the ANTENNA2 pin is used for connecting with an ant2 interface of the RFID tag analog front-end circuit.
6. the detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform of claim 5, wherein the coupling factors include a coupling factor mind1 and a coupling factor mind2, wherein mind1 is used for adjusting coupling coefficients of an inductor L1 and an inductor LCARD, and mind2 is used for adjusting coupling coefficients of an inductor L2 and an inductor Lcard.
7. the detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform of claim 6, wherein the RFID tag analog front end circuit includes a rectification circuit and a load modulation circuit.
8. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform of claim 7, wherein the rectification circuit comprises a limiter, an electrostatic discharge circuit and a multi-stage field effect transistor circuit, and the load modulation circuit comprises an electrostatic discharge circuit and a multi-stage field effect transistor circuit.
9. The detection circuit of the radio frequency SOC chip based on the digital-analog hybrid simulation platform of claim 8, wherein the operation frequency of the SOC chip antenna and the RFID tag antenna is 13.56 MHz.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110276106A (en) * | 2019-05-24 | 2019-09-24 | 杰创智能科技股份有限公司 | A kind of detection circuit of the radio frequency SOC chip based on numerical model analysis emulation platform |
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2019
- 2019-05-24 CN CN201920770585.3U patent/CN209746550U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110276106A (en) * | 2019-05-24 | 2019-09-24 | 杰创智能科技股份有限公司 | A kind of detection circuit of the radio frequency SOC chip based on numerical model analysis emulation platform |
| CN110276106B (en) * | 2019-05-24 | 2024-02-13 | 杰创智能科技股份有限公司 | Detection circuit of radio frequency SOC chip based on digital-analog hybrid simulation platform |
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