CN209674396U - A low power consumption anti-theft alarm RFID tag - Google Patents

Abstract

The utility model discloses a kind of low-power consumption burglar alarm RFID label tags, including RFID chip, the Vin2 input terminal of the RFID chip is connected with communication antenna, the end VP of the RFID chip is connect with the drain electrode of PMOS tube MP, the end VA of the RFID chip and the end VA of insurance circuit connect, the end VAD of the RFID chip and the end VAD of warning circuit connect, the ground terminal ground connection of the RFID chip.Label provided by the utility model other than it can execute the task of common label, anti-theft warning circuit the label artificially torn to pieces or because other reasons are damaged when can automatic alarm, anti-theft magnetic snap and common label can be replaced.

Description

A low power consumption anti-theft alarm RFID tag

technical field

The utility model relates to the technical field of RFID tags, in particular to a low-power consumption anti-theft alarm RFID tag.

Background technique

Usually in retail areas such as clothing, passive RFID tags or anti-theft magnetic buckles are used for inventory counting and checkout. Passive RFID tags and anti-theft magnetic buckles can be easily removed, but in most cases they cannot serve the purpose of anti-theft, causing huge economic losses to retailers and related industries.

Utility model content

In order to solve the problems existing in the prior art, the purpose of this utility model is to provide a low power consumption anti-theft alarm RFID tag. In addition to performing the tasks of ordinary tags, the anti-theft alarm circuit of the tag is artificially torn or damaged. It will automatically alarm when it is damaged due to other reasons, and can replace the anti-theft magnetic buckle and ordinary labels.

In order to achieve the above object, the technical solution adopted in the utility model is: a low power consumption anti-theft alarm RFID tag, including an RFID chip, the Vin2 input end of the RFID chip is connected with a communication antenna, and the VP end of the RFID chip is connected to the PMOS The drain of the pipe MP is connected, the VA end of the RFID chip is connected to the VA end of the insurance circuit, the VAD end of the RFID chip is connected to the VAD end of the alarm circuit, and the ground end of the RFID chip is grounded.

The gate of the PMOS transistor MP is connected to the output terminal of the AND gate AND, the source of the PMOS transistor MP is connected to the power supply VDD; the first input terminal of the AND gate AND is connected to the VT terminal of the wake-up circuit, and the The second input terminal of the AND gate AND is connected to the VA terminal of the insurance circuit; the Vin1 terminal of the wake-up circuit is connected to the rectifying antenna, the ground terminal of the wake-up circuit is grounded, and the power input terminal of the wake-up circuit is connected to the power supply VDD; The first output end of the insurance circuit is connected to the power supply VDD, the VF port of the insurance circuit is connected to the power supply VDD through an insurance line, the ground terminal of the insurance circuit is grounded; the input end of the alarm circuit is connected to the power supply VDD connected, the ground terminal of the alarm circuit is grounded, the breakage of the electrical connection of the safety wire can cause the connection of the alarm circuit, and then cause the alarm device to send an alarm signal.

The rectifying antenna is connected to the wake-up circuit. When there is no RFID reader signal, the input terminal Vin of the wake-up circuit is at a low level, and the VT terminal of the wake-up circuit inputs an AND gate and outputs a high level, and the PMOS transistor MP is turned off. The RFID chip is in a power-off state and does not consume any current; when the goods need to be settled, the signal from the RFID reader increases the output voltage of the rectenna, and when the voltage is higher than the threshold set in the wake-up circuit, the wake-up circuit The output VT is low level, so that the AND gate AND outputs a low level, and then MP is turned on, the RFID chip is in a working state, and normal read and write communication is performed. When the safety line of the insurance label is cut off, the output VA of the insurance circuit outputs a low level, so that the AND gate AND outputs a low level, the PMOS tube MP is turned on, and the RFID is in a working state, and at the same time VA makes the RFID send an alarm data through the communication antenna. Start the alarm. If the insurance line is intact but has not been settled normally, the built-in passive alarm circuit will trigger the alarm when the RFID leaves the store. When there is no need for communication, the output of the wake-up circuit and the insurance circuit are at high level at the same time, and the output of the AND gate is at a high level, so that the PMOS transistor MP is in the off state, the RFID chip is disconnected from the power supply, and the label system is in a completely off state , does not consume any static power.

Preferably, the wake-up circuit includes a voltage detection chip VD1, the output terminal of the voltage detection chip VD1 is connected to the power supply through a resistor R1, and the VT output terminal of the voltage detection chip VD1 is also connected to an input terminal of the AND gate AND, The input end of the voltage detection chip VD1 is connected with a rectifying antenna.

Preferably, the insurance circuit includes a voltage detection chip VD2, the output terminal of the voltage detection chip VD2 is connected to the VA terminal, the output terminal of the voltage detection chip VD2 is also connected to the power supply VDD through a pull-up resistor R2, and the voltage The output end of the detection chip VD2 is connected to the drain of the PMOS transistor M3, the source of the PMOS transistor M3 is connected to the power supply VDD, the gate of the PMOS transistor M3 is connected to the protection line through a resistor R3, and the gate of the PMOS transistor M3 is connected to the protection line. The gate is grounded through the resistor R4, and the ground terminal of the voltage detection chip VD2 is grounded.

Preferably, the alarm circuit includes a resistor R5, an inductor L1, a capacitor C1, an NMOS transistor M4, an inductor L2, and an NMOS transistor M5. One end of the parallel connection of the resistor R5, the inductor L1, and the capacitor C1 is connected to the power supply VDD, and the other end is connected to the power supply VDD. The drain of the NMOS transistor M4 is connected, the source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M5, the gate of the NMOS transistor M4 is grounded through the inductor L2, and the gate of the NMOS transistor M5 is connected to the VAD port , the source of the NMOS transistor M5 is grounded.

Preferably, the voltage detection chip VD1 includes a high-voltage monitoring circuit, a medium-voltage monitoring circuit and a low-voltage detection circuit, the VO output terminal of the high-voltage monitoring circuit is connected to the control terminal of the medium-voltage monitoring circuit, and the VIN of the medium-voltage monitoring circuit The output terminal is connected to the monitoring terminal of the low-voltage monitoring circuit, the VO output terminal of the medium-voltage monitoring circuit is connected to the control terminal of the low-voltage monitoring circuit, the open-drain output terminal VOD1 of the high-voltage monitoring circuit, the open-drain output terminal of the medium-voltage monitoring circuit Both the drain output terminal VOD2 and the open-drain output terminal VOD3 of the low-voltage monitoring circuit are connected to the VOD terminal, and the input terminals of the high-voltage monitoring circuit and the medium-voltage monitoring circuit are connected to the VIN terminal of the monitoring object. The high-voltage monitoring circuit , The ground terminals of the medium voltage monitoring circuit and the low voltage monitoring circuit are all grounded.

Preferably, the circuit connections of the voltage detection chip VD2 and the voltage detection chip VD1 are the same.

The beneficial effects of the utility model are:

In addition to performing the tasks of ordinary tags, the tag's anti-theft alarm circuit will automatically alarm when the tag is artificially torn or damaged due to other reasons, which can replace the anti-theft magnetic buckle and ordinary tags; when the tag is not working, the battery does not Therefore, the work does not generate power consumption, and does not require continuous monitoring of DC power supply. The wake-up adopts the power switch gating method. After receiving the trigger signal through the passive sensor, the entire system will wake up to generate power consumption, which is energy-saving and environmentally friendly, and increases the service life of the label.

Description of drawings

Fig. 1 is a schematic structural view of a low-power anti-theft alarm RFID tag according to an embodiment of the present invention;

Fig. 2 is the connection schematic diagram of the wake-up circuit of the utility model embodiment;

Fig. 3 is the connection schematic diagram of the safety circuit of the utility model embodiment;

Fig. 4 is the connection schematic diagram of the warning circuit of the utility model embodiment;

Fig. 5 is a circuit connection schematic diagram of the voltage detection circuit VD1 of the utility model embodiment;

Fig. 6 is a schematic diagram of the connection of the high-voltage monitoring circuit of the embodiment of the utility model;

Fig. 7 is a schematic diagram of the connection of the medium voltage monitoring circuit in the embodiment of the present invention;

Fig. 8 is a schematic diagram of the connection of the low-voltage monitoring circuit of the embodiment of the present invention.

Explanation of reference signs:

1. High-voltage monitoring circuit; 2. Medium-voltage monitoring circuit; 3. Low-voltage monitoring circuit; 101. PMOS-Q1; 102. First capacitor; 103. Inverter; 104. Diode D1; 105. NMOS-Q2; 106. PMOS-Q3; 107, NMOS-Q4; 201, first gating switch; 202, PMOS-Q5; 203, second capacitor; 204, first selector; 205, PMOS-Q6; 206, NMOS-Q7; 207 , the first buffer; 208, NMOS-Q8; 301, the second gating switch; 302, PMOS-Q9; 303, the third capacitor; 304, the second selector; 305, NMOS-Q10; 306, PMOS-Q11 ; 307, the second buffer; 308, NMOS-Q12.

Detailed ways

Embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings.

Example 1:

As shown in Figures 1-4, a low-power anti-theft alarm RFID tag includes an RFID chip, the Vin2 input end of the RFID chip is connected to a communication antenna, and the VP end of the RFID chip is connected to the drain of the PMOS transistor MP The VA end of the RFID chip is connected to the VA end of the insurance circuit, the VAD end of the RFID chip is connected to the VAD end of the alarm circuit, and the ground end of the RFID chip is grounded. The model of the RFID chip is AS3930.

The gate of the PMOS transistor MP is connected to the output terminal of the AND gate AND, the source of the PMOS transistor MP is connected to the power supply VDD; the first input terminal of the AND gate AND is connected to the VT terminal of the wake-up circuit, and the The second input terminal of the AND gate AND is connected to the VA terminal of the insurance circuit; the Vin1 terminal of the wake-up circuit is connected to the rectifying antenna, the ground terminal of the wake-up circuit is grounded, and the power input terminal of the wake-up circuit is connected to the power supply VDD; The first output end of the insurance circuit is connected to the power supply VDD, the VF port of the insurance circuit is connected to the power supply VDD through an insurance line, the ground terminal of the insurance circuit is grounded; the input end of the alarm circuit is connected to the power supply VDD connected, the ground terminal of the alarm circuit is grounded.

As shown in Figure 2, the wake-up circuit includes a voltage detection chip VD1, the output end of the voltage detection chip VD1 is connected to the power supply through a resistor R1, and the VT output end of the voltage detection chip VD1 is also connected to one end of the AND gate AND input connection, the rectifying antenna is connected to the input end of the voltage detection chip VD1. When there is no need for reading and writing, the output VT of the wake-up circuit is high level. When the RFID reader needs to read and write the RFID tag, the output VT of the wake-up circuit is converted from high level to low level, and the output of the AND gate AND is connected to the gate of the PMOS transistor MP, thereby turning on the PMOS transistor MP for RFID The chip is powered, so that the RFID chip starts to work normally.

As shown in Figure 3, the insurance circuit includes a voltage detection chip VD2, the output end of the voltage detection chip VD2 is connected to the VA end, and the output end of the voltage detection chip VD2 is also connected to the power supply VDD via a pull-up resistor R2, The output end of the voltage detection chip VD2 is connected to the drain of the PMOS transistor M3, the source of the PMOS transistor M3 is connected to the power supply VDD, the gate of the PMOS transistor M3 is connected to the protection line through the resistor R3, and the PMOS transistor M3 The gate of the tube M3 is grounded through the resistor R4, and the ground terminal of the voltage detection chip VD2 is grounded. In normal state, the output signal VA of this circuit is high level. When the insurance line is cut off, the VF port is disconnected from VDD, the output VA port of the insurance circuit is converted from high level to low level, after the VA port is ANDed, the MP is turned on, and the RFID chip starts to work; at the same time, the VA port enables the RFID to pass The communication antenna sends out the alarm data to trigger the alarm device.

As shown in FIG. 4, the alarm circuit includes a resistor R5, an inductor L1, a capacitor C1, an NMOS transistor M4, an inductor L2, and an NMOS transistor M5. One end of the parallel connection of the resistor R5, the inductor L1, and the capacitor C1 is connected to the power supply VDD. The other end is connected to the drain of the NMOS transistor M4, the source of the NMOS transistor M4 is connected to the drain of the NMOS transistor M5, the gate of the NMOS transistor M4 is grounded through the inductor L2, and the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5. The VAD port is connected, and the source of the NMOS transistor M5 is grounded. If the alarm release signal VAD of the RFID chip does not release the alarm, when the tag passes through the area equipped with magnetic induction equipment, it will generate internal resonance and trigger the alarm device. RFID is a standard active RFID tag, where VA is its input signal, which is used as an enabling signal for triggering an alarm as a safety line; VAD is an output signal, which is used as an enabling signal for disabling an alarm circuit.

The rectifying antenna is connected to the wake-up circuit. When there is no RFID reader signal, the input terminal Vin of the wake-up circuit is at a low level, and the VT terminal of the wake-up circuit inputs an AND gate and outputs a high level, and the PMOS transistor MP is turned off. The RFID chip is in a power-off state and does not consume any current; when the goods need to be settled, the signal from the RFID reader increases the output voltage of the rectenna, and when the voltage is higher than the threshold set in the wake-up circuit, the wake-up circuit The output VT is low level, so that the AND gate AND outputs a low level, and then MP is turned on, the RFID chip is in a working state, and normal read and write communication is performed. When the safety line of the insurance label is cut off, the output VA of the insurance circuit outputs a low level, so that the AND gate AND outputs a low level, the PMOS tube MP is turned on, and the RFID is in a working state, and the RFID chip sends an alarm data through the communication antenna at the same time. Start the alarm. If the insurance line is intact but has not been settled normally, the built-in passive alarm circuit will trigger the alarm when the RFID tag leaves the store. When there is no need for communication, the output of the wake-up circuit and the insurance circuit are at high level at the same time, and the output of the AND gate is at a high level, so that the PMOS transistor MP is in the off state, the RFID chip is disconnected from the power supply, and the label system is in a completely off state , does not consume any static power.

Example 2:

The model of the RFID chip can also be MLX90129, ATA5577C, TRF7970A, ST25DVxxx12-pin or PN7150. The pins of the RFID chip have at least one digital input and two digital outputs, so as to be electrically connected with the insurance circuit and the alarm circuit.

Example 3:

As shown in Figure 5, the voltage detection chip VD1 includes a high-voltage monitoring circuit, a medium-voltage monitoring circuit and a low-voltage detection circuit, the VO output terminal of the high-voltage monitoring circuit is connected to the control terminal of the medium-voltage monitoring circuit, and the medium-voltage monitoring circuit The VIN output terminal of the circuit is connected to the monitoring terminal of the low-voltage monitoring circuit, the VO output terminal of the medium-voltage monitoring circuit is connected to the control terminal of the low-voltage monitoring circuit, the open-drain output terminal VOD1 of the high-voltage monitoring circuit, and the medium-voltage monitoring circuit The open-drain output terminal VOD2 of the circuit and the open-drain output terminal VOD3 of the low-voltage monitoring circuit are all connected to the VOD end, and the input terminal of the high-voltage monitoring circuit and the input terminal of the medium-voltage monitoring circuit are all connected to the VIN end of the monitoring object. The ground terminals of the high-voltage monitoring circuit, the medium-voltage monitoring circuit and the low-voltage monitoring circuit are all grounded.

As shown in FIG. 6, the high-voltage monitoring circuit 1 includes PMOS-Q1 and the first capacitor 102 are connected to each other, and the VIN of the monitored object is connected to the source of PMOS-Q1, and the drain of PMOS-Q1 is connected to the first capacitor 102 at VC3. connected, the other end of the first capacitor 102 is grounded, VC3 is used as the power supply of the inverter 103, the ground level of the inverter 103 is connected to the anode of the diode D1 at Vd, the input of the inverter 103 is VIN, and the output is VB3, the cathode of diode D1 is grounded; VB3 is connected to the gate of NMOS-Q2 and PMOS-Q3, the source of NMOS-Q2 is grounded, the source of PMOS-Q3 is connected to VIN, and the drain of NMOS-Q2 and PMOS-Q3 Connect the output VO(H), where VO(H) is also connected to the gate of NMOS-Q4, the source of NMOS-Q4 is grounded, the drain of NMOS-Q4 is an open-drain output terminal and outputs VOD1; where PMOS-Q1 is a thin Gate high-voltage devices, NMOS-Q2 is a medium-gate high-voltage device, and PMOS-Q3 and NMOS-Q4 are both thick-gate high-voltage devices.

As shown in Figure 7, the medium voltage monitoring circuit 2 includes a first gating switch 201, the source of the first gating switch 201 is connected to the VIN of the monitored object, and the gate of the first gating switch 201 is connected to the VIN of the high voltage monitoring circuit 1. The output signal VO (H) is connected, and the drain of the first gating switch 201 is the output medium voltage monitoring circuit power supply VIN (M); the source of the PMOS-Q5 is connected to VIN (M), and the drain is connected to the second capacitor 203 at VC2 place is connected, and the other end of the second capacitor 203 is grounded; the input of the first selector 104 is VC2 and the ground wire, and the selection control signals of the first selector 104 are respectively VIN (M) and VO (M), and the first selection The output of device 104 is VB2; VB2 is connected with the gate of PMOS-Q6 and NMOS-Q7, the source of PMOS-Q6 is grounded, the source of NMOS-Q7 is connected with VIN (M), and the gate of PMOS-Q6 and NMOS-Q7 The drain is connected to the first buffer 207; the first buffer 207 outputs VO(M), VO(M) is connected to the gate of NMOS-Q8, the source of NMOS-Q8 is grounded, and the drain of NMOS-Q8 Extremely open-drain output VOD2 of medium voltage supervisory circuit 2. The first gating switch 201 is a middle-gate high-voltage device, PMOS-Q5, the first selector, PMOS-Q6, NMOS-Q7 and the first buffer are thin-gate low-voltage devices, and NMOS-Q8 is a thin-gate high-voltage device.

As shown in Figure 8, the low-voltage monitoring circuit 3 includes a second gating switch 301, the source of the second gating switch 301 is connected to the output VIN (M) of the medium-voltage monitoring circuit, and the gate is connected to the output VO of the medium-voltage monitoring circuit. (M) connection, the drain is the low-voltage monitoring circuit power supply VIN (L); the source of PMOS-Q9 is connected to VIN (L), the drain of PMOS-Q9 is connected to the third capacitor 303 at VC1, and the third capacitor 303 The other end of the second selector 304 is grounded; the input of the second selector 304 is VC1 and ground, the selection control signals of the second selector 304 are respectively VIN (L) and VO (L), and the output of the second selector 304 is VB1; VB1 It is connected to the gate of NMOS-Q10 and PMOS-Q11, the source of NMOS-Q10 is grounded, the source of PMOS-Q11 is connected to VIN(L), and the drain of NMOS-Q10 and PMOS-Q11 passes through the second buffer 307 Then output VO(L), VO(L) is connected to the gate of NMOS-Q12, the source of NMOS-Q12 is grounded, and the drain of NMOS-Q12 is an open-drain output VOD3. The second gating switch is a thin-gate high-voltage device, PMOS-Q9, the second selector, NMOS-Q10, PMOS-Q11 and the second buffer are all thin-gate low-voltage devices, and NMOS-Q12 is a thin-gate high-voltage device.

The above-mentioned embodiments only express the specific implementation manners of the utility model, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the patent scope of the utility model. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims (6)

1. a kind of low-power consumption burglar alarm RFID label tag, which is characterized in that including RFID chip, the Vin2 of the RFID chip is defeated Enter end and be connected with communication antenna, the end VP of the RFID chip is connect with the drain electrode of PMOS tube MP, the end VA of the RFID chip It is connect with the end VA of insurance circuit, the end VAD of the RFID chip and the end VAD of warning circuit connect, the RFID chip Ground terminal ground connection；

It the grid of the PMOS tube MP and is connect with the output end of door AND, the source electrode of the PMOS tube MP is connect with power vd D； The end VT with the first input end of door AND and wake-up circuit is connect, second input terminal and insurance circuit with door AND The end VA connection；The end Vin1 of the wake-up circuit is connect with RECTIFYING ANTENNA, the ground terminal ground connection of the wake-up circuit, described to call out The power input of awake circuit is connect with power vd D；First output end of the insurance circuit is connect with power vd D, the guarantor The port VF of dangerous circuit is connect by fuze with power vd D, the ground terminal ground connection of the insurance circuit；The warning circuit Input terminal is connect with the power vd D, and the ground terminal ground connection of the warning circuit, the electric connection of the fuze is broken It can cause the connection of warning circuit, then cause warning device and issue alarm signal.

2. a kind of low-power consumption burglar alarm RFID label tag according to claim 1, which is characterized in that the wake-up circuit packet Voltage checking chip VD1 is included, is connected to power supply on the output end of the voltage checking chip VD1 through resistance R1, the voltage inspection It surveys the VT output end of chip VD1 and also and with one end of door AND inputs connection, connect on the input terminal of the voltage checking chip VD1 It is connected to RECTIFYING ANTENNA.

3. a kind of low-power consumption burglar alarm RFID label tag according to claim 1, which is characterized in that the insurance circuit packet Voltage checking chip VD2 is included, the output end of the voltage checking chip VD2 is connect with the end VA, the voltage checking chip VD2's Output end is also connect through pull-up resistor R2 with power vd D, the drain electrode of the output end and PMOS tube M3 of the voltage checking chip VD2 Connection, the source electrode of the PMOS tube M3 are connect with power vd D, and the grid of the PMOS tube M3 is connect through resistance R3 with protective wire, The grid of the PMOS tube M3 is grounded through resistance R4, the ground terminal ground connection of the voltage checking chip VD2.

4. a kind of low-power consumption burglar alarm RFID label tag according to claim 1, which is characterized in that the warning circuit packet Include resistance R5, inductance L1, capacitor C1, NMOS tube M4, inductance L2 and NMOS tube M5, the resistance R5, inductance L1, capacitor C1 parallel connection One end afterwards is connect with power vd D, and the other end is connect with the drain electrode of NMOS tube M4, the source electrode and NMOS tube M5 of the NMOS tube M4 Drain electrode connection, the grid of the NMOS tube M4 is grounded through inductance L2, and the grid of the NMOS tube M5 is connect with the port VAD, institute State the source electrode ground connection of NMOS tube M5.

5. a kind of low-power consumption burglar alarm RFID label tag according to claim 2, which is characterized in that the voltage detecting core Piece VD1 includes high pressure monitoring circuit, middle pressure monitoring circuit and low-voltage testing circuit, the VO output end of the high pressure monitoring circuit and The control terminal connection of middle pressure monitoring circuit, medium pressure monitor the monitoring of the VIN output end and low pressure monitoring circuit of circuit The VO output end of end connection, medium pressure monitoring circuit is connect with the control terminal of low pressure monitoring circuit, and the high pressure monitors circuit Open drain output VOD1, it is middle pressure monitoring circuit open drain output VOD2 and low pressure monitoring circuit open drain output VOD3 it is equal Connect with the end VOD, the input terminal of the input terminal of high pressure monitoring circuit and middle pressure monitoring circuit with the end VIN of monitored object The ground terminal of connection, the high pressure monitoring circuit, middle pressure monitoring circuit and low pressure monitoring circuit is grounded.

6. a kind of low-power consumption burglar alarm RFID label tag according to claim 3, which is characterized in that the voltage detecting core Piece VD2 is identical with the circuit connection of voltage checking chip VD1.