CN209515664U - A kind of package assembling based on four metal-oxide-semiconductor chips - Google Patents
A kind of package assembling based on four metal-oxide-semiconductor chips Download PDFInfo
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- CN209515664U CN209515664U CN201920345652.7U CN201920345652U CN209515664U CN 209515664 U CN209515664 U CN 209515664U CN 201920345652 U CN201920345652 U CN 201920345652U CN 209515664 U CN209515664 U CN 209515664U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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Abstract
The utility model belongs to chip encapsulation technology field, mainly provide a kind of package assembling based on four metal-oxide-semiconductor chips, package assembling includes substrate, the first electrode set on substrate surface and sequentially arranged, second electrode, first Ji Dao, second Ji Dao, third Ji Dao and the 4th Ji Dao, the first metal-oxide-semiconductor chip set on the first surface Ji Dao, the second metal-oxide-semiconductor chip set on the second surface Ji Dao, third metal-oxide-semiconductor chip set on the surface third Ji Dao, the 4th metal-oxide-semiconductor chip set on the 4th surface Ji Dao, and it is equipped with first grid pin, second grid pin, third gate lead, the packaging body of 4th gate lead, to which four metal-oxide-semiconductor chips are merged encapsulation, reduce the area for occupying printed circuit board, reduce the electromagnetic interference between circuit, increase radiating efficiency, so that pin with Printed circuit board has bigger contact area.
Description
Technical field
The utility model belongs to chip encapsulation technology field more particularly to a kind of encapsulation group based on four metal-oxide-semiconductor chips
Part.
Background technique
Currently, chip package in the market is usually single-chip package or dual chip encapsulation, when needing to carry out in circuit
When multiple chips are applied in combination, multiple chips use simultaneously, which will increase, occupies PCB (Printed Circuit Board, printing electricity
Road plate) area, and can due to circuit loop increase and cause EMI (Electro Magnetic Interference, electricity
Magnetic disturbance) increase, chip failure hidden danger increases, it would therefore be highly desirable to a kind of structure for merging encapsulation based on four metal-oxide-semiconductor chips
And routing method.
Utility model content
The utility model provides a kind of package assembling based on four metal-oxide-semiconductor chips, it is intended to solve existing multiple chips
Simultaneously using will increase the area for occupying printed circuit board the problem of.
The utility model proposes a kind of package assembling based on four metal-oxide-semiconductor chips, the package assembling includes:
Substrate；
First electrode, the second electrode, the first Ji Dao, the second Ji Dao, third Ji Dao set on substrate surface and sequentially arranged
And the 4th Ji Dao；
The first metal-oxide-semiconductor chip set on the surface first Ji Dao, the drain electrode of the first metal-oxide-semiconductor chip and described first
Ji Dao is electrically connected；
The second metal-oxide-semiconductor chip set on the surface second Ji Dao, the drain electrode of the second metal-oxide-semiconductor chip and described second
Ji Dao is electrically connected；
Third metal-oxide-semiconductor chip set on the surface the third Ji Dao, the drain electrode and the third of the third metal-oxide-semiconductor chip
Ji Dao is electrically connected；
The 4th metal-oxide-semiconductor chip set on the 4th surface Ji Dao, the drain electrode and the described 4th of the 4th metal-oxide-semiconductor chip
Ji Dao is electrically connected；And
For to the substrate, the first electrode, the second electrode, first Ji Dao, second Ji Dao, institute
State third Ji Dao, the 4th Ji Dao, the first metal-oxide-semiconductor chip, the second metal-oxide-semiconductor chip, the third metal-oxide-semiconductor chip
And the packaging body that the 4th metal-oxide-semiconductor chip is packaged, and the packaging body is equipped with first grid pin, second grid
Pin, third gate lead, the 4th gate lead；
Wherein, the source electrode of the first metal-oxide-semiconductor chip is connect with the first electrode, the grid of the first metal-oxide-semiconductor chip
Pole is connect with the first grid pin, and the drain electrode of the first metal-oxide-semiconductor chip connects with the source electrode of the second metal-oxide-semiconductor chip
It connects, the grid of the second metal-oxide-semiconductor chip is connect with the second grid pin, the grid of the 4th metal-oxide-semiconductor chip and institute
The connection of the 4th gate lead is stated, the source electrode of the 4th metal-oxide-semiconductor chip is connect with the second electrode, the 4th metal-oxide-semiconductor core
The drain electrode of piece is connect with the source electrode of the third metal-oxide-semiconductor chip, and the grid of the third metal-oxide-semiconductor chip draws with the third grid
Foot connection.
Optionally, the first electrode is set to the first side of the substrate, and the second electrode is set to the of the substrate
Two sides, the first electrode and second electrode opposition are arranged.
Optionally, the shape of the packaging body is polygon.
Optionally, the polygon includes square or rectangle.
Optionally, the drain electrode of the first metal-oxide-semiconductor chip is bonded by conducting resinl with first Ji Dao, and described second
The drain electrode of metal-oxide-semiconductor chip is bonded by conducting resinl with second Ji Dao.
Optionally, the drain electrode of the third metal-oxide-semiconductor chip is bonded by conducting resinl with the third Ji Dao, and the described 4th
The drain electrode of metal-oxide-semiconductor chip is bonded by conducting resinl with the 4th Ji Dao.
Optionally, the packaging body is Plastic Package.
Optionally, the first metal-oxide-semiconductor chip is N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip, second metal-oxide-semiconductor
Chip is that perhaps the p-type metal-oxide-semiconductor chip third metal-oxide-semiconductor chip is N-type metal-oxide-semiconductor chip or p-type MOS to N-type metal-oxide-semiconductor chip
Tube chip, the 4th metal-oxide-semiconductor chip are N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip.
Optionally, the first electrode, the second electrode, first Ji Dao, second Ji Dao, the third base
Island and the 4th Ji Dao are metal copper sheet.
Optionally, the source electrode of the second metal-oxide-semiconductor chip is connect by conducting wire with first Ji Dao, the 3rd MOS
The source electrode of tube chip is connect by conducting wire with the 4th Ji Dao.
In a kind of package assembling based on four metal-oxide-semiconductor chips provided by the embodiment of the utility model, the encapsulation group
Part includes substrate, first electrode, the second electrode, the first Ji Dao, the second Ji Dao, third base set on substrate surface and sequentially arranged
Island and the 4th Ji Dao, the first metal-oxide-semiconductor chip set on the surface first Ji Dao, set on the second of the surface second Ji Dao
Metal-oxide-semiconductor chip, the third metal-oxide-semiconductor chip set on the surface the third Ji Dao, the 4th metal-oxide-semiconductor set on the 4th surface Ji Dao
Chip, for encapsulating the substrate, the first electrode, the second electrode, first Ji Dao, second Ji Dao, institute
State third Ji Dao, the 4th Ji Dao, the first metal-oxide-semiconductor chip, the second metal-oxide-semiconductor chip, the third metal-oxide-semiconductor chip
And the packaging body of the 4th metal-oxide-semiconductor chip reduces chip cost so that four metal-oxide-semiconductor chips are merged encapsulation,
The area for occupying printed circuit board is reduced, the electromagnetic interference between circuit is reduced, increases radiating efficiency, so that pin and print
Printed circuit board has bigger contact area, solves existing multiple chips while using the face that will increase occupancy printed circuit board
Product, and can due to circuit loop increase and cause electromagnetic interference to increase, chip failure hidden danger increase the problem of.
Detailed description of the invention
Fig. 1 is that the structure for the package assembling based on four metal-oxide-semiconductor chips that one embodiment of the utility model provides is shown
It is intended to；
Fig. 2 is the structure for the package assembling based on four metal-oxide-semiconductor chips that another embodiment of the utility model provides
Schematic diagram.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.Meanwhile term " first ", " second " in the description of the present invention,
It is described etc. being only used for distinguishing, is not understood to indicate or imply relative importance.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " instruction is described special
Sign, entirety, step, operation, the presence of element and/or component, but be not precluded one or more of the other feature, entirety, step,
Operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this present specification merely for the sake of description specific embodiment
And be not intended to limit the application.As present specification and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in present specification and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
In order to illustrate the above-mentioned technical solution of the application, the following is a description of specific embodiments.
Fig. 1 be the utility model proposes the package assembling based on four metal-oxide-semiconductor chips structural schematic diagram, such as Fig. 1 institute
Show, the package assembling includes:
Substrate 100；
First electrode S1, second electrode S4, the first base island D1, the second Ji Dao set on 100 surface of substrate and sequentially to arrange
D2, third base island D3 and the 4th base island D4；
The first metal-oxide-semiconductor chip M1 set on first base island surface D1, the drain electrode of the first metal-oxide-semiconductor chip M1 and institute
State the first base island D1 electric connection；
The second metal-oxide-semiconductor chip M2 set on second base island surface D2, the drain electrode of the second metal-oxide-semiconductor chip M2 and institute
State the second base island D2 electric connection；
Third metal-oxide-semiconductor chip M3 set on the third base island surface D3, the drain electrode of the third metal-oxide-semiconductor chip M3 and institute
State third base island D3 electric connection；
The 4th metal-oxide-semiconductor chip set on the 4th base island surface D4, the drain electrode of the 4th metal-oxide-semiconductor chip and described the
Four base island D4 are electrically connected；And
For to the substrate 100, the first electrode S1, the second electrode S4, first base island D1, described
Diyl island D2, third base island D3, the 4th base island D4, the first metal-oxide-semiconductor chip M1, the second metal-oxide-semiconductor chip
The packaging body 101 that M2, the third metal-oxide-semiconductor chip M3 and the 4th metal-oxide-semiconductor chip M4 are packaged, and the encapsulation
Body 101 is equipped with first grid pin G1, second grid pin G2, third gate lead G3, the 4th gate lead G4；
Wherein, the source electrode of the first metal-oxide-semiconductor chip M1 and the first electrode S1 are electrically connected, first metal-oxide-semiconductor
The grid of chip M1 and the first grid pin G1 are electrically connected, the drain electrode and described second of the first metal-oxide-semiconductor chip M1
The source electrode of metal-oxide-semiconductor chip M2 is electrically connected, and the grid of the second metal-oxide-semiconductor chip M2 electrically connects with the second grid pin G2
It connects, the grid and the 4th gate lead G4 of the 4th metal-oxide-semiconductor chip M4 is electrically connected, the 4th metal-oxide-semiconductor chip M4
Source electrode and the second electrode S4 be electrically connected, the drain electrode of the 4th metal-oxide-semiconductor chip M4 and the third metal-oxide-semiconductor chip M3
Source electrode be electrically connected, the grid of the third metal-oxide-semiconductor chip M3 and the third gate lead G3 are electrically connected.
In the present embodiment, the drain electrode of the first metal-oxide-semiconductor chip M1 and the first base island D1 are electrically connected, therefore, in the application,
The drain electrode to the first metal-oxide-semiconductor chip M1 may be implemented by the first exposed base island D1 and carry out signal transmission；First electrode S1 with
The source electrode of first metal-oxide-semiconductor chip M1 is electrically connected, and therefore, in the application, can be realized by exposed first electrode S1 to the
The source electrode of one metal-oxide-semiconductor chip carries out signal transmission.
In the present embodiment, the drain electrode of the 4th metal-oxide-semiconductor chip M4 and the 4th base island D4 are electrically connected, therefore, in the application,
Signal transmission can be carried out by the drain electrode of exposed the 4th base island D4 and the 4th metal-oxide-semiconductor chip M4.
In one embodiment, the first electrode S1, the second electrode S4, first base island D1, described second
Base island D2, third base island D3, the 4th base island D4 are exposed to the outside of the packaging body 101, wherein first electricity
The first electrode exposed region of pole S1 being exposed to outside packaging body 101 is described for the first source lead as package assembling
Second electrode S4 is exposed to the second electrode exposed region outside packaging body 101 for the 4th source lead as package assembling,
First base island D1 is exposed to the first base island exposed region outside packaging body 101 for the first drain lead as package assembling,
Second base island D2 is exposed to the second base island exposed region outside packaging body 101 for the second drain lead as package assembling,
Third base island D3 is exposed to the third base island exposed region outside packaging body 101 for third drain lead as package assembling,
4th base island D4 is exposed to the 4th base island exposed region outside packaging body 101 for the 4th drain lead as package assembling.
Fig. 2 is the structure for the package assembling based on four metal-oxide-semiconductor chips that another embodiment of the utility model proposes
Schematic diagram, as shown in Fig. 2, for clarity to the substrate 100, the first electrode S1, the second electrode S4, described
One base island D1, second base island D2, third base island D3, the 4th base island D4, the first metal-oxide-semiconductor chip M1, institute
The position for stating the second metal-oxide-semiconductor chip M2, the third metal-oxide-semiconductor chip M3 and the 4th metal-oxide-semiconductor chip M4 is illustrated, this
The packaging body 101 that package assembling in embodiment uses include 1 be sequentially disposed on the frame of substrate 100,2,3,4,5,6,7,
8、9、10、11、12、13、14、15、16、17、18、19、20、21、22、23、24、25、26、27、28、29、30、31、32、33、
34,35,36,37,38,39,40 etc. 40 pins, wherein pin 1, pin 2, pin 3, pin 4 and pin 5 are with first
Electrode S1 is electrically connected, and the bottom of the first metal-oxide-semiconductor chip M1 is the drain electrode of the first metal-oxide-semiconductor chip M1, and is pasted with the first base island D1
It closes；Pin 6 and the first base island D1 are electrically connected, and pin 7, pin 8, pin 9 and pin 10 and the second base island D2 are electrically connected,
The bottom of second metal-oxide-semiconductor chip M2 is the drain electrode of the second metal-oxide-semiconductor chip M2, and is bonded with the second base island D2, the second metal-oxide-semiconductor chip
The grid of M2 and second grid G2 are electrically connected, and second grid G2 can be pin 11, pin 12, pin 13, pin 14 and
Pin 15 and the second base island D2 are electrically connected；The bottom of third metal-oxide-semiconductor chip M3 is the bottom of third metal-oxide-semiconductor chip M3, and with
Third base island D3 fitting, the grid and third grid G 3 of third metal-oxide-semiconductor chip M3 are electrically connected, and third grid can be pin
16, pin 17, pin 18, pin 19, pin 20, pin 21, pin 22, pin 23 and pin 24 and third base island D3 are electrical
Connection；The bottom of 4th metal-oxide-semiconductor chip M4 is the drain electrode of the 4th metal-oxide-semiconductor chip M4, and is bonded with the 4th base island D4, wherein pipe
Foot 25 and the 4th base island D4 are electrically connected, pin 26, pin 27, pin 28, pin 29 and pin 30 and second electrode S4 electricity
Property connection, pin 31, pin 32, pin 33 and pin 34 and the 4th base island D4 electric connection, the grid of the 4th metal-oxide-semiconductor chip M4
Pole is connect with the 4th grid G 4, and the 4th grid G 4 can be pin 35；Grid and first grid the G1 electricity of first metal-oxide-semiconductor chip M1
Property connection, first grid G1 can be pin 36, pin 37, pin 38, pin 39 and pin 40 and the first base island D1 electrical property
Connection.
In one embodiment, the source electrode of the second metal-oxide-semiconductor chip M2 and the first area D11 of the first base island D1 electrically connect
It connects.
In one embodiment, the source electrode of third metal-oxide-semiconductor chip M3 and the first area D41 of the 4th base island D4 electrically connect
It connects.
In one embodiment, the first electrode S1 is set to the first side of the substrate 100, and the second electrode S4 is set
In second side of the substrate 100, the first electrode S1 and second electrode S4 opposition are arranged.
In one embodiment, the shape of the packaging body 101 is polygon.
In one embodiment, the polygon in the present embodiment includes square or rectangle.
In one embodiment, the drain electrode of the first metal-oxide-semiconductor chip M1 is pasted by conducting resinl and first base island D1
It closes, the drain electrode of the second metal-oxide-semiconductor chip M2 is bonded by conducting resinl with second base island D2.
In one embodiment, the drain electrode of the third metal-oxide-semiconductor chip M3 is pasted by conducting resinl and third base island D3
It closes, the drain electrode of the 4th metal-oxide-semiconductor chip M4 is bonded by conducting resinl with the 4th base island D4.
In one embodiment, the packaging body 101 is Plastic Package.Packaging body 101 i.e. in the present embodiment can be adopted
Polygon made of being encapsulated with plastic-sealed body includes square or rectangle package body structure.
In one embodiment, the first metal-oxide-semiconductor chip M1 be N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip, it is described
Second metal-oxide-semiconductor chip M2 is N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip, and the third metal-oxide-semiconductor chip M3 is N-type metal-oxide-semiconductor core
Perhaps p-type metal-oxide-semiconductor chip the 4th metal-oxide-semiconductor chip M4 is N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip to piece.
In one embodiment, the first electrode S1, the second electrode S4, first base island D1, described second
Base island D2, third base island D3 and the 4th base island D4 are metal copper sheet.
In one embodiment, the source electrode of the second metal-oxide-semiconductor chip M2 is connect by conducting wire with first base island D1.
In one embodiment, the source electrode of the third metal-oxide-semiconductor chip M3 is connect by conducting wire with the 4th base island D4.
In a kind of package assembling based on four metal-oxide-semiconductor chips provided by the embodiment of the utility model, the encapsulation group
Part include surface be equipped with first electrode, second electrode, the first Ji Dao, the second Ji Dao, third Ji Dao and the 4th Ji Dao substrate,
The first metal-oxide-semiconductor chip set on the surface first Ji Dao, the second metal-oxide-semiconductor chip set on the surface second Ji Dao, is set to
The third metal-oxide-semiconductor chip on the surface the third Ji Dao, the 4th metal-oxide-semiconductor chip set on the 4th surface Ji Dao, for encapsulating
The substrate, the first electrode, the second electrode, first Ji Dao, second Ji Dao, the third Ji Dao, institute
State the 4th Ji Dao, the first metal-oxide-semiconductor chip, the second metal-oxide-semiconductor chip, the third metal-oxide-semiconductor chip and the described 4th
The packaging body of metal-oxide-semiconductor chip, wherein the first electrode, the second electrode, first Ji Dao, second Ji Dao, institute
State third Ji Dao, the 4th Ji Dao is exposed to the packaging body, so that four metal-oxide-semiconductor chips are merged encapsulation, reduce
Chip cost reduces the area for occupying printed circuit board, reduces the electromagnetic interference between circuit, increase radiating efficiency,
So that pin and printed circuit board have bigger contact area, solves existing multiple chips while use will increase occupancy print
The area of printed circuit board, and electromagnetic interference can be caused to increase since circuit loop increases, what chip failure hidden danger increased asks
Topic.
Embodiment described above, the only specific embodiment of the application, but the protection scope of the application is not limited to
This, anyone skilled in the art within the technical scope of the present application, can easily think of the change or the replacement,
Should all it cover within the scope of protection of this application.Therefore, the protection scope of the application answers the protection model with claim
Subject to enclosing.
Claims (10)
1. a kind of package assembling based on four metal-oxide-semiconductor chips, which is characterized in that the package assembling includes:
Substrate；
The first electrode set on substrate surface and sequentially arranged, second electrode, the first Ji Dao, the second Ji Dao, third Ji Dao and
4th Ji Dao；
The first metal-oxide-semiconductor chip set on the surface first Ji Dao, the drain electrode of the first metal-oxide-semiconductor chip and first Ji Dao
It is electrically connected；
The second metal-oxide-semiconductor chip set on the surface second Ji Dao, the drain electrode of the second metal-oxide-semiconductor chip and second Ji Dao
It is electrically connected；
Third metal-oxide-semiconductor chip set on the surface the third Ji Dao, the drain electrode of the third metal-oxide-semiconductor chip and the third Ji Dao
It is electrically connected；
The 4th metal-oxide-semiconductor chip set on the 4th surface Ji Dao, the drain electrode of the 4th metal-oxide-semiconductor chip and the 4th Ji Dao
It is electrically connected；And
For to the substrate, the first electrode, the second electrode, first Ji Dao, second Ji Dao, described
Three Ji Dao, the 4th Ji Dao, the first metal-oxide-semiconductor chip, the second metal-oxide-semiconductor chip, the third metal-oxide-semiconductor chip and
The packaging body that the 4th metal-oxide-semiconductor chip is packaged, the packaging body are equipped with first grid pin, second grid pin, the
Three gate leads, the 4th gate lead；
Wherein, the source electrode of the first metal-oxide-semiconductor chip is connect with the first electrode, the grid of the first metal-oxide-semiconductor chip with
The first grid pin connection, the drain electrode of the first metal-oxide-semiconductor chip are connect with the source electrode of the second metal-oxide-semiconductor chip, institute
The grid for stating the second metal-oxide-semiconductor chip is connect with the second grid pin, the grid and the described 4th of the 4th metal-oxide-semiconductor chip
Gate lead connection, the source electrode of the 4th metal-oxide-semiconductor chip are connect with the second electrode, the leakage of the 4th metal-oxide-semiconductor chip
Pole is connect with the source electrode of the third metal-oxide-semiconductor chip, and the grid of the third metal-oxide-semiconductor chip and the third gate lead connect
It connects.
2. package assembling as described in claim 1, which is characterized in that the first electrode is set to the first side of the substrate,
The second electrode is set to second side of the substrate, and the first electrode and second electrode opposition are arranged.
3. package assembling as described in claim 1, which is characterized in that the shape of the packaging body is polygon.
4. package assembling as claimed in claim 3, which is characterized in that the polygon includes square or rectangle.
5. package assembling as described in claim 1, which is characterized in that the drain electrode of the first metal-oxide-semiconductor chip passes through conducting resinl
It is bonded with first Ji Dao, the drain electrode of the second metal-oxide-semiconductor chip is bonded by conducting resinl with second Ji Dao.
6. package assembling as described in claim 1, which is characterized in that the drain electrode of the third metal-oxide-semiconductor chip passes through conducting resinl
It is bonded with the third Ji Dao, the drain electrode of the 4th metal-oxide-semiconductor chip is bonded by conducting resinl with the 4th Ji Dao.
7. package assembling as described in claim 1, which is characterized in that the packaging body is Plastic Package.
8. package assembling as described in claim 1, which is characterized in that the first metal-oxide-semiconductor chip be N-type metal-oxide-semiconductor chip or
Person's p-type metal-oxide-semiconductor chip, the second metal-oxide-semiconductor chip are N-type metal-oxide-semiconductor chip or p-type metal-oxide-semiconductor chip, the third metal-oxide-semiconductor
Chip is that perhaps p-type metal-oxide-semiconductor chip the 4th metal-oxide-semiconductor chip is N-type metal-oxide-semiconductor chip or p-type MOS to N-type metal-oxide-semiconductor chip
Tube chip.
9. package assembling as described in claim 1, which is characterized in that the first electrode, the second electrode, described first
Ji Dao, second Ji Dao, the third Ji Dao and the 4th Ji Dao are metal copper sheet.
10. package assembling as described in claim 1, which is characterized in that the source electrode of the second metal-oxide-semiconductor chip by conducting wire with
The source electrode of the first Ji Dao connection, the third metal-oxide-semiconductor chip is connect by conducting wire with the 4th Ji Dao.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920345652.7U CN209515664U (en) | 2019-03-18 | 2019-03-18 | A kind of package assembling based on four metal-oxide-semiconductor chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920345652.7U CN209515664U (en) | 2019-03-18 | 2019-03-18 | A kind of package assembling based on four metal-oxide-semiconductor chips |
Publications (1)
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