CN208572054U - A kind of low-loss delay switch circuit - Google Patents

Abstract

The utility model discloses a kind of low-loss delay switch circuits, including NMOS tube, PMOS tube, diode V2, capacitor C1, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5, the pole S of a foot of resistance R1, the anode of diode V2 and PMOS tube connects VCC_in simultaneously, another foot of resistance R1 connect the pole G of PMOS tube with a foot of resistance R2 simultaneously, the pole D of PMOS tube connects VCC_out, another foot of resistance R2 connects the pole NMOS tube D, and a foot of resistance R5 and the pole NMOS tube S connect power cathode simultaneously；The pole G of resistance R4 connection NMOS tube, another foot of resistance R5, another foot of R4 and mono- foot of R3 connect capacitor C1 simultaneously, and the other foot of capacitor C1 connects power cathode, the cathode of another foot connection diode V2 of resistance R3；The low-loss delay switch circuit greatly reduces the loss of equipment, extends the working time of battery, reduces cost of equipment maintenance.

Description

A kind of low-loss delay switch circuit

Technical field

The utility model relates to delay switch circuit technical fields, and in particular to a kind of low-loss delay switch circuit.

Background technique

Majority accurate delay circuit realizes that delay is precisely controlled using the timer of micro process at present, its advantage is that delay Precision is high, delay time PLC technology, but the disadvantage is that higher cost, chip volume are larger.To not needing the accurate delay time Occasion is generally delayed using RC circuit, and power switch control unit point uses NPN pipe+PNP pipe, NPN pipe+metal-oxide-semiconductor or benchmark Pipe+optocoupler equation, loss is small for milliampere grade either conducting electric current, and for many power supplys, often for upper Electric timing and delay circuit starting voltage requirement are lower, it is lost and has strict demand by size of current single pair, if used Traditional delay circuit is unsatisfactory for above-mentioned requirements, and for low-loss application, low-loss design is particularly important therefore sets Loss can simply be met simultaneously and have very much practical value by the circuit of high current by counting one kind.

In addition, it is as follows with the most similar technic relization scheme of the invention, but all exist certain insufficient:

Utility model patent authorization (a kind of delay switch circuit, application number: CN201721113752.4), circuit is by light Coupling, prover pipe, resistance, capacitor composition, delay component use RC circuit, and RC circuit opens prover pipe when charging to a certain extent, It is then turned on optocoupler, final control signal.This delay switch circuit of shortcoming is only used for normal signal control, can not DC power supply is controlled, there are 1 road DC bias current, it is milliampere grade, optocoupler that prover pipe, which needs to run always operating current, There are minimum working current (milliampere grade), current conversion efficiency and Leakage Current, overall work electric current is milliampere grade.

Utility model patent authorization (switching power circuit and delay switch circuit, application number: CN201521071474.1), Circuit is made of NPN pipe, PNP pipe, resistance, capacitor, and delay component uses RC circuit, the charging of RC circuit, and NPN pipe base voltage is NPN pipe is opened when 0.6V, is then turned on PNP pipe turn-on power.This delay switch circuit of shortcoming can only control normal signal With low current DC power supply, it is unable to control high-current dc power supply (such as ampere grade)；There are (the biasings of NPN pipe DC bias current Resistance be kilohm grade, operating current milliampere grade) and PNP pipe DC bias current (biasing resistor be kilohm grade, operating current Milliampere grade)；Global switch operating current is milliampere grade.

Utility model patent authorization (delay switch circuit, application number: CN201120102609.1), circuit by NPN manage, The composition such as PNP pipe, metal-oxide-semiconductor, diode, voltage-stabiliser tube, resistance, capacitor, key, delay component are used RC circuit, are managed using NPN PNP pipe processed can only control normal signal and low current DC power supply, be unable to control high-current dc power supply (such as ampere grade)；NPN There is biasing resistor (operating current milliampere grade) in pipe, PNP pipe, automatically shut power off when not working suitable for remote controler etc., no It is suitble to high current application.Global switch operating current is milliampere grade.

Utility model patent authorization (delay switch circuit, application number: CN201220543260.X), circuit are managed by NPN, are double The composition such as road metal-oxide-semiconductor, resistance, capacitor, delay component use RC circuit, manage two-way metal-oxide-semiconductor processed using NPN, can control double Road high-current dc power supply (such as ampere grade)；NPN pipe is suitble to high current applied field in biasing resistor (operating current milliampere grade) It closes.Due to dynatron performance, when cut-off, between the pole triode C and the pole E there are when leakage current and work there are dissipated power, (operating current milliampere grade), global switch operating current are milliampere grade.

Utility model content

Purpose of the utility model is to solve defects in the prior art, provide a kind of low-loss delay switch electricity Road solves to be difficult to obtain low-loss technical problem when existing switch control high current.

To achieve the above object, the technical solution of the utility model is as follows:

A kind of low-loss delay switch circuit, including NMOS tube, PMOS tube, diode V2, capacitor C1, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5, the pole S of a foot of the resistance R1, the anode of diode V2 and PMOS tube connect simultaneously VCC_in, another foot of resistance R1 connect the pole G of PMOS tube, the pole the D connection of the PMOS tube with a foot of resistance R2 simultaneously VCC_out, another foot of resistance R2 connect the pole NMOS tube D, and a foot of the resistance R5 and the pole NMOS tube S connect power supply simultaneously Cathode；The pole G of the resistance R4 connection NMOS tube, another foot of the resistance R5, another foot of R4 and mono- foot of R3 connect capacitor simultaneously C1, the other foot of capacitor C1 connect power cathode, the cathode of another foot connection diode V2 of resistance R3.

In order to further realize the utility model, the NMOS tube uses the NMOS tube of model 2N7002.

In order to further realize the utility model, the PMOS tube uses the PMOS tube of model AO3401A.

In order to further realize the utility model, the resistance of the resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5 Value is respectively 1M Ω, 10k Ω, 1M Ω, 100k Ω and 1M Ω.

Beneficial effect

The utility model low-loss delay switch circuit, since metal-oxide-semiconductor belongs to voltage devices, when metal-oxide-semiconductor on and off Its electric current is very small, can be ignored.(NMOS and PMOS are both turned on) current loss is na level when work, and biasing resistor disappears Power consumption stream is microampere order；(NMOS and PMOS are not turned on) current loss is almost 0 when not working, and greatly reduces the damage of equipment Consumption, extends the working time of battery, reduces cost of equipment maintenance, compared with traditional delay switch current loss milliampere grade, Loss reduces greatly, is suitable for Internet of Things NB-IoT low-loss delay switch circuit application, and have very low-cost advantage.

Detailed description of the invention

Fig. 1 is the functional block diagram of the utility model low-loss delay switch circuit.

Specific embodiment

The utility model is further described in detail with reference to the accompanying drawing, these attached drawings are simplified signal Figure, only illustrates the basic structure of the utility model, the direction of this specific implementation is using the direction Fig. 1 as standard in a schematic way.

Embodiment one

As shown in Figure 1, the utility model low-loss delay switch circuit includes NMOS tube, PMOS tube, diode V2, capacitor C1, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5, in which:

The pole S (source electrode) of a foot of resistance R1, the anode of diode V2 and PMOS tube connects VCC_in simultaneously, and resistance R1 is another One foot connect the pole G (grid) of PMOS tube with a foot of resistance R2 simultaneously, and the pole D (drain electrode) of PMOS tube connects VCC_out, resistance Another foot connection pole NMOS tube D (drain electrode) of R2, a foot of resistance R5 and the pole NMOS tube S (source electrode) connect power cathode simultaneously；Electricity The pole G (grid) of R4 connection NMOS tube is hindered, another foot of resistance R5, another foot of R4 and mono- foot of R3 connect capacitor C1, capacitor C1 simultaneously An other foot connects power cathode, the cathode of another foot connection diode V2 of resistance R3.

NMOS tube uses the NMOS tube of model 2N7002, and PMOS tube uses the PMOS tube of model AO3401A, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5 resistance value be respectively 1M Ω, 10k Ω, 1M Ω, 100k Ω and 1M Ω, certainly, Resistance R3, capacitor C1 size can be adjusted according to different delayed time demand；It can be biased according to the different adjustment R1 and R2 of PMOS tube parameter Resistance sizes meet its needs；Its needs can be met according to the different adjustment R4 and R5 biasing resistor sizes of NMOS tube parameter.

Resistance R5 and resistance R4 is the biasing resistor of NMOS tube, and it is microampere order, resistance that NMOS tube biasing resistor, which consumes electric current, R1 is PMOS tube biasing resistor, and it is microampere order that PMOS tube biasing resistor, which consumes electric current,；Voltage between the pole NMOS tube G and the pole S is big In on state threshold voltage (being greater than 0V), when input power VCC_in powers on, VCC_in passes through Schottky diode V2, resistance R3 charges to capacitor C1, and when being greater than NMOS transistor conduction threshold voltage when being charged to certain voltage, NMOS tube D is extremely electric after NMOS conducting Crimp nearly 0V, PMOS tube G pole tension is close to 0V；At the same time, the voltage between the pole PMOS tube G and the pole S is less than conduction threshold electricity It presses (negative value, negative voltage), PMOS tube conducting, VCC_out obtains input power；Due to the electric conduction between the pole PMOS tube D and the pole S Resistance is that tens of milliohms, source current can be several amperes, then the pressure drop for passing through PMOS tube is that (tens of milliohms are multiplied by number for hundred millivolt levels Ampere), the pressure drop of PMOS tube is small, can be approximated to be an ideal power switch.When input power VCC_in is disconnected, NMOS and PMOS are not turned on, current loss 0.

The utility model low-loss delay switch circuit, since metal-oxide-semiconductor belongs to voltage devices, when metal-oxide-semiconductor on and off Its electric current is very small, can be ignored.(NMOS and PMOS are both turned on) current loss is na level when work, and biasing resistor disappears Power consumption stream is microampere order；(NMOS and PMOS are not turned on) current loss is almost 0 when not working, and greatly reduces the damage of equipment Consumption, extends the working time of battery, reduces cost of equipment maintenance, compared with traditional delay switch current loss milliampere grade, Loss reduces greatly, is suitable for Internet of Things NB-IoT low-loss delay switch circuit application, and have very low-cost advantage.

The foregoing is merely the better embodiment of the utility model, the utility model is not limited to above-mentioned embodiment party Formula, there may be the structural modifications that part is small in implementation process, if various changes or modifications to the utility model are not The spirit and scope of the utility model are detached from, and are belonged within the scope of the claims and equivalents of the utility model, then originally Utility model is also intended to encompass these modification and variations.

Claims (4)

1. a kind of low-loss delay switch circuit, which is characterized in that including NMOS tube, PMOS tube, diode V2, capacitor C1, electricity Hinder a foot, the anode of diode V2 and the S of PMOS tube of R1, resistance R2, resistance R3, resistance R4 and resistance R5, the resistance R1 Pole connects VCC_in simultaneously, and another foot of resistance R1 connect the pole G of PMOS tube, the PMOS tube with a foot of resistance R2 simultaneously The pole D connect VCC_out, another foot of the resistance R2 connects the pole NMOS tube D, and a foot and NMOS tube S of the resistance R5 is extremely same When connect power cathode；The pole G of the resistance R4 connection NMOS tube, another foot of the resistance R5, another foot of R4 and mono- foot of R3 are same When connect capacitor C1, the other foot of capacitor C1 connects power cathode, the cathode of another foot connection diode V2 of resistance R3.

2. low-loss delay switch circuit according to claim 1, which is characterized in that the NMOS tube uses model The NMOS tube of 2N7002.

3. low-loss delay switch circuit according to claim 1, which is characterized in that the PMOS tube uses model The PMOS tube of AO3401A.

4. low-loss delay switch circuit according to claim 1, which is characterized in that the resistance R1, resistance R2, resistance The resistance value of R3, resistance R4 and resistance R5 are respectively 1M Ω, 10k Ω, 1M Ω, 100k Ω and 1M Ω.