CN207424482U - Display panel and display device - Google Patents
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- CN207424482U CN207424482U CN201721146767.0U CN201721146767U CN207424482U CN 207424482 U CN207424482 U CN 207424482U CN 201721146767 U CN201721146767 U CN 201721146767U CN 207424482 U CN207424482 U CN 207424482U
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Abstract
The disclosure provides a kind of display panel and display device.The display panel includes：Substrate；The flatness layer being disposed on the substrate；The first electrode being arranged on flatness layer；Luminescent layer on the first electrode is set；Second electrode on the light-emitting layer；With the auxiliary electrode being arranged in flatness layer, the auxiliary electrode is electrically connected with second electrode.By the way that auxiliary electrode is arranged in flatness layer, the area of auxiliary electrode can be made to quite big, so as to significantly reduce the resistance of second electrode.
Description
Technical field
This disclosure relates to display technology field.More specifically, this disclosure relates to a kind of display panel and display device.
Background technology
, it is necessary to use transparent electrode such as transparent cathode in display panel.Transparent electrode is more demanding to the transmitance of light,
Thus the thickness of transparent electrode should be thin as far as possible.But its thinner resistance of transparent electrode film layer is higher, and excessively high resistance
Cause resistance drop (IR drop) occurs in transparent electrode, influence entire display homogeneity.Such case is in large size panel
In it is especially prominent.
Utility model content
Accordingly, it is desirable to provide a kind of display panel and display device, wherein by including auxiliary electrode, can significantly reduce
The resistance of transparent electrode.
In one aspect of the present disclosure, a kind of display panel is provided, including：
Substrate；
Flatness layer, the flatness layer are set on the substrate；
First electrode, the first electrode are arranged on the flatness layer；
Luminescent layer, the luminescent layer are set on the first electrode；
Second electrode, the second electrode are set on the light-emitting layer；With
Auxiliary electrode, the auxiliary electrode are arranged in the flatness layer, and are electrically connected with the second electrode.
According to the disclosure embodiment, the display panel further includes：Pixel defining layer, the pixel defining layer
It is arranged on the flatness layer, and limits pixel region, wherein institute's luminescent layer is formed in the pixel region, wherein described
Auxiliary electrode is electrically connected by being located at the hole in the pixel defining layer and the flatness layer with the second electrode.
According to another embodiment of the disclosure, the flatness layer includes：
First flatness layer and
Second flatness layer,
Wherein, first flatness layer is set on the substrate, and the auxiliary electrode is arranged on first flatness layer
On, and second flatness layer covers the auxiliary electrode and first flatness layer.
According to another embodiment of the disclosure, the display panel further includes：Pixel defining layer, the pixel definition
Layer is arranged on second flatness layer, and limits pixel region, and wherein institute's luminescent layer is formed in the pixel region,
Described in auxiliary electrode be electrically connected by running through the through hole of the pixel defining layer and second flatness layer with the second electrode
It connects.
According to another embodiment of the disclosure, the thickness of first flatness layer is 0.5 μm to 1.5 μm, and institute
The thickness for stating the second flatness layer is 0.5 μm to 1.5 μm.
According to another embodiment of the disclosure, second flatness layer include covering the part of the auxiliary electrode and
It covers and contacts the part of first flatness layer, wherein the covering of second flatness layer and to contact described first flat
The thickness of the part of layer is equal to the sum of the thickness for the part for covering the auxiliary electrode and the thickness of the auxiliary electrode.
According to another embodiment of the disclosure, the thickness of the thickness D1 of the auxiliary electrode and first flatness layer
D2 and second flatness layer cover and contact the ratio between the summation of thickness D3 of part of first flatness layer D1/ (D2+
D3 it is) 1: 10 to 1: 3.
According to another embodiment of the disclosure, the thickness of the auxiliary electrode is 300nm to 750nm；It is and described
The thickness of first flatness layer and second flatness layer cover and contact the total of the thickness of the part of first flatness layer
With for 1 μm to 3 μm.
According to another embodiment of the disclosure, the auxiliary electrode parallel to the area on orientation substrate with it is described
Flatness layer is being 1: 1.2 to 1: 5 parallel to the area ratio on orientation substrate.
According to another embodiment of the disclosure, the auxiliary electrode is mesh electrode.
According to another embodiment of the disclosure, the auxiliary electrode protects conductive layer, conductive gold with including first
Belong to the multilayered structure of layer and the second protection conductive layer, wherein the conductive metal layer is located at the described first protection conductive layer and described
Between second protection conductive layer, the thickness of the first protection conductive layer and the second protection conductive layer is each independently 10
To 100nm, and the thickness of the conductive metal layer is 300 to 500nm.
According to another embodiment of the disclosure, the first electrode is AlNd or Al, and the conductive metal layer is Cu,
And the first protection conductive layer and the second protection conductive layer are MoNb.
According to another embodiment of the disclosure, the first electrode is anode, and the second electrode is cathode.
In another aspect of the disclosure, a kind of display device is provided, including the display surface according to any of the above item
Plate.
According to the disclosure, a kind of display panel can be provided and include the display device of the display panel, wherein described
Display panel includes being arranged on auxiliary electrode in flatness layer, by the way that auxiliary electrode is arranged in flatness layer, and with second
Electrode is electrically connected, and the area of auxiliary electrode can be made to quite big, so as to significantly reduce the resistance of second electrode.
Description of the drawings
In order to illustrate more clearly of the technical solution in the embodiment of the present disclosure, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only the exemplary embodiment of the disclosure, right
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is illustratively to represent that display panel according to an embodiment shows in the section view on orientation substrate
It is intended to.
Fig. 2 is illustratively to represent the display panel according to another embodiment in the section view on orientation substrate
Schematic diagram.
Fig. 3 is illustratively to represent the display panel according to another embodiment of the disclosure perpendicular to orientation substrate
On schematic cross-sectional view.
Fig. 4 is the vertical view of the auxiliary electrode for the display panel for illustratively representing another embodiment according to the disclosure
Schematic diagram.
Fig. 5 is illustratively to represent to form over the passivation layer according to the display panel of another embodiment of the disclosure
In the schematic cross-sectional view on orientation substrate during one flatness layer.
Fig. 6 is illustratively to represent according to the display panel of another embodiment of the disclosure shape on the first flatness layer
Into auxiliary electrode and its it is graphical when in the schematic cross-sectional view on orientation substrate.
Fig. 7 is illustratively represented according to the display panel of another embodiment of the disclosure in the first flatness layer and auxiliary
It helps on electrode when forming the second flatness layer in the schematic cross-sectional view on orientation substrate.
Fig. 8 is illustratively to represent to be formed in the passivation layer according to the display panel of another embodiment of the disclosure
In the schematic cross-sectional view on orientation substrate when through hole is to expose drain electrode.
Fig. 9 is illustratively to represent according to the display panel of another embodiment of the disclosure shape on the second flatness layer
Into first electrode and its it is graphical when in the schematic cross-sectional view on orientation substrate.
Figure 10 is illustratively to represent the display panel according to another embodiment of the disclosure on the second flatness layer
In the schematic cross-sectional view on orientation substrate when forming pixel defining layer.
Figure 11 is illustratively to represent to be limited in pixel defining layer according to the display panel of another embodiment of the disclosure
In the schematic cross-sectional view on orientation substrate when forming luminescent layer in fixed pixel region.
Figure 12 is illustratively to represent the display panel according to another embodiment of the disclosure perpendicular to substrate side
Upward schematic cross-sectional view.
Figure 13 is illustratively to represent the display panel according to the further embodiment of the disclosure perpendicular to substrate side
Upward schematic cross-sectional view.
Specific embodiment
Below in conjunction with the specific embodiment of the disclosure, the technical solution in the embodiment of the present disclosure is carried out clear, complete
Site preparation describes, it is clear that described embodiment and/or embodiment are only a part of embodiment of the disclosure and/or implementation
The embodiment and/or embodiment of example rather than whole.Based on the embodiment and/or embodiment in the disclosure, this field is general
The every other embodiment and/or every other implementation that logical technical staff is obtained without making creative work
Example belongs to the scope of disclosure protection.
In one aspect of the present disclosure, a kind of display panel can be provided.Display panel can include substrate.On substrate
Flatness layer can be provided with.First electrode can be provided on flatness layer.Luminescent layer can be provided on the first electrode.
Second electrode can be provided on luminescent layer.Display panel includes auxiliary electrode, and wherein auxiliary electrode is arranged in flatness layer, and
And it is electrically connected with second electrode.
In another aspect of the disclosure, a kind of display device can be provided.The display device can include appointing above
The display panel of one.
In another aspect of the disclosure, it can be provided in and flatness layer is formed on substrate；The first electricity is formed on flatness layer
Pole；Luminescent layer is formed on the first electrode；Second electrode is formed on the light-emitting layer；Wherein, auxiliary electricity is formed in flatness layer
Pole, and auxiliary electrode is electrically connected with second electrode.
In the disclosure, if do not particularly pointed out, layer and film can be used interchangeably.In following description, with comprising
It is illustrated exemplified by the display panel of thin film transistor (TFT), but the present disclosure is not limited thereto.As used in the disclosure, " about " represents surveying
Within the error range of amount, such as within ± the 10% of the numerical value limited or within ± 5% or within ± 1%.Term
" first ", " second ", " the 3rd ", " the 4th " and " the 5th " etc. is only used for description purpose, and it is not intended that instruction or hint phase
To importance or the implicit quantity for indicating indicated technical characteristic.Define as a result, " first ", " second ", " the 3rd ",
One or more this feature can be expressed or be implicitly included to the feature of " the 4th " and " the 5th " etc..In the disclosure,
Term " ... formed on surface " or " ... coated on surface " in " ... on surface " it can include
" ... in whole surface " or " ... on part surface ".
In the following description, exemplified by sometimes using anode as first electrode and cathode as second electrode, but this public affairs
It opens without being limited thereto.For example, first electrode can be used as to cathode, and second electrode is used as anode.
The problem of for described in background parts, in order to improve display homogeneity, proposes to make in one embodiment of the disclosure
With the auxiliary electrode being connected with transparent electrode such as auxiliary cathode, to achieve the purpose that reduce transparent electrode resistance.For example, pass through by
Auxiliary cathode is arranged in pixel defining layer, can realize the purpose for reducing transparent cathode resistance.But due between the anode of pixel
Away from smaller, may there is no sufficient space to make auxiliary cathode.Therefore in the embodiment with auxiliary cathode to the resistance of transparent cathode
Reduction limitation.
Fig. 1 is illustratively to represent that display panel according to an embodiment shows in the section view on orientation substrate
It is intended to.
As shown in fig. 1, display panel according to an embodiment can include substrate 10, film on the substrate 10
Transistor 20, the passivation layer 30 on thin film transistor (TFT) 20, the flatness layer 40 on passivation layer 30, first on flatness layer 40
Electrode 60 and pixel defining layer 70, the luminescent layer 80 in first electrode 60 and in pixel defining layer 70 and luminescent layer 80
Two electrodes 90.As shown in Figure 1, thin film transistor (TFT) 20 can include buffer layer 21 on the substrate 10, having on buffer layer 21
It active layer 22, the gate insulator 23 on active layer 22, the grid 24 on gate insulator 23 and is electrically connected with active layer 22
And source electrode 25 on it and drain electrode 26 and the interlayer dielectric layer 27 for isolating source electrode 25, drain electrode 26 and grid 24.The
One electrode 60 is by being formed in the leakage of through hole 402 and thin film transistor (TFT) 20 in the through hole 302 and flatness layer 40 in passivation layer 30
Pole 26 is electrically connected.Pixel defining layer 70 limits pixel region 81, and luminescent layer 80 is formed in pixel region 81.
In structure as shown in Figure 1, second electrode 90 can be implemented as transparent electrode.Transparent electrode is to light
Transmitance is more demanding, thus the thickness of transparent electrode should be thin as far as possible.But the thinner resistance of film layer of transparent electrode is higher,
Excessively high resistance causes resistance drop (IR drop) occurs in transparent electrode, influences entire display homogeneity.Such situation
It is especially prominent in large size panel, thus need such as to aid in the moon using the auxiliary electrode being connected with transparent electrode such as transparent cathode
Pole, to achieve the purpose that reduce transparent electrode resistance.
Fig. 2 is illustratively to represent the display panel according to another embodiment in the section view on orientation substrate
Schematic diagram.
As shown in Figure 2, display panel can include flatness layer 40, pixel defining layer 70 and second electrode 90 such as cathode.
Luminescent layer 80 is formed in pixel defining layer 70.Cathode is covered in pixel defining layer 70 and connects with luminescent layer 80.Flatness layer 40 with
Such as anode of first electrode 60 is provided between luminescent layer 80 with luminescent layer 80 to connect.Auxiliary electrode is provided in pixel defining layer 70
50 such as auxiliary cathodes.Such as cathode of second electrode 90 is electrically connected with auxiliary cathode 50.
Equally, by the way that auxiliary cathode is arranged in pixel defining layer 70, the mesh for reducing transparent cathode resistance can be realized
's.But since the anode spacing of pixel is smaller, auxiliary cathode is made without sufficient space, therefore the auxiliary cathode is to transparent cathode
Resistance reduction limitation.
The problem of for above-mentioned embodiment as depicted in figs. 1 and 2, inventors herein proposing for the disclosure further changes
Into scheme.Fig. 3 is illustratively to represent the display panel according to another embodiment of the disclosure perpendicular to orientation substrate
On schematic cross-sectional view.
As shown in Figure 3, substrate 10, on the substrate 10 can be included according to the display panel of the embodiment of the disclosure
Thin film transistor (TFT) 20, the passivation layer 30 on thin film transistor (TFT) 20, the flatness layer 40 on passivation layer 30, on flatness layer 40
First electrode 60 and pixel defining layer 70, the luminescent layer 80 in first electrode 60 and in pixel defining layer 70 and luminescent layer 80
On second electrode 90.Thin film transistor (TFT) 20 can include buffer layer 21 on the substrate 10, the active layer on buffer layer 21
22nd, the gate insulator 23 on active layer 22, the grid 24 on gate insulator 23 and be electrically connected with active layer 22 and
Source electrode 25 on it and drain 26 and the interlayer dielectric layer 27 for isolating source electrode 25, drain electrode 26 and grid 24.First electricity
Pole 60 is by being formed in the drain electrode 26 of through hole 402 and thin film transistor (TFT) 20 in the through hole 302 and flatness layer 40 in passivation layer 30
Electrical connection.As shown in figure 3, display panel further includes auxiliary electrode 50, wherein auxiliary electrode 50 is arranged in flatness layer 40, and
It is electrically connected with second electrode 90.Pixel defining layer 70 limits pixel region 81, and luminescent layer 80 is formed in pixel region 81.
In this way, by the way that auxiliary electrode 50 is arranged in flatness layer 40, and it is electrically connected with second electrode 90, it can will be auxiliary
The area of electrode 50 is helped to be made quite big, so as to significantly reduce the resistance of second electrode 90.
According to another embodiment of the disclosure, pixel defining layer 70 can be arranged on flatness layer 40, and is limited
Pixel region 81, and luminescent layer 80 is formed in pixel region 81, and wherein auxiliary electrode 50 is by being located at pixel defining layer 70
It is electrically connected with the hole in flatness layer 40 with second electrode 90.
According to another embodiment of the disclosure, flatness layer 40 can include the first flatness layer 42 and the second flatness layer
44.As shown in figure 3, the first flatness layer 42 is set on the substrate 10, wherein auxiliary electrode 50 is arranged on the first flatness layer 42, the
Two flatness layers 44 cover 50 and first flatness layer 42 of auxiliary electrode.
According to another embodiment of the disclosure, pixel defining layer 70 can be arranged on flatness layer 40, and is limited
Pixel region 81, and luminescent layer 80 is formed in pixel region 81, and wherein auxiliary electrode 50 is by running through pixel defining layer 70
Through hole 704 (i.e. the second through hole 704) and the second flatness layer 44 90 electricity of through hole 444 (i.e. first through hole 444) and second electrode
Connection.
According to another embodiment of the disclosure, the thickness of the first flatness layer 42 can be about 0.5 μm to about 1.5 μm, and
And second the thickness of flatness layer 44 can be about 0.5 μm to about 1.5 μm.
According to another embodiment of the disclosure, the second flatness layer 44 can include the part of covering auxiliary electrode 50
It 44A and covers and contacts the part of the first flatness layer 42.Second flatness layer 44 covers and contacts the first flatness layer 42
The thickness of part 44B is equal to the sum of the thickness of the part 44A of covering auxiliary electrode 50 and the thickness of auxiliary electrode 50.
According to another embodiment of the disclosure, the thickness D2 of the thickness D1 of auxiliary electrode 50 and the first flatness layer 42 with
Covering and contacting the ratio between summation of thickness D3 of part 44B of the first flatness layer 42 D1/ (D2+D3) for second flatness layer 44 can
Think about 1: 10 to about 1: 3, for example, about 1: 9 to about 1: 3.5, for example, about 1: 8 to about 1: 4 or for example, about 1: 7 to about 1: 4.Pass through
Such embodiment, can be in the situation of the function for the flatness layer 40 for ensureing to include the first flatness layer 42 and the second flatness layer 44
The lower area by auxiliary electrode 50 is made quite big, so as to significantly reduce the resistance of second electrode 90.
According to another embodiment of the disclosure, the thickness of auxiliary electrode 50 can be about 300nm to about 750nm, example
Such as from about 350nm to about 700nm or for example, about 400nm to about 650nm.
According to another embodiment of the disclosure, the covering of the thickness of the first flatness layer 42 and the second flatness layer 44 and
The summation for contacting the thickness of the part of the first flatness layer 42 can be about 1 μm to about 3 μm, for example, about 1.2 μm to about 2.5 μm.
Fig. 4 is bowing for the auxiliary electrode 50 for the display panel for illustratively representing another embodiment according to the disclosure
Depending on schematic diagram.
As shown in Figure 4, auxiliary electrode 50 can be by running through the second through hole 704 and first through hole 444 and second electrode
90 electrical connections.First electrode 60 is by being formed in the through hole 302 (i.e. fifth hole 302) of passivation layer 30, the first flatness layer 42
Through hole 442 (i.e. fourth hole 442) and thin film transistor (TFT) 20 in through hole 422 (i.e. third through-hole 422) and the second flatness layer 44
Drain electrode 26 be electrically connected.Pixel defining layer 70 is used to limit multiple pixel regions 81.It is flat that the through hole 402 of flatness layer 40 includes first
Fourth hole 442 in 422 and second flatness layer 44 of third through-hole of smooth layer 42.
Auxiliary electrode 50 can be mesh electrode.
According to another embodiment of the disclosure, due to being formed in flatness layer 40 for by first electrode 60 and drain electrode
The auxiliary electrode 50 that the through hole 402 of 26 electrical connections and formation are electrically connected with second electrode 90, therefore can leave for shape
Auxiliary electrode 50 is formed into the region of through hole 402 so that auxiliary electrode 50 is electrically isolated with the conductive material in through hole 402.
According to another embodiment of the disclosure, auxiliary electrode 50 is parallel to the area and flatness layer on orientation substrate
40 or first flatness layer 42 or the second flatness layer 44 can be about 1: 1.2 to about 1 parallel to the area ratio on orientation substrate:
5 or about 1: 1.3 to about 1: 4 or about 1: 1.3 to about 1: 3 or about 1: 1.5 to about 1: 2.Since the first flatness layer 42 or the second is flat
Smooth layer 44 is being equal to the area of substrate 10 parallel to the area on orientation substrate, therefore can be made the area of auxiliary electrode 50
It is quite big, so as to significantly reduce the resistance of second electrode 90.
According to another embodiment of the disclosure, auxiliary electrode 50 can include conductive metal layer.Conductive metal layer can
With comprising selected from by copper, silver, aluminium, they arbitrary two or three alloy and its group that forms of mixture in conducting metal.
According to another embodiment of the disclosure, auxiliary electrode 50 can protect conductive layer, conduction with including first
The multilayered structure of metal layer and the second protection conductive layer.Conductive metal layer is located at the first protection conductive layer and the second protection is conductive
Between layer.Multilayered structure can include the three-decker that the first protection conductive layer/conductive metal layer/second protects conductive layer.The
The thickness of one protection conductive layer and the second protection conductive layer can be each independently about 10 to about 100nm, and for example, about 20 to about
90nm or for example, about 30 to about 80nm.The thickness of conductive metal layer can be about 300 to about 500nm, and for example, about 350 to about
450nm。
It can select 50 material of auxiliary electrode and first electrode material so that the etching ratio between them is as big as possible, example
If auxiliary electrode 50 selects MoNb/Cu/MoNb, and first electrode 60 selected as AlNd or A1, thus to ensure first electrode
60 in etching, and the etching liquid for etching AlNd or Al will not cause brokenly exposed auxiliary electrode 50MoNb/Cu/MoNb
It is bad.
According to another embodiment of the disclosure, material of the first electrode 60 used in the drain electrode 26 of thin film transistor (TFT) 20
It can be identical or different.
According to another embodiment of the disclosure, first electrode 60 can include AlNd or A1.Auxiliary electrode 50 can be with
With the multilayered structure for including the first protection conductive layer, conductive metal layer and the second protection conductive layer.Conductive metal layer is located at the
Between one protection conductive layer and the second protection conductive layer.First protection conductive layer and the second protection conduction can include MoNb.It leads
Metal layer can be aluminium layer, layers of copper or silver layer.
According to another embodiment of the disclosure, first electrode 60 can be anode, and second electrode 90 can be
Cathode.
According to another embodiment of the disclosure, the thickness of cathode can be about 50nm to about 200nm, for example, about 60nm
To about 180nm or for example, about 80nm to about 160nm.
According to another embodiment of the disclosure, cathode can include IZO, ITO, AZO or Ag nano wire.
In display panel shown in Fig. 1, the material of flatness layer 40 is acrylic and thickness is 4 μm；Anode is AlNd, and
And thickness is 300nm；The material of pixel defining layer 70 is polyimides, and 2.5 μm of thickness；And cathode is IZO, and thickness is
80nm.By connecting the metal pad of Mo (600 angstroms)/AlNd (5000 angstroms)/Mo (600 angstroms) at the both ends of cathode, two are found
Resistance between metal pad is about 10 Ω.
According to one embodiment of the disclosure, in display panel shown in Fig. 3, the material of the first flatness layer 42 is sub- gram
Power and thickness are 2 μm；Auxiliary cathode is mesh electrode shown in Fig. 4, using the three-decker of MoNb/Cu/MoNb, two layers of MoNb
The thickness of layer is all 50nm, and the surface area that Cu layer thickness is 400nm, the surface area of auxiliary cathode and the first flatness layer 42
The ratio between be 0.75：1；The material of first flatness layer 42 is acrylic and thickness is 2 μm；Anode is AlNd, and thickness is
300nm；The material of pixel defining layer 70 is polyimides, and 2.5 μm of thickness；And cathode is IZO, thickness 80nm.It is logical
The metal pad in the metal pad of the both ends of cathode connection Mo (600 angstroms)/AlNd (5000 angstroms)/Mo (600 angstroms) is crossed, finds two
Resistance between a metal pad is about 4 Ω.
Therefore, by the way that auxiliary electrode 50 is arranged in flatness layer 40, and it is electrically connected with second electrode 90, it can will be auxiliary
The area of electrode 50 is helped to be made quite big, so as to significantly reduce the resistance of second electrode 90.For example, connect Mo at the both ends of cathode
It, can be by the resistance between two metal pads in the case of the metal pad of (600 angstroms)/AlNd (5000 angstroms)/Mo (600 angstroms)
About 10 Ω never in the case of auxiliary electrode 50, which are reduced to, about 4 Ω of auxiliary electrode 50.
Fig. 5 to Figure 11 is illustratively to represent be passivated according to the display panel of another embodiment of the disclosure respectively
The first flatness layer 42, formation auxiliary electrode 50 and its graphical, the second flatness layer 44 of formation are formed on layer 30, in passivation layer 30
Fifth hole 302 is formed to expose drain electrode 26, form on the second flatness layer 44 first electrode 60 and its graphical, flat second
On smooth layer 44 formed pixel defining layer 70 and pixel defining layer 70 limit pixel region 81 in formed luminescent layer 80 when
Schematic cross-sectional view on orientation substrate.
According to the disclosure embodiment, a kind of method for preparing display panel can be provided, method includes following
Step：
The first flatness layer 42 is formed on the substrate 10；
Auxiliary electrode 50 is formed on the first flatness layer 42；
The second flatness layer 44 is formed on the first flatness layer 42 for being formed with auxiliary electrode 50；
The first through hole 444 communicated with auxiliary electrode 50 is formed in the second flatness layer 44；
First electrode 60 is formed on the second flatness layer 44 with first electrode material；
It is formed to limit the pixel defining layer 70 of pixel region 81 on the second flatness layer 44；
The second through hole 704 communicated with first through hole 444 is formed in pixel defining layer 70；
Luminescent layer 80 is formed in pixel region 81；With
Second electrode 90 is formed on the surface of luminescent layer 80 and pixel defining layer 70 with second electrode material, wherein second
Electrode material fills 444 and second through hole 704 of first through hole, and is electrically connected with auxiliary electrode 50.
Display panel further includes passivation layer 30 on substrate 10 and under the first flatness layer 42 and in substrate 10
The upper and thin film transistor (TFT) 20 below passivation layer 30, thin film transistor (TFT) 20 have drain electrode 26, and method further includes：
Third through-hole 422 is formed in the first flatness layer 42, in the top of drain electrode 26；
Fourth hole 442 is formed in the second flatness layer 44；With
Fifth hole 302, wherein fifth hole 302 and fourth hole 442 and third through-hole 422 are formed in passivation layer 30
It communicates；
Wherein when with first electrode material in formation first electrode 60 on the second flatness layer 44, the filling of first electrode material
Fourth hole 442, third through-hole 422 and fifth hole 302, and first electrode and the drain electrode 26 of thin film transistor (TFT) 20 are electrically connected
It connects.
Second electrode display panel after 90s is formed in pixel defining layer 70 and luminescent layer 80 perpendicular to orientation substrate
On schematic cross-sectional view it is shown in Figure 3.Substrate 10 in Fig. 5 to Figure 11, thin film transistor (TFT) 20 on the substrate 10 and in film
Passivation layer 30 on transistor 20 is identical in Fig. 3, and for simplicity, no longer it is described in detail herein.
Fig. 5 is illustratively to represent to be formed on passivation layer 30 according to the display panel of another embodiment of the disclosure
In the schematic cross-sectional view on orientation substrate during the first flatness layer 42.
As shown in Figure 5, the first flatness layer 42 is formed on passivation layer 30 shown in Fig. 3.Form the first flatness layer 42
Material can be acrylic, polyimides and silicone resin.The thickness of first flatness layer 42 can be about 0.5 μm to about 1.5 μ
M, for example, about 0.6 to about 1.5 μm or about 0.8 to about 1.2 μm.The method of formation can include spin coating, then expose, develop and
Etching.It is coated on the surface of passivation layer 30, by exposing, developing and etch, in the upper of drain electrode 26 in the first flatness layer 42
It is square into third through-hole 422.
Fig. 6 is illustratively to represent the display panel according to another embodiment of the disclosure on the first flatness layer 42
Formed auxiliary electrode 50 and its it is graphical when in the schematic cross-sectional view on orientation substrate.
As shown in Figure 6, auxiliary electrode 50 is formed on shown the first flatness layer 42 in Figure 5.It can be by sputtering at
50 material layer of auxiliary electrode is formed on the surface of first flatness layer 42, then forms it into mesh electrode by patterning processes,
As shown in Figure 4.Patterning processes can include exposure, development and etching.It can also be flat first by InkJet printing processes
Netted formation auxiliary electrode 50 on layer 42.Due to being formed in the first flatness layer 42 for first electrode 60 26 to be electrically connected with draining
The through hole 422 that connects and the auxiliary electrode 50 being electrically connected with second electrode 90 is formed on, therefore can left for shape
Auxiliary electrode 50 is formed into the region of through hole 422 so that auxiliary electrode 50 is electrically isolated with the conductive material in through hole 422.
Fig. 7 is illustratively to represent the display panel according to another embodiment of the disclosure in 42 He of the first flatness layer
In the schematic cross-sectional view on orientation substrate when forming the second flatness layer 44 on auxiliary electrode 50.
As shown in Figure 7, the second flatness layer 44 is formed on the first flatness layer 42 shown in Fig. 6 and auxiliary electrode 50.The
The material of two flatness layers 44 can be acrylic, polyimides and silicone resin.The thickness of second flatness layer 44 can be about
0.5.5 to about 1.5 μm, for example, about 0.6 to about 1.5 μm or about 0.8 to about 1.2 μm.The method of formation can include spin coating, so
Post-exposure, development and etching.It is coated on the surface of passivation layer 30, by exposing, developing and etch, in the second flatness layer 44
Form the fourth hole 442 communicated with third through-hole 422 and the first through hole 444 communicated with auxiliary electrode 50.
Fig. 8 is illustratively to represent to be formed in passivation layer 30 according to the display panel of another embodiment of the disclosure
In the schematic cross-sectional view on orientation substrate when fifth hole 302 is to expose drain electrode 26.
As shown in Figure 8, by being dry-etched in formation fifth hole 302 in passivation layer 30.Fifth hole the 302, the 4th
Through hole 442 and third through-hole 422 communicate, so as to expose drain electrode 26.
Fig. 9 is illustratively to represent the display panel according to another embodiment of the disclosure on the second flatness layer 44
Formed first electrode 60 and its it is graphical when in the schematic cross-sectional view on orientation substrate.
As shown in Figure 9, first electrode 60 is formed on the second flatness layer 44 as shown in Figure 8.Sputtering can be passed through
The first electricity is formed on the surface of the second flatness layer 44 and in fifth hole 302, third through-hole 422 and fourth hole 442
Then the first electrode material layer formed on the surface of the second flatness layer 44 is formed as by pole material layer by patterning processes
One electrode 60.Patterning processes can include exposure, development and etching.First electrode 60 passes through in fifth hole 302, third through-hole
422 and fourth hole 442 in first electrode material 26 be electrically connected with drain electrode.
Figure 10 is illustratively to represent the display panel according to another embodiment of the disclosure in the second flatness layer 44
In the schematic cross-sectional view on orientation substrate during upper formation pixel defining layer 70.
As shown in Figure 10, pixel defining layer 70 is formed on the second flatness layer 44 as shown in Figure 9, and is limited
Pixel region 81, and luminescent layer 80 is formed in pixel region 81.Formed pixel defining layer 70 material can be acrylic,
Polyimides and silicone resin.The thickness of pixel defining layer 70 can be about 1 μm to about 5 μm, for example, about 1 μm to about 3 μm or
For example, about 2 μm to about 3 μm.The method of formation can include spin coating, then expose, develop and etch.In the second flatness layer 44
It is coated on surface, then by exposing, developing and etch, the second through hole 704 is formed in pixel defining layer 70 to lead to first
Hole 444 communicates, so as to expose auxiliary electrode 50.
Figure 11 is illustratively to represent the display panel according to another embodiment of the disclosure in pixel defining layer 70
In the schematic cross-sectional view on orientation substrate when forming luminescent layer 80 in the pixel region 81 of restriction.
As shown in Figure 11, luminescent layer 80 is formed in the pixel region 81 limited in pixel defining layer 70.Spray may be employed
Black printing technology forms luminescent layer 80 by luminous organic material.
Then, by second electrode material in the whole surface of pixel defining layer 70 as shown in Figure 10 and luminescent layer 80
Second electrode 90 is formed on surface.444 and second through hole of first through hole of auxiliary electrode 50 is exposed in the filling of second electrode material
704.The thickness of second electrode 90 can be about 50nm to about 200nm, and for example, about 60nm to about 180nm or for example, about 80nm are extremely
About 160nm.Form second electrode display panel after 90s as shown in Figure 3.
Fig. 3 and Fig. 5-11 is illustrated so that display panel includes top gate type thin film transistor 20 as an example, but this public affairs
It opens without being limited thereto.For example, the construction shown in Figure 12 or Figure 13 can may be employed with the display panel of the disclosure.
Figure 12 is illustratively to represent the display panel according to another embodiment of the disclosure perpendicular to substrate side
Upward schematic cross-sectional view.
The display panel for including the bottom gate thin film transistor 20 with etching barrier layer is shown in Figure 12.In Figure 12
Shown, grid 24 is between active layer 22 and substrate 10, and bottom gate thin film transistor 20 has etching barrier layer 29.Etching
Barrier layer 29 covers active layer 22 and the gate insulator 23 not covered by active layer 22, and isolates source electrode 25 and drain electrode 26.
Part and the passivation layer 30 shown in Fig. 3 and passivation on the passivation layer 30 of display panel shown in Figure 12 and passivation layer 30
Part on layer 30 is identical.
Figure 13 is illustratively to represent the display panel according to the further embodiment of the disclosure perpendicular to substrate side
Upward schematic cross-sectional view.
The display panel for including back of the body channel-type bottom gate thin film transistor 20 is shown in Figure 13.As shown in Figure 13, grid
Pole 24 is between active layer 22 and substrate 10.Part on the passivation layer 30 of display panel shown in Figure 13 and passivation layer 30
It is identical with the passivation layer 30 shown in Fig. 3 and the part on passivation layer 30.
According to the disclosure, a kind of display panel, the display device comprising display panel can be provided and prepare display panel
Method, wherein display panel include auxiliary electrode, by the way that auxiliary electrode is arranged in flatness layer, and with second electrode electricity
The area of auxiliary electrode can be made quite big, so as to significantly reduce the resistance of second electrode by connection.
Obviously, those skilled in the art can carry out the embodiment of the present disclosure various modification and variations without departing from this public affairs
The spirit and scope opened.In this way, if these modifications and variations of the disclosure belong to disclosure claim and its equivalent technologies
Within the scope of, then the disclosure is also intended to comprising including these modification and variations.
Claims (14)
1. a kind of display panel, including：
Substrate；
Flatness layer, the flatness layer are set on the substrate；
First electrode, the first electrode are arranged on the flatness layer；
Luminescent layer, the luminescent layer are set on the first electrode；
Second electrode, the second electrode are set on the light-emitting layer；With
Auxiliary electrode, the auxiliary electrode are arranged in the flatness layer, and are electrically connected with the second electrode.
2. display panel according to claim 1, further includes：Pixel defining layer, the pixel defining layer are arranged on described
On flatness layer, and pixel region being limited, wherein institute's luminescent layer is formed in the pixel region,
Wherein described auxiliary electrode passes through the hole being located in the pixel defining layer and the flatness layer and second electrode electricity
Connection.
3. display panel according to claim 1, wherein the flatness layer includes：
First flatness layer and
Second flatness layer,
Wherein, first flatness layer is set on the substrate, and the auxiliary electrode is arranged on first flatness layer, and
And second flatness layer covers the auxiliary electrode and first flatness layer.
4. display panel according to claim 3, further includes：Pixel defining layer, the pixel defining layer are arranged on described
On second flatness layer, and pixel region being limited, wherein institute's luminescent layer is formed in the pixel region,
Wherein described auxiliary electrode is electric by the through hole and described second for running through the pixel defining layer and second flatness layer
Pole is electrically connected.
5. display panel according to claim 3, wherein the thickness of first flatness layer is 0.5 μm to 1.5 μm, and
The thickness of second flatness layer is 0.5 μm to 1.5 μm.
6. display panel according to claim 3, wherein second flatness layer includes covering the portion of the auxiliary electrode
Point and cover and contact the part of first flatness layer, wherein the covering of second flatness layer and contacting described first
The thickness of the part of flatness layer is equal to the sum of the thickness for the part for covering the auxiliary electrode and the thickness of the auxiliary electrode.
7. display panel according to claim 6, wherein the thickness D1 of the auxiliary electrode and first flatness layer
Thickness D2 and second flatness layer cover and contact the ratio between the summation of thickness D3 of part of first flatness layer D1/
(D2+D3) it is 1: 10 to 1: 3.
8. display panel according to claim 6, wherein the thickness of the auxiliary electrode is 300nm to 750nm；And institute
State covering and contacting the thickness of the part of first flatness layer for the thickness of the first flatness layer and second flatness layer
Summation is 1 μm to 3 μm.
9. display panel according to claim 1, wherein the auxiliary electrode parallel to the area on orientation substrate with
The flatness layer is being 1: 1.2 to 1: 5 parallel to the area ratio on orientation substrate.
10. display panel according to claim 1, wherein the auxiliary electrode is mesh electrode.
11. display panel according to claim 1 includes the first protection conductive layer, leads wherein the auxiliary electrode has
Metal layer and second protection conductive layer multilayered structure, wherein the conductive metal layer be located at described first protection conductive layer and
Between the second protection conductive layer, the thickness of the first protection conductive layer and the second protection conductive layer is independently
For 10 to 100nm, and the thickness of the conductive metal layer is 300 to 500nm.
12. display panel according to claim 11, wherein the first electrode is AlNd or Al, the conductive metal layer
It is Cu, and the first protection conductive layer and the second protection conductive layer are MoNb.
13. display panel according to claim 1, wherein the first electrode is anode, and the second electrode is
Cathode.
14. a kind of display device, including the display panel according to any one of claim 1-13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721146767.0U CN207424482U (en) | 2017-09-07 | 2017-09-07 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721146767.0U CN207424482U (en) | 2017-09-07 | 2017-09-07 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107394060A (en) * | 2017-09-07 | 2017-11-24 | 京东方科技集团股份有限公司 | Display panel, display device and the method for preparing display panel |
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2017
- 2017-09-07 CN CN201721146767.0U patent/CN207424482U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107394060A (en) * | 2017-09-07 | 2017-11-24 | 京东方科技集团股份有限公司 | Display panel, display device and the method for preparing display panel |
| CN107394060B (en) * | 2017-09-07 | 2024-01-19 | 京东方科技集团股份有限公司 | Display panel, display device and method for manufacturing display panel |
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