CN207320098U - 引线框半导体封装体 - Google Patents

引线框半导体封装体 Download PDF

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Publication number
CN207320098U
CN207320098U CN201720457769.5U CN201720457769U CN207320098U CN 207320098 U CN207320098 U CN 207320098U CN 201720457769 U CN201720457769 U CN 201720457769U CN 207320098 U CN207320098 U CN 207320098U
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Prior art keywords
lead frame
package body
die pad
layers
semiconductor package
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CN201720457769.5U
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English (en)
Inventor
王远丰
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STMicroelectronics Sdn Bhd
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STMicroelectronics Sdn Bhd
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Abstract

一个或多个实施例涉及引线框和引线框半导体封装体。一个实施例涉及具有一个或多个裸片焊盘的铜引线框以及具有粗糙化表面的一条或多条引线。覆盖引线框的裸片焊盘的粗糙化表面的是银(Ag)纳米层。该纳米层的厚度优选地具有对应于该铜引线框的该粗糙化表面的厚度。例如，在一个实施例中，该铜引线框被粗糙化以具有平均约10纳米的峰和谷并且纳米层的厚度为10纳米。覆盖该Ag纳米层的一部分的是Ag微米层，其提供适当的键合表面以便通过粘合剂材料将半导体裸片耦合到裸片焊盘。

Description

引线框半导体封装体
技术领域
本公开的实施例涉及引线框封装体。
背景技术
引线框封装体广泛用在半导体工业中，并且一般而言，提供具有相对直接的组件处理的低成本解决方案。然而，在引线框封装体内的某些材料之间维持适当粘合度依然存在各种障碍。
为了提高引线框的粘合度，引线框的一个或多个表面可以被粗糙化。在那个方面，诸如粘合剂和密封剂的材料可以在组件处理期间更好地粘附至引线框的表面。
然而，遗憾的是，引线框的粗糙化表面还增大表面的可湿性。因此，由于由粗糙化表面造成的毛细效应，用于将半导体裸片或芯片耦合至引线框的粗糙化表面的粘合剂材料可以在引线框的粗糙化表面上流动或渗出。此外，能够承受热循环而不破裂的某些粘合剂材料可以在引线框的粗糙化表面上更容易地渗出或流动。
因此，期望提高半导体封装体的部件与封装体的引线框之间的粘合度。
实用新型内容
根据本实用新型的实施例，提供一种引线框半导体封装体，其提高半导体封装体的部件与封装体的引线框之间的粘合度。
一个或多个实施例涉及引线框和引线框半导体封装体。一个实施例涉及具有一个或多个裸片焊盘的铜引线框以及具有粗糙化表面的一条或多条引线。覆盖引线框的裸片焊盘的粗糙化表面的是银(Ag)纳米层。该纳米层的厚度优选地具有对应于该铜引线框的该粗糙化表面的厚度。例如，在一个实施例中，该铜引线框被粗糙化以具有平均约10纳米的峰和谷并且该纳米层的厚度为10纳米。覆盖Ag纳米层的一部分的是Ag微米层，其提供适当的键合表面以便通过粘合剂材料将半导体裸片耦合到裸片焊盘。
在一个实施例中，粘合剂材料包括铅(Pb)、锡(Sn)和银(Ag)，如，95.5％的Pb、2％的Sn和2.5％的Ag的组合物，被称为软焊料。在一个或多个实施例中，Ag纳米层减少或消除焊料材料从裸片焊盘的表面上渗出。这至少部分是由于焊料材料的Pb已经利用Ag提高了溶解性，该溶解性高于其利用引线框材料的铜材料时的溶解性。具体地，当焊料材料与纳米层的Ag一起流动时，焊料材料的Pb和纳米层的Ag形成PbAg的中间化合物。
在一个方面，提供了一种引线框半导体封装体，包括：裸片焊盘，所述裸片焊盘具有粗糙化表面、在所述裸片焊盘的所述粗糙化表面的至少一部分上的Ag纳米层以及在所述Ag纳米层的至少一部分上的Ag微米层；焊料材料，所述焊料材料在所述Ag微米层上；半导体芯片，所述半导体芯片通过所述焊料材料耦合到所述Ag微米层；至少一条引线；以及导电线，所述导电线具有耦合到所述半导体芯片的键合焊盘的第一端以及耦合到所述至少一条引线的第二端。
所述裸片焊盘和至少一条引线包括铜或铜合金。
所述Ag纳米层位于所述裸片焊盘的所述整个粗糙化表面上。
所述Ag纳米层约为10纳米厚。
所述至少一条引线是多条引线，并且所述Ag纳米层是第一Ag纳米层，所述引线框半导体封装体包括在所述多条引线上的第二Ag纳米层。
所述焊料材料是软焊料材料。
所述至少一条引线具有粗糙化表面。
在另一方面，提供了一种引线框半导体封装体，包括：裸片焊盘，所述裸片焊盘具有粗糙化表面、位于所述粗糙化表面上的Ag纳米层；焊料材料，所述焊料材料在所述裸片焊盘上；半导体芯片，所述半导体芯片通过所述焊料材料耦合到所述裸片焊盘；多条引线，所述多条引线具有粗糙化表面；以及导电线，所述导电线具有耦合到所述半导体芯片的键合焊盘的第一端以及耦合到所述多条引线的第二端。
所述焊料材料是软焊料。
所述Ag纳米层约为10纳米厚。
所述引线框半导体封装体进一步包括在所述Ag纳米层的一部分上的Ag微米层。
在所述多条引线的所述粗糙化表面上的是Ag纳米层。
所述半导体芯片的周边的外向部分是由所述焊料材料和所述Ag纳米层形成的中间材料。
根据本实用新型的实施例的引线框半导体封装体能够提高半导体封装体的部件与封装体的引线框之间的粘合度。
附图说明
在附图中，完全相同的参考号标识类似的元件。附图中的元件的尺寸和相对位置未必按比例绘制。
图1A是根据一个实施例的没有包封材料的引线框封装体的俯视图。
图1B是图1A的一部分的特写截面图。
图2是根据另一个实施例的具有包封材料的引线框封装体的一部分的特写截面图。
图3A至图3E是侧视图，展示了用于形成图1A和图1B的引线框封装体的各制造阶段。
图4是Cu和Pb的相图。
图5是Ag和Pb的相图。
具体实施方式
将理解的是，尽管出于说明的目的在此描述了本公开的具体实施例，在不背离本公开的精神和范围的情况下可以进行各种修改。
在以下描述中，阐述了某些具体细节以便提供对所公开主题的各个方面的全面理解。然而，可以在没有这些具体细节的情况下实践所公开的主题。在一些实例中，尚未详细描述包括在此公开的主题的实施例的公知结构和半导体处理方法(如，半导体功率器件)以免模糊本公开的其它方面的描述。
图1A是根据一个实施例的没有包封材料的半导体封装体的自顶向下视图。图1B是图1A的半导体封装体在图1A中所指示的位置处的部分特写截面图。
如图1A中所示，半导体封装体10包括半导体晶粒或芯片12，具体地，键合到引线框的上表面的第一、第二和第三半导体芯片12A，12B，12C。更具体地，第一、第二和第三半导体晶粒或芯片12A，12B，12C键合到裸片焊盘14的上表面，具体地，引线框的第一、第二和第三裸片焊盘14A，14B，14C。引线框是由铜(Cu)或铜合金制成的。然而，引线框可以由其他导电材料制成。如将在以下更详细解释的，引线框具有粗糙化上表面。
每个半导体芯片12包括一个或多个电气部件，如，集成电路。集成电路可以是模拟或数字电路，这些模拟或数字电路被实现为在裸片内形成的并且根据芯片的电气设计和功能电互连的有源器件、无源器件、导电层和介电层。在所展示的实施例中，第一和第二芯片是功率芯片并且第三芯片是控制器。尽管半导体封装体10包括三个半导体芯片和三个裸片焊盘，但半导体封装体可以包括任何数量的芯片和裸片焊盘，包括单个裸片焊盘上的仅一个芯片。
靠近每个裸片焊盘14的是一条或多条引线16。如在本领域公知的，引线16电耦合到半导体芯片12。具体地，靠近第一裸片焊盘14A的第一侧是引线16，靠近第二裸片焊盘14B的第二侧是引线16，并且靠近第三裸片焊盘14C的第一和第二侧是引线16。应理解的是，每个裸片焊盘的任何数量的侧可以包括一条或多条引线并且任何数量的引线可以与每个裸片焊盘对应。
如以上所提到的，半导体芯片12电耦合到引线16。在所展示的实施例中，导电线20将第一、第二和第三半导体芯片12A，12B，12C电耦合到相应的引线16。如图1B中最佳示出的，导电线20的第一端22耦合到第一半导体芯片12A的裸片焊盘并且导电线20的第二端24耦合到引线16。
包封材料26形成在电气部件(如，半导体芯片12和导电线20)周围。引线16的部分从包封材料26延伸并且为封装体10提供外部触点。封装体10内部的半导体芯片12可以通过引线16与封装体10外部的电气部件进行通信，如在本领域公知的。
包封材料26是保护电气部件(如，半导体裸片和导电线)不受损坏的绝缘材料，该损坏可以包括腐蚀、物理损坏、潮湿损坏或对电子器件和材料的其他损坏原因。在一些实施例中，包封材料26是聚合物、环氧树脂、树脂、聚酰亚胺和硅树脂中的至少一种。
如以上所提到的，至少裸片焊盘14的上表面和引线16被粗糙化。在一些实施例中，裸片焊盘14的上表面和下表面以及引线16被粗糙化或者整个引线框被粗糙化。在一个实施例中，裸片焊盘14的粗糙化表面的至少一些峰和谷以及引线16大于10微米。
裸片焊盘14包括粗糙化上表面之上的银(Ag)纳米层30。在一个实施例中，Ag纳米层30设置在引线框的铜裸片焊盘的粗糙化表面之上。Ag纳米层30可以在整个裸片焊盘之上或者在裸片焊盘的一部分之上。例如，在一个实施例中，Ag纳米层30在围绕半导体芯片12A的周边的裸片焊盘14上。
纳米层30的厚度优选地具有对应于引线框材料的粗糙化表面的厚度。例如，在一个实施例中，铜引线框的裸片焊盘14被粗糙化以具有平均大于10纳米的峰和谷，并且Ag纳米层30的厚度为10纳米。Ag纳米层30可以是几十纳米(如，小于约30纳米)的任意厚度。
在所展示的实施例中，引线16不包括Ag纳米层。在那个方面，导电线20的第二端24直接耦合到引线16的粗糙化表面。
在裸片焊盘14上，在Ag纳米层30之上的是Ag微米层32。如图1B中最佳示出的，Ag微米层32在半导体芯片12之下。Ag微米层32提供适当的键合表面以便将具有焊料材料34的半导体芯片12键合到裸片焊盘14。Ag微米层32可以是几十微米(如，小于约30微米)的任意厚度。在一个实施例中，Ag微米层32是约5至10微米厚。
图1B展示了第一半导体芯片12A和裸片焊盘14A的放大截面图，然而，应理解的是，该截面图是第二和第三半导体芯片12B，12C和裸片焊盘14B，14C的示意性截面图。如图1B中最佳示出的，第一半导体芯片12A通过焊料材料34耦合到第一裸片焊盘。具体地，焊料材料34位于第一半导体芯片12A与裸片焊盘14A的上表面上的Ag微米层32之间。焊料材料34可以是任何合适的焊料材料。在一个实施例中，焊料材料34包括铅(Pb)、锡(Sn)和银(Ag)。在一个实施例中，焊料材料具有约95.5％的Pb、2％的Sn和2.5％的Ag的组合物，该组合物在此将被称为软焊料。软焊料能够承受热循环，该热循环可以在组件处理期间发生以便形成封装体。也就是说，软焊料承受热循环而不破裂。
在一个或多个实施例中，Ag纳米层30减少或消除焊料材料34从裸片焊盘14A的表面上渗出。这至少部分是由于焊料材料34的Pb已经利用Ag提高了溶解性，该溶解性高于其利用引线框材料的铜材料时的溶解性。具体地，当焊料材料34与纳米层30的Ag一起流动时，焊料材料34的Pb和纳米层30的Ag形成PbAg中间化合物。此外，由于Ag纳米层30在引线框材料的粗糙化铜之上如此薄，因此引线框的铜能够提高粘合度以便将半导体芯片附接到裸片焊盘。应理解的是，尽管附图中未示出，在一个或多个实施例中，由于粗糙化引线框的峰和谷，Ag纳米层30将使引线框材料的某些部分暴露在裸片焊盘14和引线16上。在那个方面，引线框材料(如，铜)提供用于键合的适当材料，同时Ag纳米层限制焊料材料的渗出。在那个方面，由此提高裸片对裸片焊盘的附接。
图2展示了根据另一实施例的半导体封装体10A。除引线16还包括Ag纳米层30以外，图2的半导体封装体10A与图1的半导体封装体10在结构和功能上完全相同。在那个方面，导电线20的第二端24在Ag纳米层30处耦合到引线16。
图3A至图3E分别展示了制造半导体封装体(如，图1A和图1B的半导体封装体10和10A)的各个阶段。尽管图3A至图3E中未示出，但引线框条带包括多个裸片焊盘，如，多组第一和第二裸片焊盘14A，14B，14C，以及通过系杆耦合到一起的引线，如在本领域公知的。具体地，图3A至图3E展示了引线框条带或矩阵的一部分，该引线框条带或矩阵包括第一和第二裸片焊盘14A，14B以及邻近引线16。然而，应理解的是，引线框还将包括第三裸片焊盘14C和相应的引线16。
图3A展示了对第一和第二裸片焊盘14的一个或多个表面以及铜或铜合金引线框的引线16进行粗糙化的步骤。如以上所提到的，引线框是包括除所示出的之外的许多其他组裸片焊盘和引线的引线框条带或阵列。
利用用于粗糙化铜的任何适当技术来将铜引线框粗糙化。在一个实施例中，在电镀步骤中将引线框粗糙化。电镀步骤可以包括沉积铜和将铜从引线框上剥去二者。在另一实施例中，通过蚀刻引线框来将引线框粗糙化。如以上所提到的，将引线框的引线和裸片焊盘粗糙化，从而使得粗糙化表面的至少峰和谷平均大于10纳米。
将裸片焊盘14的至少上表面和引线框的引线16粗糙化。如果仅将引线框的一部分粗糙化，则引线框未被粗糙化的一部分可以具有在粗糙化步骤之前形成在其上的掩模(如，光刻胶)。在一个实施例中，将整个引线框条带或阵列粗糙化，包括系杆，从而使得掩模将不必形成在引线框上。
如图3B中所示，Ag纳米层30形成在裸片焊盘14的粗糙化表面上。纳米层30可以形成在裸片焊盘14的整个表面上或者至少围绕裸片焊盘14的一部分的周边，该裸片焊盘将支撑将在随后步骤中耦合到的半导体芯片。在一个实施例中，通过电镀形成Ag纳米层30。如以上所提到的，Ag纳米层30的厚度对应于铜引线框的粗糙度。因此，在铜引线框的一个或多个(或平均)峰和谷为约10纳米的实施例中，Ag纳米层30为约10纳米。应理解的是，峰和谷与纳米层之间的区别可以相对于彼此变化许多纳米，如，多达约5纳米。
如图3B中所示，Ag纳米层30未形成在引线16上。在那个方面，在形成Ag纳米层30之前，掩模层(如，光刻胶层)形成在其上没有Ag纳米层30的引线框条带或矩阵的区域上，如，引线16和系杆。在形成掩模层之后，Ag纳米层30电镀在裸片焊盘14上，并且掩模被去除。
如果图2的半导体封装体10A形成，则引线16将不会在其上形成掩模层并且Ag纳米层30也将电镀在引线16上。
如图3C中所示，Ag微米层32形成在Ag纳米层30之上的裸片焊盘14的一部分上。Ag微米层32被电镀在Ag纳米层30上。Ag纳米层30和Ag微米层32位于裸片焊盘14上在半导体芯片12将耦合到裸片焊盘14的位置处。裸片焊盘14的外周边从Ag微米层32保持暴露。如以上所提到的，Ag微米层32的厚度在约5-10微米之间。
如图3D中所示的，焊料材料34用于在Ag微米层32处将半导体芯片12耦合到裸片焊盘14。在一个实施例中，焊料材料34被沉积在Ag微米层32上，并且半导体芯片12被放置在焊料材料34上。具体地，拾取放置工具可以用于将半导体芯片12放置在Ag微米层32之上的焊料材料34上。可替代地，焊料材料34可以被沉积在半导体芯片12的后表面上或二者上。
为了在Ag微米层32处将半导体芯片12适当地粘附至裸片焊盘14，该过程可以包括加热处理步骤。例如，在一个实施例中，在这一阶段，引线框条带可以在360℃的烤炉中放置约一分钟或更少，该烤炉可以包括加热管道和传送带。在加热步骤期间，焊料材料34回流。随着焊料材料34与裸片焊盘14上的Ag纳米层30接触，焊料材料34的Pb与Ag纳米层30的Ag一起形成中间材料。
如在图5中所示，在约360℃的温度下，～5％的Ag可溶于～95％的Pb，而如图4中所示，在360℃的温度下，0％的Cu可溶于Pb。在那个方面，在加热处理步骤期间，Ag纳米层30能够与焊料材料34一起形成中间层。通过形成中间层，渗出裸片焊盘14的焊料材料34由此被消除或者至少被减少。
图3D中的半导体芯片12是功率芯片。在一个实施例中，第三半导体芯片12C是控制器，该控制器在后续步骤中耦合到引线框条带或矩阵的裸片焊盘14C。因此，尽管未示出，半导体芯片12C可以利用以上所讨论的方法中的任何一种耦合到引线框条带或矩阵的保持裸片焊盘14C。此外，为了在Ag微米层32处将半导体芯片12C适当地粘附至裸片焊盘14C，该过程可以包括加热处理步骤。在那个方面，引线框条带再一次在360℃下暴露约1分钟或更少。应理解的是，在这一第二加热步骤中，粘附半导体芯片12的焊料材料34在第一加热步骤中将再一次被暴露以便加热。然而，裸片焊盘14上的Ag纳米层30继续约束或限制焊料材料34渗出到如以上所讨论的裸片焊盘上。
如图3E中所示，导电线20耦合到半导体芯片12的裸片焊盘以及引线16。具体地，导电线20的第一端22耦合到半导体芯片12的裸片焊盘，并且导电线20的第二端24耦合到引线16。
包封材料26然后形成在电气部件(如，半导体芯片12、导电线20和引线16的一部分)周围。包封材料26可以模制在电气部件周围。例如，引线框条带或矩阵被放置在模具中，并且包封材料26被注入到模具中并且在电气部件周围流动。该过程可以包括一个或多个固化步骤以便使包封材料26硬化。尽管未示出，但在一个实施例中，裸片焊盘14的后表面可以从包封材料暴露出来。
可以组合以上所描述的各实施例以提供进一步实施例。在本说明书中引用的和/或在申请数据表中列举的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开通过引用而完全并入于此。如果必要则可以修改实施例的方面以运用各种专利、申请和公开文献的概念以提供又进一步实施例。
可以按照上文详述的描述对实施例进行这些和其它改变。一般而言，在以下权利要求中，使用的术语不应理解为将权利要求书限制为本说明书和权利要求中公开的特定实施例，而应当理解为包括所有可能实施例，连同此权利要求书有权获得的等效物的整个范围。因而，权利要求不受本公开所限制。

Claims (13)

1.一种引线框半导体封装体，其特征在于，包括：
裸片焊盘，所述裸片焊盘具有粗糙化表面、在所述裸片焊盘的所述粗糙化表面的至少一部分上的Ag纳米层以及在所述Ag纳米层的至少一部分上的Ag微米层；
焊料材料，所述焊料材料在所述Ag微米层上；
半导体芯片，所述半导体芯片通过所述焊料材料耦合到所述Ag微米层；
至少一条引线；以及
导电线，所述导电线具有耦合到所述半导体芯片的键合焊盘的第一端以及耦合到所述至少一条引线的第二端。
2.如权利要求1所述的引线框半导体封装体，其特征在于，所述裸片焊盘和至少一条引线包括铜或铜合金。
3.如权利要求1所述的引线框半导体封装体，其特征在于，所述Ag纳米层位于所述裸片焊盘的所述整个粗糙化表面上。
4.如权利要求1所述的引线框半导体封装体，其特征在于，所述Ag纳米层为10纳米厚。
5.如权利要求1所述的引线框半导体封装体，其特征在于，所述至少一条引线是多条引线，并且所述Ag纳米层是第一Ag纳米层，所述引线框半导体封装体包括在所述多条引线上的第二Ag纳米层。
6.如权利要求1所述的引线框半导体封装体，其特征在于，所述焊料材料是软焊料材料。
7.如权利要求1所述的引线框半导体封装体，其特征在于，所述至少一条引线具有粗糙化表面。
8.一种引线框半导体封装体，其特征在于，包括：
裸片焊盘，所述裸片焊盘具有粗糙化表面、位于所述粗糙化表面上的Ag纳米层；
焊料材料，所述焊料材料在所述裸片焊盘上；
半导体芯片，所述半导体芯片通过所述焊料材料耦合到所述裸片焊盘；
多条引线，所述多条引线具有粗糙化表面；以及
导电线，所述导电线具有耦合到所述半导体芯片的键合焊盘的第一端以及耦合到所述多条引线的第二端。
9.如权利要求8所述的引线框半导体封装体，其特征在于，所述焊料材料是软焊料。
10.如权利要求8所述的引线框半导体封装体，其特征在于，所述Ag纳米层为10纳米厚。
11.如权利要求8所述的引线框半导体封装体，其特征在于，进一步包括在所述Ag纳米层的一部分上的Ag微米层。
12.如权利要求8所述的引线框半导体封装体，其特征在于，在所述多条引线的所述粗糙化表面上的是Ag纳米层。
13.如权利要求8所述的引线框半导体封装体，其特征在于，所述半导体芯片的周边的外向部分是由所述焊料材料和所述Ag纳米层形成的中间材料。
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