CN206975367U - Array base palte and display device - Google Patents
Array base palte and display device Download PDFInfo
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- CN206975367U CN206975367U CN201720960969.2U CN201720960969U CN206975367U CN 206975367 U CN206975367 U CN 206975367U CN 201720960969 U CN201720960969 U CN 201720960969U CN 206975367 U CN206975367 U CN 206975367U
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- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims description 70
- 239000000203 mixture Substances 0.000 claims description 20
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- 238000007493 shaping process Methods 0.000 claims description 10
- 239000012528 membrane Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 26
- 239000010410 layer Substances 0.000 description 24
- 230000000052 comparative effect Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 10
- 239000010409 thin film Substances 0.000 description 9
- 238000000059 patterning Methods 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000000994 depressogenic effect Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model provides a kind of array base palte and display device, wherein array base palte, including substrate, the scan line and data wire intersected on substrate formed with spatial vertical, scan line and data wire limit pixel region, pixel electrode is provided with pixel region, pixel electrode includes center pixel electrode bar and marginal position pixel electrode bar, and center pixel electrode bar is higher than marginal position pixel electrode bar in vertical direction.Pixel electrode bar in center of the present utility model is higher than marginal position pixel electrode bar in vertical direction, so that transmitance, which is substantially improved, contributes relatively low marginal position pixel electrode, small elevation center pixel electrode, make the transmitance of pixel electrode everywhere more balanced and obtain certain lifting.
Description
Technical field
The technical field of liquid crystal display is the utility model is related to, more particularly to a kind of array base palte and display device.
Background technology
Thin Film Transistor-LCD development is more and more rapider, has become the flat-panel monitor of main flow.From occur to
The present, Thin Film Transistor-LCD have been developed that multiple species, and its drive pattern and display effect are not quite similar, respectively
It is long.
Wherein, the thin film transistor liquid crystal display device of plane conversion (In-Plane Switching, IPS) pattern (includes
The array base palte of IPS patterns) with its distinctive design feature and driving principle, show excellent display capabilities and effect.
Liquid crystal molecule is in the face parallel to glass substrate, after applying voltage between comb electrode, makes liquid crystal molecule occur to turn in face
It is dynamic, cause birefringence to control the transmitance of light.Fig. 1 is that the cross section structure of the array base palte of the 1st comparative example in the prior art shows
It is intended to.Referring to Fig. 1, the pixel electrode 11 and public electrode 12 of IPS display patterns are arranged on the same side, to form plane electricity
, this pattern aperture opening ratio is low, and the transmitance of light is low.
Fig. 2 is the cross section structure schematic diagram of the array base palte of the 2nd comparative example in the prior art.Referring to Fig. 2, IPS
FFS (Fringe Field Switching) framework is to include top layer strip pixel electrode 11 and the He of bottom planar public electrode 12
Insulating barrier 13 between top layer strip pixel electrode 11 and bottom planar public electrode 12, passes through the top layer in TFT substrate
Caused fringe field between strip pixel electrode 11 and bottom planar public electrode 12, make between electrode and directly over electrode
The technology that liquid crystal molecule can rotate in the plane parallel to glass substrate, corresponding electrooptics principle and IPS frameworks
Principle it is substantially similar.FFS frameworks are used for the special construction for producing fringe field so that FFS frameworks pass on the wide angle of visibilities of IPS
While, also higher transmitance.Compared to IPS frameworks, FFS frameworks are not required to set storage capacitance in addition, improve aperture opening ratio.
Fig. 3 is the cross section structure schematic diagram of the array base palte of the 3rd comparative example in the prior art.Referring to Fig. 3, IPS
Paper frameworks are that depressed part and lug boss are provided with insulating barrier 13 therein, and pixel electrode 11 and public is provided with depressed part
One in electrode 12, another in pixel electrode 11 and public electrode 12 is provided with lug boss, using by insulating barrier 13
Patterning, the pixel electrode 11 of pectination and public electrode 12 are arranged on different upright positions, can be obtained compared with high transmittance.
Existing framework is mainly considered using pixel electrode in IPS frameworks and public electrode as two entirety, conversion above
Their relative position, transmitance purpose is improved so as to reach.But the pixel electrode subdivision to pixel electrode is not examined
Consider the transmitance for improving IPS.
Utility model content
The purpose of this utility model is to provide a kind of array base palte and preparation method and display device, pixel electrode is entered
More careful division is gone, in same pixel, transmitance contributes different center pixel electrode and marginal position picture
Plain electrode makes a distinction, and by changing framework, transmitance is substantially improved and contributes relatively low marginal position pixel electrode, slightly
Center pixel electrode is lifted, makes the transmitance of pixel electrode everywhere more balanced and obtains certain lifting.
A kind of array base palte, including substrate, the scan line intersected on substrate formed with spatial vertical and data wire, scanning
Line and data wire limit pixel region, are provided with pixel electrode in pixel region, pixel electrode includes center pixel electrode
Bar and marginal position pixel electrode bar, center pixel electrode bar are higher than marginal position pixel electrode bar in vertical direction.
Further, the difference in height of center pixel electrode bar and marginal position pixel electrode bar is 0.1~0.5 μm.
Further, public electrode is additionally provided with pixel region, public electrode includes public electrode bar, pixel electrode and public affairs
The comb electrode of extremely one time composition of common-battery.
Further, the height of public electrode bar and marginal position pixel electrode bar is equal in vertical direction.
Further, the height of public electrode bar is less than the height of marginal position pixel electrode bar in vertical direction.
Further, the height of public electrode bar is more than the height of marginal position pixel electrode bar in vertical direction.
Further, insulating barrier is additionally provided with pixel region, insulating barrier is arranged on the lower section of pixel electrode and public electrode,
The thickness of insulating barrier under the pixel electrode bar of center is more than the thickness of the insulating barrier of marginal position pixel electrode bar.
Further, insulating barrier is the insulating barrier of multiple composition shaping.
Further, insulating barrier is the insulating barrier of a composition shaping.
The utility model also provides a kind of display device, including above-mentioned array base palte, color membrane substrates and is arranged on battle array
Liquid crystal layer between row substrate and color membrane substrates.
The beneficial effects of the utility model are：Center pixel electrode bar is higher than marginal position pixel in vertical direction
Electrode strip so that transmitance is substantially improved and contributes relatively low marginal position pixel electrode, small elevation center pixel
Electrode, make the transmitance of pixel electrode everywhere more balanced and obtain certain lifting.
Brief description of the drawings
Fig. 1 is the cross section structure schematic diagram of the array base palte of the 1st comparative example in the prior art.
Fig. 2 is the cross section structure schematic diagram of the array base palte of the 2nd comparative example in the prior art.
Fig. 3 is the cross section structure schematic diagram of the array base palte of the 3rd comparative example in the prior art.
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model.
Fig. 5 is the cross section structure schematic diagram of the array base palte of preferable 1st embodiment of the utility model.
Fig. 6 is the cross section structure schematic diagram of the array base palte of preferable 2nd embodiment of the utility model.
Fig. 7 is the cross section structure schematic diagram of the array base palte of preferable 3rd embodiment of the utility model.
Fig. 8 is the cross section structure schematic diagram of the array base palte of preferable 4th embodiment of the utility model.
Fig. 9 is the cross section structure schematic diagram of the array base palte of preferable 5th embodiment of the utility model.
Figure 10 is the cross section structure schematic diagram of the array base palte of preferable 6th embodiment of the utility model.
Figure 11 is the cross section structure schematic diagram of the display device with Fig. 4.
Figure 12 be the array base palte with preferable 1st embodiment of the utility model display device with it is right in the prior art
The effect contrast figure of penetrance-voltage of the display device of the array base palte of ratio.
Embodiment
Further to illustrate that the utility model is to reach technical approach and effect that predetermined purpose of utility model is taken,
Below in conjunction with drawings and Examples, to specific embodiment of the present utility model, structure, feature and its effect, describe in detail such as
Afterwards.
[the 1st embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Fig. 5 is the utility model preferable the
The cross section structure schematic diagram of the array base palte of 1 embodiment.Fig. 4 and Fig. 5, a kind of array base palte, including substrate are referred to, in substrate
On the scan line intersected formed with spatial vertical and data wire, scan line and data wire limit pixel region, in pixel region
Provided with thin film transistor (TFT), pixel electrode 11 and public electrode 12, the grid of thin film transistor (TFT) is connected with scan line, drained and number
Connected according to line, source electrode and pixel electrode 11 connect, formed with insulating barrier between source, drain electrode and pixel electrode 11.
Pixel electrode 11 and the comb electrode that public electrode 12 is a composition.
Wherein, pixel electrode 11 includes center pixel electrode bar 111 and marginal position pixel electrode bar (the first side
Edge position pixel electrode bar 112, second edge position pixel electrode bar 113), first edge position pixel electrode article 112 and
Two marginal position pixel electrode bars 113 are located at the both sides of center pixel electrode bar 111, center pixel electrode respectively
Bar 111 is higher than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113 in vertical direction, high
Degree difference is 0.1~0.5 μm.
Wherein, public electrode 12 includes public electrode bar (the first public electrode bar 121, the second public electrode bar 122), the
One public electrode bar 121, the second public electrode bar 122, first edge position pixel electrode bar 112 and second edge position pixel
The height of electrode strip 113 is equal in vertical direction.
Pixel electrode 11 and the lower section of public electrode 12 are provided with insulating barrier 13, and insulating barrier 13 is the insulation of multiple composition shaping
Layer, the thickness of the insulating barrier 13 under center pixel electrode bar 111 is more than first edge position pixel electrode bar 112 and second
The thickness of the insulating barrier 13 of the lower section of marginal position pixel electrode bar 113.
Specifically, insulating barrier 13 includes the first insulating barrier 131 and tool with central protuberance area and both sides of the edge horizontal zone
There is the second insulating barrier 132 of patterning, center pixel electrode bar 111 is located at central protuberance area, the first public electrode bar
121st, the second public electrode bar 122, first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113 are equal
Positioned at both sides of the edge horizontal zone.
Further, first edge position pixel electrode bar 112, the first public electrode bar 121, center pixel electrode
Bar 111, the second public electrode bar 122 and second edge position pixel electrode bar 113 are arranged in a crossed manner.
[the 2nd embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Fig. 6 is the utility model preferable the
The cross section structure schematic diagram of the array base palte of 2 embodiments.Refer to Fig. 4 and Fig. 6, the difference of the 2nd embodiment and the 1st embodiment
It is insulating barrier of the insulating barrier 13 for a composition shaping.
[the 3rd embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Fig. 7 is the utility model preferable the
The cross section structure schematic diagram of the array base palte of 3 embodiments.Fig. 4 and Fig. 7, a kind of array base palte, including substrate are referred to, in substrate
On the scan line intersected formed with spatial vertical and data wire, scan line and data wire limit pixel region, in pixel region
Provided with thin film transistor (TFT), pixel electrode 11 and public electrode 12, the grid of thin film transistor (TFT) is connected with scan line, drained and number
Connected according to line, source electrode and pixel electrode 11 connect, formed with insulating barrier between source, drain electrode and pixel electrode 11.
Pixel electrode 11 and the comb electrode that public electrode 12 is a composition.
Wherein, pixel electrode 11 includes center pixel electrode bar 111 and marginal position pixel electrode bar (the first side
Edge position pixel electrode bar 112, second edge position pixel electrode bar 113), first edge position pixel electrode article 112 and
Two marginal position pixel electrode bars 113 are located at the both sides of center pixel electrode bar 111, center pixel electrode respectively
Bar 111 is higher than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113 in vertical direction, and
Difference in height is 0.1~0.5 μm.
Wherein, public electrode 12 includes public electrode bar (the first public electrode bar 121, the second public electrode bar 122).The
The height of one public electrode bar 121 and the second public electrode bar 122 is less than first edge position pixel electrode in vertical direction
The height of bar 112 and second edge position pixel electrode bar 113.
Pixel electrode 11 and the lower section of public electrode 12 are provided with insulating barrier 13, and insulating barrier 13 is the insulation of multiple composition shaping
Layer, the thickness of the insulating barrier 13 under center pixel electrode bar 111 is more than first edge position pixel electrode bar 112 and second
The thickness of the insulating barrier 13 of marginal position pixel electrode bar 113.
Specifically, insulating barrier 13 include with central protuberance area, both sides of the edge depressed area and both sides of the edge convex area the
One insulating barrier 131 and the second insulating barrier 132 with patterning, the second insulating barrier 132 include central part 132a and edge part
132b, central part 132a are higher than edge part 132b, during center pixel electrode bar 111 is located above corresponding central part 132a
Heart convex area, the first public electrode bar 121 and the second public electrode bar 122 are located at both sides of the edge depressed area, first edge position
The both sides of the edge that pixel electrode bar 112 and second edge position pixel electrode bar 113 are located above the 132b of corresponding sides edge are raised
Area.
Further, first edge position pixel electrode bar 112, the first public electrode bar 121, center pixel electrode
Bar 111, the second public electrode bar 122 and second edge position pixel electrode bar 113 are arranged in a crossed manner.
[the 4th embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Fig. 8 is the utility model preferable the
The cross section structure schematic diagram of the array base palte of 4 embodiments.Refer to Fig. 4 and Fig. 8, the difference of the 4th embodiment and the 3rd embodiment
It is insulating barrier of the insulating barrier 13 for a composition shaping.
[the 5th embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Fig. 9 is the utility model preferable the
The cross section structure schematic diagram of the array base palte of 5 embodiments.Fig. 4 and Fig. 9, a kind of array base palte, including substrate are referred to, in substrate
On the scan line intersected formed with spatial vertical and data wire, scan line and data wire limit pixel region, in pixel region
Provided with thin film transistor (TFT), pixel electrode 11 and public electrode 12, the grid of thin film transistor (TFT) is connected with scan line, drained and number
Connected according to line, source electrode and pixel electrode 11 connect, formed with insulating barrier between source, drain electrode and pixel electrode 11.
Pixel electrode 11 and the comb electrode that public electrode 12 is a composition.
Wherein, pixel electrode 11 includes center pixel electrode bar 111 and marginal position pixel electrode bar (the first side
Edge position pixel electrode bar 112, second edge position pixel electrode bar 113), first edge position pixel electrode article 112 and
Two marginal position pixel electrode bars 113 are located at the both sides of center pixel electrode bar 111, center pixel electrode respectively
Bar 111 is higher than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113 in vertical direction, and
Difference in height is 0.1~0.5 μm.
Wherein, public electrode 12 includes public electrode bar (the first public electrode bar 121, the second public electrode bar 122), the
The height of one public electrode bar 121 and the second public electrode bar 122 is more than first edge position pixel electrode in vertical direction
The height of bar 112 and second edge position pixel electrode bar 113.
Specifically, pixel electrode 11 and the lower section of public electrode 12 are provided with insulating barrier 13, and insulating barrier 13 is molded for multiple composition
Insulating barrier, the thickness of the insulating barrier 13 under center pixel electrode bar 111 is more than first edge position pixel electrode bar 112
With the thickness of the insulating barrier 13 of second edge position pixel electrode bar 113, the first public electrode bar 121 and the second public electrode bar
The thickness of insulating barrier 13 under 122 is more than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113
Insulating barrier 13 thickness.
Specifically, insulating barrier 13 includes having central protuberance area, the stepped region of both sides first successively decreased by central protuberance area with
First insulating barrier 131 of the stepped region of both sides second and the second insulating barrier 132 with patterning, center pixel electrode bar
111 are located at central protuberance area, and the first public electrode bar 121 and the second public electrode bar 122 are located at the stepped region of both sides first, and first
Marginal position pixel electrode bar 112 and second edge position pixel electrode bar 113 are located at the stepped region of both sides second.
Further, first edge position pixel electrode bar 112, the first public electrode bar 121, center pixel electrode
Bar 111, the second public electrode bar 122 and second edge position pixel electrode bar 113 are arranged in a crossed manner.
[the 6th embodiment]
Fig. 4 is the planar structure schematic diagram of the preferable array base palte of the utility model, and Figure 10 is that the utility model is preferable
The cross section structure schematic diagram of the array base palte of 6th embodiment.Refer to Fig. 4 and Figure 10, the area of the 6th embodiment and the 5th embodiment
It is not insulating barrier of the insulating barrier 13 for a composition shaping.
The utility model is preferable 1st, 3, the preparation method of the array base paltes of 5 embodiments, including：
Scan line, grid, gate insulator, active layer, data wire, source electrode and drain electrode are formed in substrate；
Exhausted formed with being set on scan line, grid, gate insulator, active layer, data wire, source electrode and the substrate of drain electrode
Edge layer 13, insulating barrier 13 are the processing of composition twice.
Transparent conductive film is formed on insulating barrier 13, a composition processing is carried out to transparent conductive film, to form comb
The pixel electrode 11 of shape and the public electrode 12 of pectination.
Wherein, the pixel electrode 11 of pectination includes center pixel electrode bar 111 and first edge position pixel electrode
Bar 112 and first edge position pixel electrode bar 113, center pixel electrode bar 111 are higher than the first side in vertical direction
Edge position pixel electrode bar 112 and first edge position pixel electrode bar 113, difference in height are 0.1~0.5 μm.
In 1st embodiment, the composition processing twice of insulating barrier 13 is to include the second insulating barrier 132 of patterning；Patterning
The second insulating barrier 132 on be coated with photoresistance, exposure, etching, removing photoresistance formed there is central protuberance area and both sides of the edge horizontal zone
The first insulating barrier 131.
Further, insulating barrier 13 includes the first insulating barrier 131 and the second insulating barrier 132, the thickness of the first insulating barrier 131
For example,The thickness of second insulating barrier 132 is, for example,Center pixel electrode
The thickness of insulating barrier under bar 111 is more than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113
Insulating barrier thickness.
The utility model is preferable 2nd, 4, the preparation method of the array base paltes of 6 embodiments, difference is that insulating barrier 13 is one
The insulating barrier of secondary composition shaping.The method for example, etched, control etch recipe and technique so that center pixel electrode bar
The thickness of insulating barrier under 111 is more than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113
The thickness of insulating barrier.
Figure 11 is the cross section structure schematic diagram of the display device with Fig. 4.Figure 11 is referred to, the utility model also provides one
Kind of display device, including above-mentioned array base palte 10, color membrane substrates 20 and be arranged on array base palte 10 and color membrane substrates 20 it
Between liquid crystal layer 30.
Array base palte 10 includes：
Substrate 16；
The first metal layer 15, formed on substrate 16, form grid 15a and scan line 15b；
Gate insulator 134, formed on substrate 16 and cover the first metal layer 15；
Semiconductor layer 16, formed on gate insulator 134 and above grid 15a；
Second metal layer 14, formed on gate insulator 134, including source electrode 14a, drain electrode 14b and data wire 14c, source
Pole 14a and drain electrode 14b are separated and contacted respectively with semiconductor layer 16, and the semiconductor layer 16 of part is from source electrode 14a and drain electrode
Expose between 14b；
3rd insulating protective layer 133, formed in second metal layer 14 and the semiconductor layer 16 exposed；
Second insulating protective layer 132, is formed on the 3rd insulating protective layer 133；
First insulating protective layer 131, formed on the second insulating protective layer 132；
Pixel electrode 11 and public electrode 12, formed by the comb electrode of a composition in the first insulating protective layer 131
On.
Wherein pixel electrode 11 includes center pixel electrode bar 111 and marginal position pixel electrode bar (first edge
Position pixel electrode bar 112, second edge position pixel electrode bar 113), first edge position pixel electrode bar 112 and second
Marginal position pixel electrode bar 113 is located at the both sides of center pixel electrode bar 111, center pixel electrode bar respectively
111 are higher than first edge position pixel electrode bar 112 and second edge position pixel electrode bar 113 in vertical direction, and high
Degree difference is 0.1~0.5 μm；
Public electrode 12 includes public electrode bar (the first public electrode bar 121, the second public electrode bar 122), the first side
Edge position pixel electrode bar 112, the first public electrode bar 121, center pixel electrode bar 111, the second public electrode bar 122
It is arranged in a crossed manner with second edge position pixel electrode bar 113.
Inner side of the color membrane substrates 30 for example including substrate 31, substrate 31 is provided with color blocking layer 32 and flatness layer 33, and sets
ITO conductive layer 34 between color blocking layer 32 and flatness layer 33.
Between pectination pixel electrode 11 and public electrode 12 apply voltage after, parallel to glass substrate liquid crystal molecule in face
Inside rotate.
Figure 12 be the array base palte with preferable 1st embodiment of the utility model display device with it is right in the prior art
The effect contrast figure of penetrance-voltage of the display device of the array base palte of ratio.Table 1 is that the utility model the preferable 1st is real
Apply the display device of the array base palte of example and penetrance (the maximum electricity of the display device of the array base palte of comparative example in the prior art
Pressure) effect contrast figure.
Table 1 is the display device and comparative example in the prior art of the array base palte of preferable 1st embodiment of the utility model
Array base palte display device penetrance (maximum voltage) Contrast on effect form.
| Effect | 1st comparative example | 2nd comparative example | 3rd comparative example | 1st embodiment |
| Transmitance (max) | 6.40% | 6.46% | 6.65% | 6.78% |
| Transmitance ratio | 100% | 100.90% | 103.87% | 105.82% |
Figure 12 is referred to, curve I is penetrance-electricity of the display device of the array base palte of the 1st comparative example in the prior art
The relation of pressure, curve II are the relation of penetrance-voltage of the display device of the array base palte of the 2nd comparative example in the prior art,
Curve III is the relation of penetrance-voltage of the display device of the array base palte of the 3rd comparative example in the prior art, and curve IV is
The relation of penetrance-voltage of the display device of the array base palte of preferable 1st embodiment of the utility model.Pass through Figure 12 and table
1 as can be seen that in identical liquid crystal (such as MJ121791), identical box thickness (such as 3.5 μm), identical ITO thickness/gap-ratio
(such as 3 μm/3 μm), identical thickness of insulating layer (such as 0.2 μm), the utility model compare IPS frameworks transmitance improve
5.82%；1.0V is reduced in terms of driving voltage compared to FFS frameworks, transmitance can improve 4.88%, can obtain more excellent IS levels,
The processing procedure under conditions of 6 light shields can be ensured.The utility model increases number by the insulating barrier of fabricating patterned on the data line
According to the thickness of insulating barrier on line, can reach reduces power consumption purpose.
By adjusting the simulation of electrode distance, preferable 1st embodiment of the utility model can make equipotential lines distribution more hang down
Directly in electrode surface, so as to strengthen the effect that horizontal component of electric field turns to liquid crystal molecule.Being in particular in makes electrode edge position
Liquid crystal molecule is turned to closer to 45 ° (this angle can obtain optimal brightness), so as to lift penetrance, makes to press close to electrode surface position
Liquid crystal molecule angle is smaller, illustrates that the utility model electrode framework reduces ll vertical electric field component herein and the water in being lifted herein
Ordinary telegram field component, so as to lift transmitance.
The beneficial effects of the utility model are：Center pixel electrode bar is higher than marginal position pixel in vertical direction
Electrode strip so that transmitance is substantially improved and contributes relatively low marginal position pixel electrode, small elevation center pixel
Electrode, make the transmitance of pixel electrode everywhere more balanced and obtain certain lifting.
It is described above, only it is preferred embodiment of the present utility model, not the utility model is made any formal
Limitation, although the utility model is disclosed above with preferred embodiment, but be not limited to the utility model, it is any ripe
Professional and technical personnel is known, is not being departed from the range of technical solutions of the utility model, when in the technology using the disclosure above
Hold the equivalent embodiment made a little change or be modified to equivalent variations, as long as being without departing from technical solutions of the utility model
Hold, any simple modification, equivalent change and modification made according to the technical essence of the utility model to above example, still
Belong in the range of technical solutions of the utility model.
Claims (10)
1. a kind of array base palte, including substrate, the scan line intersected over the substrate formed with spatial vertical and data wire, institute
State scan line and data wire limits pixel region, it is characterised in that pixel electrode (11) is provided with the pixel region, it is described
Pixel electrode (11) includes center pixel electrode bar (111) and marginal position pixel electrode bar (112,113), the center
Position pixel electrode bar (111) is higher than the marginal position pixel electrode bar (112,113) in vertical direction.
2. array base palte as claimed in claim 1, it is characterised in that the center pixel electrode bar (111) and described
The difference in height of marginal position pixel electrode bar (112,113) is 0.1~0.5 μm.
3. array base palte as claimed in claim 1, it is characterised in that public electrode (12) is additionally provided with the pixel region,
The public electrode (12) includes public electrode bar (121,122), and the pixel electrode (11) and the public electrode (12) are
The comb electrode of composition.
4. array base palte as claimed in claim 3, it is characterised in that the public electrode bar (121,122) and marginal position
The height of pixel electrode bar (112,113) is equal in vertical direction.
5. array base palte as claimed in claim 3, it is characterised in that the height of the public electrode bar (121,122) is being hung down
Nogata is less than the height of marginal position pixel electrode bar (112,113) upwards.
6. array base palte as claimed in claim 3, it is characterised in that the height of the public electrode bar (121,122) is being hung down
Nogata is more than the height of marginal position pixel electrode bar (112,113) upwards.
7. array base palte as claimed in claim 3, it is characterised in that insulating barrier (13), institute are additionally provided with the pixel region
State the lower section that insulating barrier (13) is arranged on the pixel electrode (11) and the public electrode (12), the center pixel electricity
The thickness of insulating barrier (13) under pole bar (111) is more than the thickness of the insulating barrier (13) of marginal position pixel electrode bar (112,113)
Degree.
8. array base palte as claimed in claim 7, it is characterised in that the insulating barrier (13) is the insulation of multiple composition shaping
Layer.
9. array base palte as claimed in claim 7, it is characterised in that the insulating barrier (13) is the insulation of a composition shaping
Layer.
10. a kind of display device, it is characterised in that including array base palte as claimed in any one of claims 1-9 wherein (10), coloured silk
Ilm substrate (20) and the liquid crystal layer (30) being arranged between the array base palte (10) and the color membrane substrates (20).
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| CN201720960969.2U CN206975367U (en) | 2017-08-03 | 2017-08-03 | Array base palte and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720960969.2U CN206975367U (en) | 2017-08-03 | 2017-08-03 | Array base palte and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109407422A (en) * | 2018-11-14 | 2019-03-01 | 惠科股份有限公司 | Display panel, manufacturing method and display device |
| CN110441965A (en) * | 2019-08-23 | 2019-11-12 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| CN112068373A (en) * | 2020-09-10 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN112540483A (en) * | 2020-12-09 | 2021-03-23 | 惠科股份有限公司 | Display panel and display device |
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2017
- 2017-08-03 CN CN201720960969.2U patent/CN206975367U/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109407422A (en) * | 2018-11-14 | 2019-03-01 | 惠科股份有限公司 | Display panel, manufacturing method and display device |
| CN109407422B (en) * | 2018-11-14 | 2020-10-16 | 惠科股份有限公司 | Display panel, manufacturing method and display device |
| CN110441965A (en) * | 2019-08-23 | 2019-11-12 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| CN110441965B (en) * | 2019-08-23 | 2022-05-20 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN112068373A (en) * | 2020-09-10 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN112540483A (en) * | 2020-12-09 | 2021-03-23 | 惠科股份有限公司 | Display panel and display device |
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