CN206116395U - 一种具有支撑架式电感的封装结构 - Google Patents

一种具有支撑架式电感的封装结构 Download PDF

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CN206116395U
CN206116395U CN201621008850.7U CN201621008850U CN206116395U CN 206116395 U CN206116395 U CN 206116395U CN 201621008850 U CN201621008850 U CN 201621008850U CN 206116395 U CN206116395 U CN 206116395U
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inductance
substrate
packaging structure
chip
utility
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丛尤飞
章春燕
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型涉及一种具有支撑架式电感的封装结构，属于半导体封装技术领域。它包括基板（2），所述基板（2）上设置有电感部件（1），所述电感部件（1）包括电感线圈（1.1），所述电感线圈（1.1）外围包覆有绝缘层（1.3），所述绝缘层（1.3）四周设置有多个支撑架（1.2），所述多个支撑架（1.2）架设于基板（2）上，所述电感部件（1）下方通过导电部件（5）设置有至少一个芯片（3），所述电感部件（1）和芯片（3）外围包封有塑封料（4）。本实用新型一种具有支撑架式电感的封装结构，它能够缩小封装平面尺寸，减小封装结构在印刷电路板上的占用面积，提高印刷电路板的集成度，并且可以增加电感线圈圈数，提升感值。

Description

一种具有支撑架式电感的封装结构
技术领域
本实用新型涉及一种具有支撑架式电感的封装结构，属于半导体封装技术领域。
背景技术
目前对于各封装中含电感产品的结构一般都是嵌入到基板中（参见图1和图2）。这种基板嵌入电感线圈的封装结构形式不太适合高密度集成的封装结构，嵌入电感线圈的圈数受基板尺寸而限制，而且对于基板线路设计也是极大的挑战，并且封装体平面尺寸因为要整合线圈与线路的布局而增大。后续这种基板嵌入电感线圈的封装结构贴装在印刷电路板上，会使印刷电路板集成度相对降低，集成功能性相对降低。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种具有支撑架式电感的封装结构，它能够缩小封装平面尺寸，减小封装结构在印刷电路板上的占用面积，提高印刷电路板的集成度，并且可以增加电感线圈圈数，提升感值。
本实用新型解决上述问题所采用的技术方案为：一种具有支撑架式电感的封装结构，它包括基板，所述基板上设置有电感部件，所述电感部件包括电感线圈，所述电感线圈外围包覆有绝缘层，所述绝缘层四周设置有多个支撑架，所述多个支撑架架设于基板上，所述电感部件下方通过导电部件设置有至少一个芯片，所述电感部件和芯片外围包封有塑封料。
所述多个支撑架中至少有两个支撑架与电感线圈相连接，其中与电感线圈相连接的支撑架电性连接至基板，未连接电感线圈的支撑架架设于基板的绝缘区上。
所述基板为平面基板或凹槽基板。
与现有技术相比，本实用新型的优点在于：
1、本实用新型可有效的缩小封装结构的平面尺寸，减小PCB板的占用面积，提高PCB板的集成度；
2、本实用新型可以增加电感线圈圈数，提升感值。
附图说明
图1为现有的具有电感的封装结构示意图。
图2为现有的另一种具有电感的封装结构示意图。
图3为本实用新型一种具有支撑架式电感的封装结构的示意图。
图4为图3中的电感部件的结构示意图。
其中：
电感部件1
电感线圈1.1
支撑架1.2
绝缘层1.3
基板2
芯片3
塑封料4
导电部件5。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
如图3~4所示，本实施例中的一种具有支撑架式电感的封装结构，它包括基板2，所述基板2上设置有电感部件1，所述电感部件1包括电感线圈1.1，所述电感线圈1.1外围包覆有绝缘层1.3，所述绝缘层1.3四周设置有多个支撑架1.2，所述多个支撑架1.2架设于基板2上，所述电感部件1下方通过导电部件5设置有至少一个芯片3，所述电感部件1和芯片3外围包封有塑封料4；
所述多个支撑架1.2中至少有两个与电感线圈1.1相连接，其中与电感线圈1.1相连接的支撑架1.2电性连接至基板2，未连接电感线圈1.1的支撑架1.2架设于基板2的绝缘区上；
所述基板2可以为平面基板，也可以是凹槽基板，能够进一步的缩小封装体积；
所述支撑架1.2可冲塑成型成所需形状。
除上述实施例外，本实用新型还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本实用新型权利要求的保护范围之内。

Claims (3)

1.一种具有支撑架式电感的封装结构，其特征在于：它包括基板（2），所述基板（2）上设置有电感部件（1），所述电感部件（1）包括电感线圈（1.1），所述电感线圈（1.1）外围包覆有绝缘层（1.3），所述绝缘层（1.3）四周设置有多个支撑架（1.2），所述多个支撑架（1.2）架设于基板（2）上，所述电感部件（1）通过导电部件（5）下方设置有至少一个芯片（3），所述电感部件（1）和芯片（3）外围包封有塑封料（4）。
2.根据权利要求1所述的一种具有支撑架式电感的封装结构，其特征在于：所述多个支撑架（1.2）中至少有两个与电感线圈（1.1）相连接，其中与电感线圈（1.1）相连接的支撑架（1.2）电性连接至基板（2），未连接电感线圈（1.1）的支撑架（1.2）架设于基板（2）的绝缘区上。
3.根据权利要求1所述的一种具有支撑架式电感的封装结构，其特征在于：所述基板（2）为平面基板或凹槽基板。
CN201621008850.7U 2016-08-31 2016-08-31 一种具有支撑架式电感的封装结构 Active CN206116395U (zh)

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