CN205453539U

CN205453539U - Intelligence power module and air conditioner

Info

Publication number: CN205453539U
Application number: CN201620169940.8U
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2016-03-04
Filing date: 2016-03-04
Publication date: 2016-08-10
Anticipated expiration: 2026-03-04

Abstract

The utility model provides an intelligence power module and air conditioner is provided with on the HVIC pipe in the intelligent power module corresponding to current detection terminal 's first port and the second port of holding corresponding to the PFC control input, the first of self -adaptive circuit is connected to bridge arm signal input part on the three -phase respectively to the third input, and the fourth is bridge arm signal input part under the 6th input is connected to the three -phase respectively, and the 7th input is connected to the second port, and the 8th input is connected to first port, and the output can be held as the messenger of HVIC pipe, when self -adaptive circuit is the low level at first incoming signal to the 7th input, according to the incoming signal and the corresponding level signal of the output of the relation between the first setting value of the 8th input, when the incoming signal of at least one input was the high level to the 7th input in, according to the temperature of intelligent power module, the incoming signal and the corresponding level signal of the output of the relation between the the second set value of the 8th input, the the second set value was greater than first setting value first.

Description

SPM and air-conditioner

Technical field

This utility model relates to SPM technical field, in particular to a kind of SPM and a kind of air-conditioner.

Background technology

SPM (IntelligentPowerModule, it is called for short IPM) it is a kind of analog line driver that power electronics discrete device and integrated circuit technique are integrated, SPM comprises device for power switching and high-voltage driving circuit, and with overvoltage, overcurrent and the failure detector circuit such as overheated.The logic input terminal of SPM receives the control signal of master controller, and outfan drives compressor or subsequent conditioning circuit work, sends the system status signal detected back to master controller simultaneously.Relative to traditional discrete scheme; SPM has the advantages such as high integration, high reliability, self-inspection and protection circuit; it is particularly suitable for driving the converter of motor and various inverter, is the desired power level electronic device of frequency control, metallurgical machinery, electric propulsion, servo-drive, frequency-conversion domestic electric appliances.

The structural representation of existing Intelligent power module circuit is as it is shown in figure 1, MTRIP port is as current detecting end, to protect SPM 100 according to the size of current detected.PFCIN port controls input as the PFC (PowerFactorCorrection, PFC) of SPM.

In SPM work process, PFCINP end is frequently switched between low and high level by certain frequency, make that IGBT pipe 127 is continuously on off state and FRD pipe 131 is continuously in freewheeling state, this frequency be generally LIN1～LIN3,2～4 times of HIN1～HIN3 switching frequency, and the most directly contact with the switching frequency of LIN1～LIN3, HIN1～HIN3.

ITRIP is current detecting end, general by milliohm resistance eutral grounding, by the pressure drop measuring and calculating electric current of detection milliohm resistance, when current is excessive, SPM 100 is made to quit work, it is to avoid after miscarriage life is overheated excessively, SPM 100 to be produced permanent damage.

-VP, COM, UN, VN, WN have electrical connection in actual use.Therefore, current noise when voltage noise when IGBT pipe 121～IGBT pipe 127 switchs and FRD pipe 111～FRD pipe 116, FRD pipe 131 afterflow all can intercouple, and impacts the input pin of each low-voltage area.

In each input pin, HIN1～HIN3, LIN1～LIN3, PFCINP threshold value typically at about 2.3V, and the threshold voltage of ITRIP typically only have below 0.5V, therefore, ITRIP be most susceptible to interference pin.When ITRIP is toggled, SPM 100 will quit work, and because the most really there is stream, so the triggering that ITRIP is now belongs to false triggering.

In general, the voltage noise that FRD pipe 111～116, the FRD pipe 141 reverse recovery current spike when Reverse recovery is coupled on ground wire is easiest to cause this kind of false triggering.

As shown in Figure 2, when HIN1～HIN3, LIN1～LIN3, PFCINP are high level, making FRD pipe 114～116, FRD pipe 111～113, FRD pipe 141 produce reverse recovery current spike respectively, MTRIP end produces voltage noise therewith, in general, the persistent period of spike is the longest, and reverse recovery time is the longest, the noise duration of MTRIP is the longest, and the peak value of spike is the biggest, i.e. reverse recovery current is the biggest, and the noise amplitude of MTRIP is the biggest.Further, because the reverse recovery time of FRD pipe and reverse recovery current increase facing to the rising of temperature.

If the condition making MTRIP trigger is: voltage > Vth, and the persistent period > Tth；In fig. 2, if Ta < Tth < Tb, then when 25 DEG C, the reverse recovery current of FRD pipe is not enough so that MTRIP produces false triggering, and when 75 DEG C, the high voltage persistent period the shortest deficiency in first three cycle of FRD pipe is so that MTRIP produces false triggering, to the 4th cycle, MTRIP will produce false triggering.

The length of the reverse recovery time of FRD pipe is relevant with temperature, and temperature is the highest, and reverse recovery time is the longest.And, temperature is the highest when, the Converting Unit and the power correction section that are usually SPM switch when getting over the most frequently, so along with the continuous firing of system, the constant temperature of SPM 100 rises, and the probability that MTRIP is triggered is increasing, in the application scenario that some are severe, eventually produce false triggering, make system stalls.Although this false triggering can recover to destroy without forming system over time, but user can be caused puzzlement undoubtedly.Such as the application scenario for transducer air conditioning, the when that the highest user just of ambient temperature more needing air conditioning system continuous firing, but the reverse recovery time that high ambient temperature can make FRD pipe increases, MTRIP is improved by the probability of false triggering, once MTRIP is by false triggering, air conditioning system can quit work 3～5 minutes because being mistakenly considered to occur to flow, and makes user during this period of time cannot obtain cold wind, and this is to cause air conditioning system because of the not enough one of the main reasons by customer complaint of refrigerating capacity.

Therefore, how on the premise of guaranteeing that SPM can the most normally work, effectively reduce SPM and at high temperature become technical problem urgently to be resolved hurrily by the probability of false triggering.

Utility model content

This utility model is intended at least to solve one of technical problem present in prior art or correlation technique.

To this end, a purpose of the present utility model is to propose a kind of new SPM, on the premise of can the most normally can working guaranteeing SPM, effectively reduce SPM at high temperature by the probability of false triggering.

Another purpose of the present utility model is to propose a kind of air-conditioner.

For achieving the above object, embodiment according to first aspect of the present utility model, propose a kind of SPM, including: on three-phase, under brachium pontis signal input part, three-phase, brachium pontis signal input part, three-phase low reference voltage end, current detecting end and PFC control input；HVIC (HighVoltageIntegratedCircuit, high voltage integrated circuit) pipe, it is provided with on described HVIC pipe and is respectively connecting on described three-phase the terminals of brachium pontis signal input part under brachium pontis signal input part and described three-phase, and correspond to the first port of described current detecting end and control the second port of input corresponding to described PFC, described first port is connected with described current detecting end by connecting line, and described second port controls input by connecting line with described PFC and is connected；Sampling resistor, described three-phase low reference voltage end and described current detecting end be connected to the first end of described sampling resistor, and the second end of described sampling resistor is connected to the low-pressure area power supply negative terminal of described SPM；Adaptive circuit, the power supply positive pole of described adaptive circuit and negative pole are respectively connecting to low-pressure area power supply anode and the negative terminal of described SPM, the first input end of described adaptive circuit, the corresponding end that second input and the 3rd input are respectively connecting on described three-phase in brachium pontis signal input part, the four-input terminal of described adaptive circuit, the corresponding end that 5th input and the 6th input are respectively connecting under described three-phase in brachium pontis signal input part, 7th input of described adaptive circuit is connected to described second port, 8th input of described adaptive circuit is connected to described first port, the outfan of described adaptive circuit is as the Enable Pin of described HVIC pipe；

Wherein, described adaptive circuit, when the input signal of described first input end to described 7th input is all low level, exports corresponding level signal according to the magnitude relationship between value and first setting value of the input signal of described 8th input；Described adaptive circuit at described first input end to when the input signal of at least one input is high level in described 7th input, temperature according to described SPM, the magnitude relationship between value and second setting value of the input signal of described 8th input export corresponding level signal, and described second setting value is more than described first setting value.

nullSPM according to embodiment of the present utility model，Adaptive circuit is at first input end to the 7th input (i.e. brachium pontis signal input part on three-phase、Under three-phase, brachium pontis signal input part and PFC control input) input signal when being all low level，Corresponding level signal is exported by the magnitude relationship between value and first setting value of the input signal according to the 8th input (i.e. current detecting end)，Make when first input end to the 7th input of adaptive circuit is all low level (when being not likely to produce noise signal)，Adaptive circuit can make real time reaction according to the signal value that current detecting end detects，When signal value that i.e. current detecting end detects is bigger，Output in time controls HVIC and manages out-of-work enable signal，When signal value that current detecting end detects is less，Output controls the enable signal of HVIC pipe work，To guarantee that SPM can normally work under room temperature (time i.e. less than predetermined temperature value)，And carry out overcurrent protection.

At the first input end of adaptive circuit to when in the 7th input, the input signal of at least one input is high level, by the temperature according to SPM, magnitude relationship between the value of the input signal of current detecting end with the second setting value exports corresponding level signal, make when easily producing noise signal and causing false triggering, can determine whether that output controls HVIC and manages out-of-work enable signal by bigger the second setting value (compared to the first setting value) as standard, and then can effectively reduce when SPM at high temperature works by the probability of false triggering.

SPM according to above-described embodiment of the present utility model, it is also possible to there is techniques below feature:

According to an embodiment of the present utility model, described adaptive circuit is when the input signal of described first input end to described 7th input is all low level, if the value of the input signal of described 8th input is more than or equal to described first setting value, then export the enable signal of the first level, to forbid that described HVIC pipe works；Otherwise, the enable signal of output second electrical level, to allow described HVIC pipe to work；

Described adaptive circuit at described first input end to when the input signal of at least one input is high level in described 7th input, if the temperature of described SPM is higher than predetermined temperature value, and the value of the input signal of described 8th input is more than or equal to described second setting value, then export the enable signal of described first level；Otherwise, the enable signal of described second electrical level is exported.

Wherein, the enable signal of the first level can be low level signal, and the enable signal of second electrical level can be high level signal.

According to an embodiment of the present utility model, described adaptive circuit includes:

First or door, described first or three inputs of door respectively as first input end, the second input and the 3rd input of described adaptive circuit；

Second or door, described second or three inputs of door respectively as four-input terminal, the 5th input and the 6th input of described adaptive circuit；

3rd or door, described first or the outfan of door be connected to the described 3rd or the first input end of door, described second or the outfan of door be connected to the second input of the described 3rd or door, described 3rd or the 3rd input of door as the 7th input of described adaptive circuit, the described 3rd or the outfan of door be connected to the input of the first NAND gate；

First resistance, first end of described first resistance is connected to the power supply positive pole of described adaptive circuit, second end of described first resistance is connected to the negative electrode of Zener diode, and the anode of described Zener diode is connected to the power supply negative pole of described adaptive circuit；

Second resistance, the first end of described second resistance is connected to the second end of described first resistance, and the second end of described second resistance is connected to the positive input terminal of the first voltage comparator；

Critesistor, the first end of described critesistor is connected to the second end of described second resistance, and the second end of described critesistor is connected to the anode of described Zener diode；

First voltage source, the negative pole of described first voltage source is connected to the anode of described Zener diode, the positive pole of described first voltage source is connected to the negative input end of described first voltage comparator, the outfan of described first voltage comparator is connected to the second input of described first NAND gate, the outfan of described first NAND gate is connected to the input of the first not gate, and the outfan of described first not gate is connected to the control end of analog switch；

Second voltage comparator, the positive input terminal of described second voltage comparator is as the 8th input of described adaptive circuit, the negative input end of described second voltage comparator is connected to the positive pole of the second voltage source, the negative pole of described second voltage source is connected to the power supply negative pole of described adaptive circuit, and the outfan of described second voltage comparator is connected to the first selection end and first input end of the second NAND gate of described analog switch；

Tertiary voltage comparator, the positive input terminal of described tertiary voltage comparator is connected to the positive input terminal of described second voltage comparator, the negative input end of described tertiary voltage comparator is connected to the positive pole in tertiary voltage source, the negative pole in described tertiary voltage source is connected to the power supply negative pole of described adaptive circuit, the outfan of described tertiary voltage comparator is connected to the second input of described second NAND gate, the outfan of described second NAND gate is connected to the input of the second not gate, the outfan of described second not gate is connected to the second selection end of described analog switch, the fixing end of described analog switch is connected to the input of the 3rd not gate, the outfan of described 3rd not gate is as the outfan of described adaptive circuit.

nullAccording to an embodiment of the present utility model，The signal output part of PFC drive circuit it is additionally provided with on described HVIC pipe，Described SPM also includes: the first power switch pipe and the first diode，The anode of described first diode is connected to the emitter stage of described first power switch pipe，The negative electrode of described first diode is connected to the colelctor electrode of described first power switch pipe，The colelctor electrode of described first power switch pipe is connected to the anode of the second diode，The negative electrode of described second diode is connected to the high voltage input of described SPM，The base stage of described first power switch pipe is connected to the signal output part of described PFC drive circuit，The emitter stage of described first power switch pipe is as the PFC low reference voltage end of described SPM，The colelctor electrode of described first power switch pipe is as the PFC end of described SPM.

Wherein, the first power switch pipe can be IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor).

According to an embodiment of the present utility model, also including: boostrap circuit, described boostrap circuit includes:

First bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described first bootstrap diode is connected to the U phase higher-pressure region power supply anode of described SPM；Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described SPM；3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described SPM.

According to an embodiment of the present utility model, also include: bridge arm circuit on three-phase, the signal output part of corresponding phase during the input of bridge arm circuit is connected to the three-phase high-voltage district of described HVIC pipe in each phase in bridge arm circuit on described three-phase；Bridge arm circuit under three-phase, the signal output part of corresponding phase during the input of bridge arm circuit is connected to the three-phase low-voltage district of described HVIC pipe under each phase in bridge arm circuit under described three-phase.

Wherein, on three-phase, bridge arm circuit includes: bridge arm circuit in bridge arm circuit, W phase in bridge arm circuit, V phase in U phase；Under three-phase, bridge arm circuit includes: the lower bridge arm circuit of the lower bridge arm circuit of U phase, V phase, the lower bridge arm circuit of W phase.

According to an embodiment of the present utility model, in described each phase, bridge arm circuit includes: the second power switch pipe and the 3rd diode, the anode of described 3rd diode is connected to the emitter stage of described second power switch pipe, the negative electrode of described 3rd diode is connected to the colelctor electrode of described second power switch pipe, the colelctor electrode of described second power switch pipe is connected to the high voltage input of described SPM, the base stage of described second power switch pipe is as the input of bridge arm circuit in described each phase, the emitter stage of described second power switch pipe is connected to the higher-pressure region power supply negative terminal of described SPM correspondence phase.Wherein, the second power switch pipe can be IGBT.

According to an embodiment of the present utility model, under described each phase, bridge arm circuit includes: the 3rd power switch pipe and the 4th diode, the anode of described 4th diode is connected to the emitter stage of described 3rd power switch pipe, the negative electrode of described 4th diode is connected to the colelctor electrode of described 3rd power switch pipe, the colelctor electrode of described 3rd power switch pipe is connected to the anode of described 3rd diode in the upper bridge arm circuit of correspondence, the base stage of described 3rd power switch pipe is as the input of bridge arm circuit under described each phase, the emitter stage of described 3rd power switch pipe is as the low reference voltage end of the corresponding phase of described SPM.Wherein, the 3rd power switch pipe can be IGBT.

According to an embodiment of the present utility model, the voltage of the high voltage input of described SPM is 300V.

According to an embodiment of the present utility model, connect between anode and the negative terminal of each phase higher-pressure region power supply of described SPM and have filter capacitor.

Embodiment according to this utility model second aspect, it is also proposed that a kind of air-conditioner, including: the SPM as described in above-mentioned any one embodiment.

Additional aspect of the present utility model and advantage will part be given in the following description, and part will become apparent from the description below, or is recognized by practice of the present utility model.

Accompanying drawing explanation

Above-mentioned and/or additional aspect of the present utility model and advantage will be apparent from easy to understand, wherein from combining the accompanying drawings below description to embodiment:

Fig. 1 shows the structural representation of the SPM in correlation technique；

Fig. 2 shows the waveform diagram of the noise of the SPM generation in correlation technique；

Fig. 3 shows the structural representation of the SPM according to embodiment of the present utility model；

Fig. 4 shows the external circuit schematic diagram of the SPM according to embodiment of the present utility model；

Fig. 5 shows the internal structure schematic diagram of the adaptive circuit according to embodiment of the present utility model.

Detailed description of the invention

In order to be more clearly understood that above-mentioned purpose of the present utility model, feature and advantage, with detailed description of the invention, this utility model is further described in detail below in conjunction with the accompanying drawings.It should be noted that in the case of not conflicting, the feature in embodiments herein and embodiment can be mutually combined.

Elaborate a lot of detail in the following description so that fully understanding this utility model; but; this utility model can be implemented to use other to be different from other modes described here, and therefore, protection domain of the present utility model is not limited by following public specific embodiment.

Fig. 3 shows the structural representation of the SPM according to embodiment of the present utility model.

As it is shown on figure 3, according to the SPM of embodiment of the present utility model, including: HVIC pipe 1101 and adaptive circuit 1105.

The VCC end of HVIC pipe 1101 is as the low-pressure area power supply anode VDD of SPM 1100, and VDD is generally 15V；

Inside HVIC pipe 1101:

HIN1 end connects the first input end of adaptive circuit 1105；HIN2 end connects the second input of adaptive circuit 1105；HIN3 end connects the 3rd input of adaptive circuit 1105；LIN1 end connects the four-input terminal of adaptive circuit 1105；LIN2 end connects the 5th input of adaptive circuit 1105；LIN3 end connects the 6th input of adaptive circuit 1105；PFCINP end connects the 7th input of adaptive circuit 1105；ITRIP end connects the 7th input of adaptive circuit 1105；VCC end connects the power supply anode of adaptive circuit 1105；GND end connects the power supply negative terminal of adaptive circuit 1105；The outfan of adaptive circuit 1105 is designated as ICON, for controlling HIN1～HIN3, LIN1～LIN3, the effectiveness of PFCINP signal.

HVIC pipe 1101 is internal also has boostrap circuit structure as follows:

VCC end is connected with bootstrap diode 1102, bootstrap diode 1103, the anode of bootstrap diode 1104；The negative electrode of bootstrap diode 1102 is connected with the VB1 of HVIC pipe 1101；The negative electrode of bootstrap diode 1103 is connected with the VB2 of HVIC pipe 1101；The negative electrode of bootstrap diode 1104 is connected with the VB3 of HVIC pipe 1101.

Brachium pontis signal input part UHIN in the U phase that HIN1 end is SPM 1100 of HVIC pipe 1101；Brachium pontis signal input part VHIN in the V phase that HIN2 end is SPM 1100 of HVIC pipe 1101；Brachium pontis signal input part WHIN in the W phase that HIN3 end is SPM 1100 of HVIC pipe 1101；The lower brachium pontis signal input part ULIN of the U phase that LIN1 end is SPM 1100 of HVIC pipe 1101；The lower brachium pontis signal input part VLIN of the V phase that LIN2 end is SPM 1100 of HVIC pipe 1101；The lower brachium pontis signal input part WLIN of the W phase that LIN3 end is SPM 1100 of HVIC pipe 1101；The MTRIP end that ITRIP end is SPM 1100 of HVIC pipe 1101；The PFCINP end of HVIC pipe 1101 controls input PFCIN as the PFC of SPM 100；The GND end of HVIC pipe 1101 is as the low-pressure area power supply negative terminal COM of SPM 1100.Wherein, SPM 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input and PFCIN end receive 0V or 5V input signal.

The VB1 end of HVIC pipe 1101 connects one end of electric capacity 1131, and as the U phase higher-pressure region power supply anode UVB of SPM 1100；The HO1 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1121 in U phase；The VS1 end of HVIC pipe 1101 is connected with the emitter-base bandgap grading of IGBT pipe 1121, the anode of FRD pipe 1111, the lower colelctor electrode of brachium pontis IGBT pipe 1124 of U phase, the negative electrode of FRD pipe 1114, the other end of electric capacity 1131, and as the U phase higher-pressure region power supply negative terminal UVS of SPM 1100.

The VB2 end of HVIC pipe 1101 connects one end of electric capacity 1132, and as the V phase higher-pressure region power supply anode VVB of SPM 1100；The HO2 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in V phase；The VS2 end of HVIC pipe 1101 is connected with the emitter-base bandgap grading of IGBT pipe 1122, the anode of FRD pipe 1112, the lower colelctor electrode of brachium pontis IGBT pipe 1125 of V phase, the negative electrode of FRD pipe 1115, the other end of electric capacity 1132, and as the V phase higher-pressure region power supply negative terminal VVS of SPM 1100.

The VB3 end of HVIC pipe 1101 connects one end of electric capacity 1133, as the W phase higher-pressure region power supply anode WVB of SPM 1100；The HO3 end of HVIC pipe 1101 is connected with the grid of brachium pontis IGBT pipe 1123 in W phase；The VS3 end of HVIC pipe 1101 is connected with the emitter-base bandgap grading of IGBT pipe 1123, the anode of FRD pipe 1113, the lower colelctor electrode of brachium pontis IGBT pipe 1126 of W phase, the negative electrode of FRD pipe 1116, the other end of electric capacity 1133, and as the W phase higher-pressure region power supply negative terminal WVS of SPM 1100.

The LO1 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1124；The LO2 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1125；The LO3 end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1126；The emitter-base bandgap grading of IGBT pipe 1124 is connected with the anode of FRD pipe 1114, and as the U phase low reference voltage end UN of SPM 1100；The emitter-base bandgap grading of IGBT pipe 1125 is connected with the anode of FRD pipe 1115, and as the V phase low reference voltage end VN of SPM 1100；The emitter-base bandgap grading of IGBT pipe 1126 is connected with the anode of FRD pipe 1116, and as the W phase low reference voltage end WN of SPM 1100.

VDD is HVIC pipe 1101 power supply anode, and GND is the power supply negative terminal of HVIC pipe 1101；VDD-GND voltage is generally 15V；VB1 and VS1 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the outfan of U phase higher-pressure region；VB2 and VS2 is respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the outfan of V phase higher-pressure region；VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the outfan of W phase higher-pressure region；LO1, LO2, LO3 are respectively U phase, V phase, the outfan of W phase low-pressure area.

The PFCO end of HVIC pipe 1101 is connected with the grid of IGBT pipe 1127；The emitter-base bandgap grading of IGBT pipe 1127 is connected with the anode of FRD pipe 1117, and as the PFC low reference voltage end-VP of SPM 1100；The colelctor electrode of IGBT pipe 1127 is connected with negative electrode, the anode of FRD pipe 1141 of FRD pipe 1117, and as the PFC end of SPM 1100；

The colelctor electrode of IGBT pipe 1121, the negative electrode of FRD pipe 1111, the colelctor electrode of IGBT pipe 1122, the negative electrode of FRD pipe 1112, the colelctor electrode of IGBT pipe 1123, the negative electrode of FRD pipe 1113, the negative electrode of FRD pipe 1141 are connected, and the high voltage input P, P as SPM 1100 typically meets 300V.

Outside at SPM 1100, as shown in Figure 4, the UN (U phase low reference voltage end) of SPM 1100, VN (V phase low reference voltage end), the MTRIP end of WN (the W phase low reference voltage end) SPM 1100 that is connected and one end of sampling resistor 1138, the other end ground connection of sampling resistor 1138.

The effect of HVIC pipe 1101 is:

When ICON is high level, the logic input signal of the 0 or 5V of input HIN1, HIN2, HIN3 is passed to outfan HO1, HO2, HO3 respectively, the signal of LIN1, LIN2, LIN3 is passed to outfan LO1, LO2, LO3 respectively, the signal of PFCINP is passed to outfan PFCO, wherein HO1 be the logic output signal of VS1 or VS1+15V, HO2 be the logic output signal of VS2 or VS2+15V, HO3 be the logic output signal of VS3 or VS3+15V, LO1, LO2, LO3, PFCO are the logic output signals of 0 or 15V；

When ICON is low level, HO1, HO2, HO3, LO1, LO2, LO3, PFCO are all set to low level.

The effect of adaptive circuit 1105 is:

Being all the low level moment at HIN1～3, LIN1～LIN3, the PFCINP of described HVIC pipe 1101, the magnitude of voltage of ITRIP compares, as ITRIP with the voltage V1 of setting > V1 time, ICON output low level at once, otherwise ICON keep high level constant；

The HIN1～3 of described HVIC pipe 1101, LIN1～LIN3, PFCINP at least one be the temperature of high level and SPM higher than a certain particular value T1 time, the magnitude of voltage of ITRIP compares with certain voltage V2, V2 is a magnitude of voltage bigger than V1, as ITRIP > V2 time, ICON output low level at once, otherwise ICON keeps high level constant.

In an embodiment of the present utility model, the particular circuit configurations schematic diagram of adaptive circuit 1105 as it is shown in figure 5, particularly as follows:

HIN1 connects or one of them input of door 2001；HIN2 connects or one of them input of door 2001；HIN3 connects or one of them input of door 2001；

LIN1 connects or one of them input of door 2002；LIN2 connects or one of them input of door 2002；LIN3 connects or one of them input of door 2002；

PFCINP connects or one of them input of door 2003；Or the output of the outfan of door 2001 or door 2002 terminates or two other input of door 2003；Or one of them input of the output termination NAND gate 2014 of door 2003；

One termination VCC of resistance 2004；One end of the other end connecting resistance 2007 of resistance 2004 and the negative electrode of Zener diode 2005；The anode of Zener diode 2005 meets GND；

The positive input terminal of another termination voltage comparator 2009 of resistance 2007 and one end of PTC (PositiveTemperatureCoefficient, positive temperature coefficient) resistance 2006；Another termination GND of PTC resistor 2006；

The anode of the negative input termination voltage source 2008 of voltage comparator 2009；The negative terminal of voltage source 2008 meets GND；Another input of the output termination NAND gate 2014 of voltage comparator 2009；The input of the output termination not gate 2015 of NAND gate 2014；The control end of the output termination analog switch 2018 of not gate 2015；

ITRIP connects positive input terminal and the positive input terminal of voltage comparator 2013 of voltage comparator 2010；The negative input end just terminating voltage comparator 2010 of voltage source 2011；The negative terminal of voltage source 2011 meets GND；The negative input end just terminating voltage comparator 2013 of voltage source 2012；The negative terminal of voltage source 2012 meets GND；0 selection end and one of them input of NAND gate 2016 of the output termination analog switch 2018 of voltage comparator 2010；

Another input of the output termination NAND gate 2016 of voltage comparator 2013；The input of the output termination not gate 2017 of NAND gate 2016；1 selection end of the output termination analog switch 2018 of not gate 2017；The input of the fixing termination not gate 2019 of analog switch 2018；The outfan of not gate 2019 is as ICON.

The operation principle of following description above-described embodiment and key parameter value:

Unless HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 and PFCINP are low level, otherwise A point output high level；When D point voltage is more than the voltage of voltage source 2008, C exports high level, otherwise C point output low level；

The clamp voltage design of Zener diode 2005 is 6.4V, and resistance 2004 is designed as 20k Ω, then produce the stable 6.4V voltage not affected with VCC voltage pulsation at B point；PTC resistor 2006 is designed as 10k Ω when 25 DEG C, 20k Ω when 100 DEG C；Resistance 2007 is designed as 44k Ω, and voltage source 2008 is designed as 2V, then, below 100 DEG C, voltage comparator 2009 output low level, more than 100 DEG C, voltage comparator 2009 exports high level；According to practical application needs, the temperature of trigger voltage comparator 2009 exporting change can be controlled by regulating the value of resistance 2007；

When A point is high level with C point simultaneously, the control end of analog switch 2018 is high level, and otherwise the control end of analog switch 2018 is low level；

Voltage source 2011 is designed as 0.5V, and voltage source 2012 is designed as 0.7V, it is possible to be designed as the voltage higher than 0.5V, such as 0.6V；

When the control end of analog switch 2018 is high level, if the voltage of ITRIP makes ICON output low level higher than 0.5V the most at once, otherwise ICON keeps high level constant；

When the control end of analog switch 2018 is low level, the voltage of ITRIP necessarily be greater than 0.7V, and after the time delay of NAND gate 2016 and not gate 2017, just can make ICON output low level, and otherwise ICON keeps high level constant；The size of NAND gate 2016 and not gate 2017 can be designed as technique and allows 3～5 times of minimum dimension, is used for regulating time delay.

From the technical scheme of above-described embodiment, the SPM that the utility model proposes is completely compatible with existing SPM, can directly be replaced with existing SPM, and by the temperature of automatic decision SPM, after arriving the temperature spot being easiest to produce false triggering, having an opportunity to cause the threshold voltage of the time period raising ITRIP of false triggering, thus ITRIP is greatly reduced at high temperature by the probability of false triggering, by above mechanism, make the SPM that the utility model proposes equal energy reliably working in the range of total temperature.

The technical solution of the utility model is described in detail above in association with accompanying drawing, the utility model proposes a kind of new SPM, on the premise of can the most normally can working guaranteeing SPM, effectively reduce SPM at high temperature by the probability of false triggering.

The foregoing is only preferred embodiment of the present utility model, be not limited to this utility model, for a person skilled in the art, this utility model can have various modifications and variations.All within spirit of the present utility model and principle, any modification, equivalent substitution and improvement etc. made, within should be included in protection domain of the present utility model.

Claims

1. a SPM, it is characterised in that including:

On three-phase, under brachium pontis signal input part, three-phase, brachium pontis signal input part, three-phase low reference voltage end, current detecting end and PFC control input；

HVIC manages, it is provided with on described HVIC pipe and is respectively connecting on described three-phase the terminals of brachium pontis signal input part under brachium pontis signal input part and described three-phase, and correspond to the first port of described current detecting end and control the second port of input corresponding to described PFC, described first port is connected with described current detecting end by connecting line, and described second port controls input by connecting line with described PFC and is connected；

Sampling resistor, described three-phase low reference voltage end and described current detecting end be connected to the first end of described sampling resistor, and the second end of described sampling resistor is connected to the low-pressure area power supply negative terminal of described SPM；

Adaptive circuit, the power supply positive pole of described adaptive circuit and negative pole are respectively connecting to low-pressure area power supply anode and the negative terminal of described SPM, the first input end of described adaptive circuit, the corresponding end that second input and the 3rd input are respectively connecting on described three-phase in brachium pontis signal input part, the four-input terminal of described adaptive circuit, the corresponding end that 5th input and the 6th input are respectively connecting under described three-phase in brachium pontis signal input part, 7th input of described adaptive circuit is connected to described second port, 8th input of described adaptive circuit is connected to described first port, the outfan of described adaptive circuit is as the Enable Pin of described HVIC pipe；

SPM the most according to claim 1, it is characterised in that:

Described adaptive circuit is when the input signal of described first input end to described 7th input is all low level, if the value of the input signal of described 8th input is more than or equal to described first setting value, then export the enable signal of the first level, to forbid that described HVIC pipe works；Otherwise, the enable signal of output second electrical level, to allow described HVIC pipe to work；

SPM the most according to claim 1, it is characterised in that described adaptive circuit includes:

SPM the most according to claim 1, it is characterised in that be additionally provided with the signal output part of PFC drive circuit on described HVIC pipe, described SPM also includes:

First power switch pipe and the first diode, the anode of described first diode is connected to the emitter stage of described first power switch pipe, the negative electrode of described first diode is connected to the colelctor electrode of described first power switch pipe, the colelctor electrode of described first power switch pipe is connected to the anode of the second diode, the negative electrode of described second diode is connected to the high voltage input of described SPM, the base stage of described first power switch pipe is connected to the signal output part of described PFC drive circuit, the emitter stage of described first power switch pipe is as the PFC low reference voltage end of described SPM, the colelctor electrode of described first power switch pipe is as the PFC end of described SPM.

SPM the most according to any one of claim 1 to 4, it is characterised in that also include: boostrap circuit, described boostrap circuit includes:

First bootstrap diode, the anode of described first bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described first bootstrap diode is connected to the U phase higher-pressure region power supply anode of described SPM；

Second bootstrap diode, the anode of described second bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described second bootstrap diode is connected to the V phase higher-pressure region power supply anode of described SPM；

3rd bootstrap diode, the anode of described 3rd bootstrap diode is connected to the low-pressure area power supply anode of described SPM, and the negative electrode of described 3rd bootstrap diode is connected to the W phase higher-pressure region power supply anode of described SPM.

SPM the most according to any one of claim 1 to 4, it is characterised in that also include:

Bridge arm circuit on three-phase, the signal output part of corresponding phase during the input of bridge arm circuit is connected to the three-phase high-voltage district of described HVIC pipe in each phase in bridge arm circuit on described three-phase；

Bridge arm circuit under three-phase, the signal output part of corresponding phase during the input of bridge arm circuit is connected to the three-phase low-voltage district of described HVIC pipe under each phase in bridge arm circuit under described three-phase.

SPM the most according to claim 6, it is characterised in that in described each phase, bridge arm circuit includes:

Second power switch pipe and the 3rd diode, the anode of described 3rd diode is connected to the emitter stage of described second power switch pipe, the negative electrode of described 3rd diode is connected to the colelctor electrode of described second power switch pipe, the colelctor electrode of described second power switch pipe is connected to the high voltage input of described SPM, the base stage of described second power switch pipe is as the input of bridge arm circuit in described each phase, and the emitter stage of described second power switch pipe is connected to the higher-pressure region power supply negative terminal of described SPM correspondence phase.

SPM the most according to claim 7, it is characterised in that under described each phase, bridge arm circuit includes:

3rd power switch pipe and the 4th diode, the anode of described 4th diode is connected to the emitter stage of described 3rd power switch pipe, the negative electrode of described 4th diode is connected to the colelctor electrode of described 3rd power switch pipe, the colelctor electrode of described 3rd power switch pipe is connected to the anode of described 3rd diode in the upper bridge arm circuit of correspondence, the base stage of described 3rd power switch pipe is as the input of bridge arm circuit under described each phase, and the emitter stage of described 3rd power switch pipe is as the low reference voltage end of the corresponding phase of described SPM.

9., according to the SPM described in claim 7 or 8, it is characterised in that the voltage of the high voltage input of described SPM is 300V, connect between anode and the negative terminal of each phase higher-pressure region power supply of described SPM and have filter capacitor.

10. an air-conditioner, it is characterised in that including: SPM as claimed in any one of claims 1-9 wherein.