CN205051678U - A circuit structure for reducing microlock medium oscillator phase noise - Google Patents
A circuit structure for reducing microlock medium oscillator phase noise Download PDFInfo
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- CN205051678U CN205051678U CN201520545372.2U CN201520545372U CN205051678U CN 205051678 U CN205051678 U CN 205051678U CN 201520545372 U CN201520545372 U CN 201520545372U CN 205051678 U CN205051678 U CN 205051678U
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- Prior art keywords
- circuit structure
- microlock
- reducing
- phase noise
- oscillator
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- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 230000006872 improvement Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Radar Systems Or Details Thereof (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
The utility model discloses a circuit structure for reducing microlock medium oscillator phase noise, loop through phase discriminator, loop filter, voltage controlled oscillator, merit including reference signal and divide the ware to export, its characterized in that: circuit structure include that reference signal loops through frequency multiplier, first wave filter and inserts first detector and oscillator down coversion and carry out the phase locking and reduce the frequency dividing ratio, insert the phase discriminator looks of reflecting through the second wave filter again. A circuit structure for reducing microlock medium oscillator phase noise, owing to adopt foretell circuit structure, the utility model discloses reduce the phase noise of oscillator. On circuit design, the utility model discloses changing circuitry's planar structure does not debug the convenience, and reliable and simple can obtain extensive application in the microwave circuit design.
Description
Technical field
The utility model relates to microlock dielectric oscillator, particularly a kind of circuit structure for reducing microlock dielectric oscillator phase noise.
Background technology
Microlock dielectric oscillator is generally used as the local vibration source of fixed frequency, and dielectric resonator Q value is high, as frequency stabilization element, has the features such as frequency stability is high, noise is low, volume is little, price is low.It has the advantages that frequency stability is high, phase noise is low, integrated level is high.Therefore, be widely used in the field such as radar, communication.
In the ideal case, the output of oscillator is single-frequency, can represent with an independent straight line.But in fact there is noise jamming and make output spectrum with " skirt " in oscillator, is centered around around carrier frequency.Produce mutual mixing phenomenon, reduce the signal to noise ratio of receiver, the performance of deteriorates reception machine.
For the problems referred to above, provide a kind of novel improvement circuit, the phase noise reducing microlock dielectric oscillator is the problem that prior art needs to solve.
Utility model content
Technical problem to be solved in the utility model is, provides a kind of circuit structure for reducing microlock dielectric oscillator phase noise, reduces the phase noise of microlock dielectric oscillator, reduces the interference to receiver.
For achieving the above object, the technical solution of the utility model is, a kind of circuit structure for reducing microlock dielectric oscillator phase noise, comprise reference signal to be exported by phase discriminator, loop filter, voltage controlled oscillator, power splitter successively, it is characterized in that: described circuit structure comprises reference signal and carries out phase-locked reduction frequency dividing ratio by frequency multiplier, the first filter access frequency mixer and oscillator down-conversion successively, then carries out phase demodulation through the second filter access phase discriminator.
Described power splitter is leaded up to the 3rd filter and is exported, another road access frequency mixer.
Described frequency multiplier accesses the first filter by amplifier.
Described frequency multiplier adopts snap-off diode.
The circuit board soldering of described circuit structure, in metallic cavity, guarantees that ground connection is good.
For reducing a circuit structure for microlock dielectric oscillator phase noise, owing to adopting above-mentioned circuit structure, the utility model reduces the phase noise of oscillator.In circuit design, the utility model does not change the planar structure of circuit, and debugging is convenient, simple, can be widely used in microwave circuits.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail;
Fig. 1 is the structured flowchart of a kind of circuit structure for reducing microlock dielectric oscillator phase noise of the utility model;
In FIG, 1, reference signal; 2, frequency multiplier; 3, the first filter; 4, frequency mixer; 5, phase discriminator; 6, loop filter; 7, voltage controlled oscillator; 8, power splitter; 9, the second filter; 10, the 3rd filter.
Embodiment
As shown in Figure 1, the utility model is comprised reference signal 1 and is exported by phase discriminator 5, loop filter 6, voltage controlled oscillator 7, power splitter 8 successively, it is characterized in that: described circuit structure comprises reference signal 1 and accesses frequency mixer 4 by frequency multiplier 2, first filter 3 successively and carry out phase-locked reduction frequency dividing ratio with oscillator down-conversion, then access phase discriminator 5 through the second filter 9 and carry out phase demodulation.Power splitter 8 is leaded up to the 3rd filter 10 and is exported, another road access frequency mixer 4.Frequency multiplier 2 accesses the first filter 3 by amplifier.Frequency multiplier 2 adopts snap-off diode.
The utility model improves the phase noise of oscillator by the frequency dividing ratio reducing digital frequency divider, reference signal is by the high snap-off diode frequency multiplication of shg efficiency, take out desired signal through sound table the first filter 3, be mixed to lower frequency with oscillator, then carry out phase demodulation with reference signal.In frequency multiplication process, because the harmonic power exported is less, need amplify signal.For the design of amplifier, preferably build with the bipolar transistor that flicker noise is low.Though one chip amplifier is easy to use, noise is large, and noise floor can be elevated, and avoids using.Whole circuit structure is simple, and sheet material is Rogers 5880.Circuit board soldering, in metallic cavity, guarantees abundant ground connection, does not have air-gap in the middle of circuit board.
By reference to the accompanying drawings the utility model is exemplarily described above; obvious the utility model specific implementation is not subject to the restrictions described above; as long as have employed the various improvement that technical solutions of the utility model are carried out; or directly apply to other occasion, all within protection range of the present utility model without improving.
Claims (5)
1. the circuit structure for reducing microlock dielectric oscillator phase noise, comprise reference signal (1) to be exported by phase discriminator (5), loop filter (6), voltage controlled oscillator (7), power splitter (8) successively, it is characterized in that: described circuit structure comprises reference signal (1) and carries out phase-locked reduction frequency dividing ratio by frequency multiplier (2), the first filter (3) access frequency mixer (4) with oscillator down-conversion successively, then carries out phase demodulation through the second filter (9) access phase discriminator (5).
2. a kind of circuit structure for reducing microlock dielectric oscillator phase noise according to claim 1, it is characterized in that: described power splitter (8) is leaded up to the 3rd filter (10) and exported, another road access frequency mixer (4).
3. a kind of circuit structure for reducing microlock dielectric oscillator phase noise according to claim 1, is characterized in that: described frequency multiplier (2) accesses the first filter (3) by amplifier.
4. a kind of circuit structure for reducing microlock dielectric oscillator phase noise according to claim 3, is characterized in that: described frequency multiplier (2) adopts snap-off diode.
5. a kind of circuit structure for reducing microlock dielectric oscillator phase noise according to claim 1, is characterized in that: the circuit board soldering of described circuit structure, in metallic cavity, guarantees that ground connection is good.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520545372.2U CN205051678U (en) | 2015-07-23 | 2015-07-23 | A circuit structure for reducing microlock medium oscillator phase noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520545372.2U CN205051678U (en) | 2015-07-23 | 2015-07-23 | A circuit structure for reducing microlock medium oscillator phase noise |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205051678U true CN205051678U (en) | 2016-02-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520545372.2U Expired - Fee Related CN205051678U (en) | 2015-07-23 | 2015-07-23 | A circuit structure for reducing microlock medium oscillator phase noise |
Country Status (1)
| Country | Link |
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| CN (1) | CN205051678U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107144716A (en) * | 2016-03-01 | 2017-09-08 | 三美电机株式会社 | Sensor device and semiconductor device |
-
2015
- 2015-07-23 CN CN201520545372.2U patent/CN205051678U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107144716A (en) * | 2016-03-01 | 2017-09-08 | 三美电机株式会社 | Sensor device and semiconductor device |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160224 |
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| CF01 | Termination of patent right due to non-payment of annual fee |