CN204859189U - High -speed CMOS single scale intergration optical receiver with single -ended slip branch of full bandwidth - Google Patents

High -speed CMOS single scale intergration optical receiver with single -ended slip branch of full bandwidth Download PDF

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CN204859189U
CN204859189U CN201520521906.8U CN201520521906U CN204859189U CN 204859189 U CN204859189 U CN 204859189U CN 201520521906 U CN201520521906 U CN 201520521906U CN 204859189 U CN204859189 U CN 204859189U
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circuit
bandwidth
transfer difference
ended transfer
amplifier
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谢生
高谦
毛陆虹
陶希子
吴思聪
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Tianjin University
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Tianjin University
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Abstract

The utility model discloses a high -speed CMOS single scale intergration optical receiver with single -ended slip branch of full bandwidth, include: high bandwidth regulation type cascode strides and hinders the amplifier for turn into voltage signal with the current signal of photoelectric detector output, go on tentatively enlargedly, the single -ended slip that has the negative electricity capacitive circuit divides the ware for realize single -endedly to difference conversion, improvement bandwidth and enlarged voltage signal, the unit is eliminated to the direct current offset, is used for eliminating single -ended slip divides the alternating expression active feedback limiting amplifier's that the non -equilibrium signal of ware output arouses direct current offset, makes alternating expression active feedback limiting amplifier common mode level unanimous, alternating expression active feedback limiting amplifier, be used for with high bandwidth regulation type cascode strides the voltage signal who hinders the amplifier output and enlargies to the required voltage level of digital process unit, the output buffer stage for provide the driving force. The utility model discloses in the raising circuitry gain, expanded the work bandwidth, overcome the not enough of prior art.

Description

There is the high-speed cmos monolithic integrated photoreceiver of full bandwidth single-ended transfer difference
Technical field
The utility model relates to optical fiber telecommunications system and light network field, particularly relates to a kind of high-speed cmos monolithic integrated photoreceiver based on adjustment type cascade (RGC) circuit structure and full bandwidth single-ended transfer difference.
Background technology
Along with the demand of human society to the network bandwidth and data traffic is doubled and redoubled.Ultrahigh speed, vast capacity Fibre Optical Communication Technology for main line network transmission make a breakthrough, but between the rack room, circuit board of optical-fiber network switching node, the short haul connection such as chip chamber and chip internal, still adopt electronic information process and exchanged form at present, limit the further lifting of information processing rate.Therefore, in short distance, very short distance, adopting light network to substitute electrical interconnection becomes inexorable trend.Optical fiber telecommunications system is carrier wave with photon, using optical fiber as transmission medium, by opto-electronic conversion, carrys out the communication system of transmission information with photon, and it mainly comprises optical sender, repeater and optical receiver three part.The effect of optical receiver is receiving optical signals and converts thereof into the required signal of telecommunication.Trans-impedance amplifier (TIA) is positioned at optical receiver circuit foremost, and its effect is by the photoelectric current amplification of photodetector output, is converted to voltage signal.The performance of optical receiver determines the receiving velocity of optical communication system, and trans-impedance amplifier is as the core circuit of optical receiver AFE (analog front end), and the performance that its technical indicator directly affects optical receiver systems is good and bad.
Traditional cmos photoreceiver front-end circuit can be divided into two classes by technical characterstic: high bandwidth optical receiver and low noise optical receiver.In the front-end circuit of high bandwidth optical receiver, be generally adopt reduction input impedance and frequency acquisition and tracking to expand bandwidth.Wherein, reduce the mode of input impedance and often adopt to regulate input junction device size or introduce feedback arrangement and realize, this usually with sacrifice circuit noiseproof feature for cost.The input impedance of low noise optical receiver then mainly through increasing front-end circuit realizes.Obviously, the acquisition of low noise is to sacrifice bandwidth for cost.In the design process of trans-impedance amplifier, bandwidth and noise are conflicting, are difficult to search out both all excellent schemes.
Utility model content
The utility model provides a kind of high-speed cmos monolithic integrated photoreceiver with full bandwidth single-ended transfer difference, and the utility model, while lifting circuit gain, has been expanded bandwidth of operation, overcome the deficiencies in the prior art, described below:
Have a high-speed cmos monolithic integrated photoreceiver for full bandwidth single-ended transfer difference, described high-speed cmos monolithic integrated photoreceiver comprises:
High bandwidth adjustment type cascade trans-impedance amplifier, is converted into voltage signal for the current signal exported by photodetector, tentatively amplifies;
With the single-ended transfer difference device of negative capacitance circuit, single-ended to differential conversion for realizing, improve bandwidth sum amplification voltage signal;
Direct current offset eliminates unit, and the direct current offset of the alternating expression active feedback limiting amplifier that the non-equilibrium signal exported for eliminating described single-ended transfer difference device causes, makes alternating expression active feedback limiting amplifier common mode electrical level consistent;
Described alternating expression active feedback limiting amplifier, is amplified to digital processing element required voltage level for the voltage signal exported by described high bandwidth adjustment type cascade trans-impedance amplifier;
Export buffer stage, for providing driving force.
Wherein, described high bandwidth adjustment type cascade trans-impedance amplifier is made up of the cascade pole branch road of Butterworth LC staircase match network, common gate amplifying circuit and band inductance.
Described direct current offset is eliminated unit and is arranged on described with between the single-ended transfer difference device of negative capacitance circuit, described alternating expression active feedback limiting amplifier.
The described single-ended transfer difference device with negative capacitance circuit comprises: single-ended transfer difference circuit and negative capacitance circuit.
Wherein, described negative capacitance circuit is arranged on described single-ended transfer difference circuit, described direct current offset is eliminated between unit.
The beneficial effect of the technical scheme that the utility model provides is:
1, in trans-impedance amplifier circuit structure, adopt the cascade of band inductance extremely to substitute the common-source circuits of traditional RGC structure, the equivalent transconductance of trans-impedance amplifier can be increased, again maskable the Miller effect, thus effectively alleviate the contradiction between bandwidth sum gain.
2, introduce Butterworth LC staircase match network in trans-impedance amplifier front end, effectively can reduce the impact of photodetector electric capacity on trans-impedance amplifier, can also equivalent input noise be reduced simultaneously.
3, in trans-impedance amplifier and single-ended transfer difference circuit, introduce an inductance respectively, make the parasitic capacitance in itself and circuit form two π type broadband matching networks.By described matching network, by the parasitic capacitance in circuit structure and inductance generation resonance, each point impedance can be reduced, limit pulled to high frequency treatment, thus expansion bandwidth of operation.
4, compared with traditional single-ended transfer difference structure realized based on high pass filter, the novel single-end slip parallel circuit that the utility model proposes, can realize the differential conversion of full bandwidth, promotes bandwidth sum circuit gain.Compared with symmetrical differential conversion circuit, the single-ended transfer difference structure that the utility model proposes can reduce the usage quantity of inductance.
5, introduce negative capacitance circuit at the output of single-ended transfer difference structure, reduce the speed of roll-offing of high-frequency gain, thus effective lifting-three dB bandwidth.
6, use direct current offset to eliminate unit, ensure that the common mode electrical level of limiting amplifier is consistent.Limiting amplifier progression elects three grades as, and introduces alternating expression active backfeed circuit, effectively suppresses the decline of circuit bandwidth.
In sum, by adopting the novel RGC structure that the utility model proposes and single-ended transfer difference technology can realize standard CMOS monolithic integrated photoreceiver at a high speed.
Accompanying drawing explanation
Fig. 1 gives the structured flowchart of the optical receiver designed by the utility model;
Fig. 2 gives the circuit diagram of traditional RGC trans-impedance amplifier;
Fig. 3 gives the circuit diagram of the high bandwidth RGC trans-impedance amplifier with single-ended transfer difference circuit and negative capacitance circuit;
Fig. 4 gives the equivalent small signal circuit figure of novel high bandwidth RGC trans-impedance amplifier;
Fig. 5 gives direct current offset and eliminates unit (DCOffsetCancellationUnit) circuit diagram.
In accompanying drawing, being listed as follows of parts:
1: high bandwidth adjustment type cascade trans-impedance amplifier; 2: with the single-ended transfer difference device of negative capacitance circuit;
3: direct current offset eliminates unit; 4: alternating expression active feedback limiting amplifier;
5: export buffer stage.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearly, below the utility model execution mode is described in further detail.
Embodiment 1
Have a high-speed cmos monolithic integrated photoreceiver for full bandwidth single-ended transfer difference, see Fig. 1, this high-speed cmos monolithic integrated photoreceiver comprises:
High bandwidth adjustment type cascade trans-impedance amplifier 1, is converted into voltage signal for the current signal exported by photodetector, tentatively amplifies;
With the single-ended transfer difference device 2 of negative capacitance circuit, single-ended to differential conversion for realizing, improve bandwidth sum amplification voltage signal;
Direct current offset eliminates unit 3, and the direct current offset of the alternating expression active feedback limiting amplifier 4 that the non-equilibrium signal exported for eliminating single-ended transfer difference device 2 causes, makes the common mode electrical level of alternating expression active feedback limiting amplifier 4 consistent;
Alternating expression active feedback limiting amplifier 4, is amplified to digital processing element required voltage level for the voltage signal exported by high bandwidth adjustment type cascade trans-impedance amplifier 1;
Export buffer stage 5, for providing driving force.
Wherein, high bandwidth adjustment type cascade trans-impedance amplifier 1 is made up of the cascade pole branch road of Butterworth LC staircase match network, common gate amplifying circuit and band inductance.
Direct current offset is eliminated unit 3 and is arranged on between the single-ended transfer difference device 2 of negative capacitance circuit, alternating expression active feedback limiting amplifier 4.
High bandwidth adjustment type cascade trans-impedance amplifier 1, respectively introduce an inductance with the single-ended transfer difference device 2 of negative capacitance circuit, form two π type broadband matching networks.By matching network, by the parasitic capacitance in circuit structure and inductance generation resonance, each point impedance can be reduced, limit pulled to high frequency treatment, thus expansion bandwidth of operation.
Preferably, alternating expression active feedback limiting amplifier 4 is three grades of concatenated in order.
Single-ended transfer difference device 2 with negative capacitance circuit comprises: single-ended transfer difference circuit and negative capacitance circuit.
Wherein, single-ended transfer difference circuit, by a single-ended transfer difference transducer, realizes single-ended transfer difference; Single-ended transfer difference circuit, forming π type broadband matching network by introducing inductance, promoting the bandwidth of trans-impedance amplifier.
Wherein, negative capacitance circuit is arranged on single-ended transfer difference circuit, direct current offset is eliminated between unit 3.
In sum, the utility model adopts the basic structure of adjustment type cascade (RGC) circuit as trans-impedance amplifier of band inductance, expand bandwidth of operation by introducing Butterworth LC ladder network and π type broadband matching network, also reduce equivalent input noise simultaneously.Adopt novel single-ended transfer difference circuit, achieve the differential conversion of full bandwidth, while lifting circuit gain, decrease inductance quantity and chip area.In addition, introduce negative capacitance circuit, reduce high-frequency gain and to roll-off speed, promote bandwidth of operation further.
Embodiment 2
In order to clearly describe structure and the operation principle of the high bandwidth RGC trans-impedance amplifier 1 that the utility model proposes, outstanding high bandwidth RGC trans-impedance amplifier 1 designed by the utility model compares the plurality of advantages of traditional RGC trans-impedance amplifier, first simply describing the operation principle of traditional RGC trans-impedance amplifier below, then reducing from expanding bandwidth sum the operation principle that noise two aspect describes high bandwidth RGC trans-impedance amplifier 1 in detail.
The utility model has fully utilized following four kinds of technology to expand bandwidth, and namely cascade feedback path reduces input impedance, miller capacitance " shielding " effect, Butterworth LC staircase match network and π type broadband matching network.Wherein, Butterworth LC staircase match network effectively can reduce equivalent input noise current.
Fig. 2 gives the basic structure of traditional RGC trans-impedance amplifier.This structure is on the basis of common grid amplifier, by increasing an active feedback path between source electrode and drain electrode, reduces circuit input impedance, thus the pole location of adjustment limiting bandwidth, reach the object expanding bandwidth.Wherein, M 21for common bank tube, M 22for providing the common source pipe of active feedback.I pdfor the equivalent current source of photodetector, and C pdfor the equivalent parasitic capacitances of photodetector.
Tradition RGC trans-impedance amplifier has the following advantages:
(1) direct current biasing is stablized
R 22and M 22provide common gate amplifying circuit (by R 21, M 21and R 2sform) bias voltage, without the need to extra biasing circuit.And due to M 22provide a negative feedback path, this is biased highly stable.
(2) input impedance is little
Can be obtained by the small-signal equivalent circuit of RGC trans-impedance amplifier, its input impedance is:
Z i n = V i n I i n = 1 g m 1 ( 1 + g m 2 R 22 ) - - - ( 1 )
Wherein, g m1and g m2represent M respectively 21and M 22mutual conductance.Obviously, the input impedance of RGC trans-impedance amplifier is than the input impedance (1/g of conventional cathode-input amplifier m1) reduce 1+g m2r 22doubly.
Fig. 3 gives the circuit diagram of the broadband RGCTIA of band single-ended transfer difference circuit new construction.Whole circuit comprises three parts: novel RGCTIA, single-ended transfer difference circuit and negative capacitance circuit (by high bandwidth RGC trans-impedance amplifier 1, combining with the single-ended transfer difference circuit 2 of negative capacitance circuit).The effect of this circuit receives photodetector I pdthe current signal exported, amplifies current signal, is converted to differential voltage signal output.
Wherein, novel RGCTIA mainly comprises: cascade pole branch road three part of Butterworth LC staircase match network, common gate amplifying circuit and band inductance.Inductance L 31a termination input port I in, the other end and transistor M 32grid be connected; Inductance L 32one end connect transistor M 32grid, the other end and transistor M 31source electrode and resistance R 3Sone end connects, resistance R 3Sother end ground connection; Transistor M 31drain electrode and resistance R 31be connected to power supply, grid and transistor M 33drain electrode is connected; M 33drain electrode connecting resistance R 32, grid meets bias voltage V b, resistance R 32another termination power; Transistor M 33source electrode connect inductance L 33; Inductance L 33another termination transistor M 32drain electrode, M 32source ground, transistor M 32grid and inductance L 31and inductance L 32be connected.
The operation principle of novel RGCTIA: photodetector I pdthe photoelectric current exported flows into from input, through amplifying, exports with voltage signal at output.Transistor M 32, resistance R 32with transistor M 33the cascade pole of composition is amplified to common gate device M by anti-phase for input signal 31grid, thus improve transistor M 31equivalent transconductance.Next novel RGCTIA circuit described in the utility model is analyzed from the following aspects.
(1) transistor M 31equivalent transconductance G mfor:
G m＝g m1(1+g m2(g m3+g mb3)r 02r 03R 32)(2)
Wherein, g m1, g m2, g m3m respectively 31, M 32, M 33small-signal transconductance; R 32resistance R 32resistance.R 02, r 03m respectively 32, M 33output resistance.
Compare the traditional RGC circuit shown in Fig. 2, G m=g m1(1+g m2r 22), the utility model proposes the equivalent transconductance G of trans-impedance amplifier circuit mlarger, thus circuit has lower input impedance, and input limit can be pulled to high frequency treatment, thus working band is wider.
(2) RGC trans-impedance amplifier described in the utility model can the impact of effective " shielding " miller capacitance.
From the circuit analysis of traditional RGC structure, its-three dB bandwidth can be expressed as
f - 3 d B = 1 1 + sR 21 [ ( 1 + g m 1 g m 2 ) C g d 1 + C g d 2 + C L ] - - - ( 3 )
Wherein, s represents a plural number in transfer function; C gd1, C gd2be respectively transistor M 31, M 32grid source electric capacity; C lfor the input capacitance of load capacitance or late-class circuit.
And cascade described in the utility model feedback RGC trans-impedance amplifier-three dB bandwidth is
f - 3 d B = 1 1 + sR 31 ( C g d 1 + C g d 2 + C L ) - - - ( 4 )
Comparison expression (3) and (4) known, due to the impact of the Miller effect, the C of traditional RGC structure gd1item is than C described in the utility model gd1large (the 1+g of item m1/ g m2) doubly.This is because cascade feedback arrangement acts on " shielding " of the Miller effect.Therefore, novel RGC structural rate tradition RGC circuit described in the utility model has higher bandwidth of operation.
(3) the Butterworth LC staircase match network that input is introduced has two effects: expand bandwidth sum and reduce equivalent input noise current.The equivalent small signal circuit of novel RGCTIA as shown in Figure 4, is now analyzed as follows:
Passive matching network, when not worsening other parameters, can improve the restriction of gain-bandwidth.By a passive matching network of two-port, the maximum gain bandwidth product that makes promotes four times.Therefore, LC staircase match network (Butterworth matching network) just can be utilized under the condition maximizing gain flatness to promote bandwidth significantly.
In addition, by En-In noise model, (this model refers to that the internal noise of amplifier can with the zero impedance voltage generator En being connected on input, and be connected in parallel on the current feedback circuit In that input has an infinite-impedance and represent, both coefficient correlations be r) analyze known, band matching network RGCTIA in inductance L 31on the impact reducing equivalent input noise current be:
|i n,eq| 2＝(1-ω 2L 31C pd) 2I n 2+ω 2C pd 2E n 2(5)
Wherein, C pdrepresent the junction capacitance of photodetector; | i n, eq| 2represent equivalent noise current spectrum density, unit is A 2/ H z; ω represents angular frequency.
And the equivalent input noise not with matching network RGCTIA is:
|i n,eq| 2＝I n 2+ω 2C pd 2E n 2(6)
L 32effective inductance be L (32, eff)=(L 32/ (1+g m32r 31)), wherein, g m32m 32small-signal transconductance; L (32, eff)its value is relatively little, therefore, on reducing the impact of equivalent input noise current relative to L 31smaller.Known based on above-mentioned analysis, the equivalent input noise current with matching network TIA is lower.
(4) when at trans-impedance amplifier transistor M 32with M 33between introduce inductance L 33, at the transistor M of single-ended transfer difference circuit 35grid and the output node of trans-impedance amplifier between introduce inductance L 34after, can inductance L be utilized 34form π type broadband matching network, by parasitic capacitance " inspiration " network, thus reach the object of secondary spread spectrum.
Inductance L is increased at active feedback path 33after, inductance L 33, transistor M 32gate leakage capacitance C gd2and transistor M 33grid source electric capacity C gs3form first π type broadband matching network.Inductance L is introduced in single-ended transfer difference circuit 34, this inductance L 34can with transistor M 35gate leakage capacitance C gd5with grid source electric capacity C gs5, and transistor M 31gate leakage capacitance C gd1form another π type broadband matching network.By above-mentioned two π type broadband matching networks, the parasitic capacitance in trans-impedance amplifier circuit and two inductance generation resonance can be made, reduce each joint impedance, limit is pulled to high frequency treatment, thus effective spread bandwidth.
Known by above-mentioned analysis, the bandwidth of operation of novel RGC trans-impedance amplifier can significantly promote, and also reduces equivalent input noise simultaneously.
Because trans-impedance amplifier is Single-end output, in order to suppress common-mode noise, needing to be converted into fully differential and exporting, so the utility model proposes a kind of novel single-end slip parallel circuit with negative capacitance circuit, being next described in greater detail.
As shown in Figure 3 (the second dotted line frame), the single-ended transfer difference task of trans-impedance amplifier can be completed by a single-ended transfer difference transducer, instead of adopt symmetric circuit structure to realize differential conversion.The output signal of trans-impedance amplifier and resistance R fand inductance L 34one end connect, inductance L 34the other end be connected to transistor M 35grid, resistance R fthe other end and M 34source electrode, M 35drain electrode and M 36grid be connected, transistor M 35source ground.Transistor M 34grid meet power vd D, M 34drain electrode be connected to resistance R 33one end, resistance R 33another termination power vd D.M 36source ground, transistor M 36grid meet transistor M 34source electrode, transistor M 36drain electrode connecting resistance R 34, resistance R 34another termination power vd D.Wherein, transistor M 34with resistance R 33the common grid level circuit formed, with transistor M 36with resistance R 34the common-source stage circuit realiration two ends output signal formed is anti-phase.
Designed by the utility model, single-ended transfer difference circuit has the following advantages: 1, compared with the symmetrical circuit realiration differential conversion of employing, the use of three inductance can be reduced, thus chip area is reduced, and export as fully differential signal, adopting the differential conversion of symmetrical circuit realiration real is pseudo-differential, because the other end does not have signal to input; 2, forming π type broadband matching network by introducing inductance, promoting the bandwidth of trans-impedance amplifier further; 3, the single-ended transfer difference circuit that the utility model proposes is different from the change-over circuit based on high pass filter, and it can realize the transfer of data of Whole frequency band; 4, by transistor M 34with resistance R 33the common grid level circuit formed, with transistor M 36with resistance R 34the common-source circuits formed promotes gain.
As shown in Figure 3 (the 3rd dotted line frame), eliminate between unit 3 at single-ended transfer difference circuit and direct current offset and introduce a negative capacitance circuit, two signals that single-ended transfer difference circuit exports are connected on transistor M respectively 37with transistor M 38drain electrode, transistor M 37grid and transistor M 38drain electrode be connected, and transistor M 38grid and transistor M 37drain electrode be connected.At transistor M 37with transistor M 38between and an electric capacity C, and transistor M 37with transistor M 38source electrode be then connected with current source.Can be obtained by small-signal analysis, the equiva lent impedance of negative capacitance circuit is:
Z N C ≅ - 1 s C g m N C + s ( C g s N C + 2 C ) g m N C - - - ( 7 )
Wherein, g mNCand C gsNCrepresent transistor M respectively 37(or M 38) mutual conductance and grid source electric capacity.
From formula (6), the output impedance of negative capacitance circuit can produce a high frequency peaks, and the impedance of DC condition is infinitely great, can not have an impact to DC current gain, so negative capacitance circuit can maintain under the constant prerequisite of DC current gain, reduce high-frequency gain to roll-off speed, promote bandwidth of operation.Compare passive inductance peaking technique, the scheme of the utility model design can effectively reduce chip area.
Fig. 5 is the circuit diagram that direct current offset eliminates unit (DCOffsetCancellationUnit) 3.Trans-impedance amplifier output asymmetrical signals easily causes the direct current offset of limiting amplifier.For this reason, the utility model inserts a direct current offset and eliminates unit 3 between trans-impedance amplifier and limiting amplifier.Resistance R 51aa termination supply voltage VDD, another termination transistor M 51adrain electrode, and with crystal M 52bdrain electrode be connected, transistor M 51agrid meet input In 5a, source electrode and transistor M 52a, transistor M 52bwith transistor M 51bsource electrode be connected, and with tail current source M 53drain electrode be connected, tail current source M 53source ground, grid meets bias voltage V b5.Transistor M 52adrain electrode connecting resistance R 51band transistor M 51bdrain electrode, grid connecting resistance R 5awith electric capacity C 5aone end, electric capacity C 5aother end ground connection, resistance R 5aanother termination input In 5a.Resistance R 51ba termination supply voltage VDD, another termination transistor M 51bdrain electrode, and with transistor M 52adrain electrode be connected, transistor M 51bgrid meet input In 5b, transistor M 52bdrain electrode connecting resistance R 51aand transistor M 51adrain electrode, grid connecting resistance R 5bwith electric capacity C 5bone end, electric capacity C 5bother end ground connection, resistance R 5banother termination input In 5b.
The operation principle that direct current offset eliminates unit 3 is as follows: a road signal In of input 5acontrol transistor M 51asource and drain direct current, another road through low pass filter (by resistance R 5awith electric capacity C 5aforming) after filtering, the DC component of input signal controls transistor M 52asource and drain direct current, so the DC level of left half branch road output is by transistor M 51aand M 52asource and drain direct current sum determine.In like manner, the DC level of right half branch road output is by transistor M 51band M 52bsource and drain direct current sum determine.Therefore, no matter input In 5aand In 5bdC level how, the DC level of two outputs is all equal, thus achieves direct current offset and eliminate function.
In order to overcome the g ain phenomenon that three rank gain stages cause, the utility model have employed alternating expression feedback technique, is added between two traditional reponse systems by a feedback unit.
Opto-electronic conversion is being carried out to light signal and after limited range enlargement, also will converted to digital signal by analog to digital converter (AnalogtoDigitalconverter) and clock data recovery circuit (ClockandDataRecovery) and process again.Therefore, optical receiver needs enough driving forces.In addition, the input and output of high-frequency electronic system all need impedance matching, otherwise can cause signal reflex, cannot carry out maximum power transfer.The utility model adopts F tfrequency multiplier structure is as output buffer stage.
In sum, the utility model adopts the basic structure of adjustment type cascade (RGC) circuit as trans-impedance amplifier of band inductance, expand bandwidth of operation by introducing Butterworth LC ladder network and π type broadband matching network, also reduce equivalent input noise simultaneously.Adopt novel single-ended transfer difference circuit, achieve the differential conversion of full bandwidth, while lifting circuit gain, decrease inductance quantity and chip area.In addition, introduce negative capacitance circuit, reduce high-frequency gain and to roll-off speed, promote bandwidth of operation further.
The utility model embodiment is to the model of each device except doing specified otherwise, and the model of other devices does not limit, as long as can complete the device of above-mentioned functions.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, above-mentioned the utility model embodiment sequence number, just to describing, does not represent the quality of embodiment.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.

Claims (5)

1. have a high-speed cmos monolithic integrated photoreceiver for full bandwidth single-ended transfer difference, it is characterized in that, described high-speed cmos monolithic integrated photoreceiver comprises:
High bandwidth adjustment type cascade trans-impedance amplifier, is converted into voltage signal for the current signal exported by photodetector, tentatively amplifies;
With the single-ended transfer difference device of negative capacitance circuit, single-ended to differential conversion for realizing, improve bandwidth sum amplification voltage signal;
Direct current offset eliminates unit, and the direct current offset of the alternating expression active feedback limiting amplifier that the non-equilibrium signal exported for eliminating described single-ended transfer difference device causes, makes alternating expression active feedback limiting amplifier common mode electrical level consistent;
Described alternating expression active feedback limiting amplifier, is amplified to digital processing element required voltage level for the voltage signal exported by described high bandwidth adjustment type cascade trans-impedance amplifier;
Export buffer stage, for providing driving force.
2. a kind of high-speed cmos monolithic integrated photoreceiver with full bandwidth single-ended transfer difference according to claim 1, it is characterized in that, described high bandwidth adjustment type cascade trans-impedance amplifier is made up of the cascade pole branch road of Butterworth LC staircase match network, common gate amplifying circuit and band inductance.
3. a kind of high-speed cmos monolithic integrated photoreceiver with full bandwidth single-ended transfer difference according to claim 1, it is characterized in that, described direct current offset is eliminated unit and is arranged on described with between the single-ended transfer difference device of negative capacitance circuit, described alternating expression active feedback limiting amplifier.
4. a kind of high-speed cmos monolithic integrated photoreceiver with full bandwidth single-ended transfer difference according to claim 1 or 3, is characterized in that, the described single-ended transfer difference device with negative capacitance circuit comprises: single-ended transfer difference circuit and negative capacitance circuit.
5. a kind of high-speed cmos monolithic integrated photoreceiver with full bandwidth single-ended transfer difference according to claim 4, is characterized in that, described negative capacitance circuit is arranged on described single-ended transfer difference circuit, described direct current offset is eliminated between unit.
CN201520521906.8U 2015-07-17 2015-07-17 High -speed CMOS single scale intergration optical receiver with single -ended slip branch of full bandwidth Expired - Fee Related CN204859189U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104993876A (en) * 2015-07-17 2015-10-21 天津大学 High-speed CMOS monolithically integrated optical receiver with full bandwidth single-ended-to-differential
CN106680690A (en) * 2016-11-17 2017-05-17 上海精密计量测试研究所 Clock driving method for single-ended input differential output of ATE testing
CN114224302A (en) * 2021-12-22 2022-03-25 上海贝瑞电子科技有限公司 Multi-physiological-parameter signal single-channel synchronous acquisition device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104993876A (en) * 2015-07-17 2015-10-21 天津大学 High-speed CMOS monolithically integrated optical receiver with full bandwidth single-ended-to-differential
CN106680690A (en) * 2016-11-17 2017-05-17 上海精密计量测试研究所 Clock driving method for single-ended input differential output of ATE testing
CN106680690B (en) * 2016-11-17 2020-02-07 上海精密计量测试研究所 Clock driving method for single-ended input and differential output applied to ATE (automatic test equipment) test
CN114224302A (en) * 2021-12-22 2022-03-25 上海贝瑞电子科技有限公司 Multi-physiological-parameter signal single-channel synchronous acquisition device
CN114224302B (en) * 2021-12-22 2024-03-15 上海贝瑞电子科技有限公司 Multi-physiological parameter signal single-channel synchronous acquisition device

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