CN204362311U - A kind of novel LTE terminal comprehensive tester - Google Patents

Abstract

The utility model discloses a kind of novel LTE terminal comprehensive tester, it comprises radio frequency sending/receiving module, baseband processing module, clock generating module, master control control module and Subscriber Interface Module SIM, described radio-frequency transmissions receiver module is connected with baseband processing module, baseband processing module is connected with master control control module, master control control module is connected with Subscriber Interface Module SIM, master control control module also with clock generating model calling; Described baseband processing module comprises a DSP, the 2nd DSP, a FPGA and the 2nd FPGA, and the AIF2 interface of a described DSP is connected with radio frequency sending/receiving module, and the AIF2 interface of a DSP is also connected with the GTX interface of a FPGA.A kind of LTE terminal comprehensive tester of the present utility model, have data process effects outstanding, realize double antenna and receive and dispatch synchronous advantage, when especially many for data, adopt the tupe of two CSTR and double FPGA, make the ability of data processing stronger.

Description

A kind of novel LTE terminal comprehensive tester

Technical field

The utility model relates to a kind of novel LTE terminal comprehensive tester.

Background technology

LTE(Long Term Evolution, Long Term Evolution) be by 3GPP(The 3rd Generation Partnership Project, third generation partner program) the UMTS(Universal Mobile Telecommunications System that organizes to set up, universal mobile telecommunications system) Long Term Evolution of technical standard is the basis of mobile communication technology to forth generation evolution.LTE system introduces OFDM(Orthogonal Frequency Division Multiplexing, OFDM) and MIMO(Multi-Input & Multi-Output, multiple-input and multiple-output) etc. critical transmissions technology, (20M bandwidth 2X2MIMO is in 64QAM situation to significantly increase spectrum efficiency and message transmission rate, theoretical descending peak transfer rate is 201Mbps, be probably 140Mbps after removing signaling consumption, but according to actual networking and terminal capability restriction, it is generally acknowledged that downlink peak rates is 100Mbps, upper behavior 50Mbps), and support that various bandwidth is distributed: 1.4MHz, 3MHz, 5MHz, 10MHz, 15MHz and 20MHz etc., and support global main flow 2G/3G frequency range and some newly-increased frequency ranges, thus spectrum allocation may is more flexible, power system capacity and covering also significantly promote.The LTE system network architecture more flattening is simplified, and decreases network node and system complexity, thus reduces Time Delay of Systems, also reduce network design and maintenance cost.LTE system is supported and other 3GPP interoperability of system.LTE system has two kinds of standard: FDD-LTE and TDD-LTE, i.e. Frequency Division Duplexing (FDD) LTE system and time division duplex LTE system, and the main distinction of the two technology is in the physical layer of air interface (picture frame structure, time-division design, synchronous etc.).FDD-LTE system eat dishes without rice or wine downstream transmission adopt a pair symmetry UHF band reception and send data, TDD-LTE system up-downgoing then uses identical frequency range to transmit on different time slots, and relative to FDD duplex mode, TDD has the higher availability of frequency spectrum.Along with LTE network is in the Large scale construction in the whole world, the demand of LTE network optimization and troubleshooting test terminal is increasing, and the demand of LTE terminal comprehensive tester is also more obvious.

Utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, provides a kind of novel LTE terminal comprehensive tester strong to base band data disposal ability.

The purpose of this utility model is achieved through the following technical solutions: a kind of novel LTE terminal comprehensive tester, it comprises radio frequency sending/receiving module, baseband processing module, clock generating module, master control control module and Subscriber Interface Module SIM, described radio-frequency transmissions receiver module is connected with baseband processing module, baseband processing module is connected with master control control module, master control control module is connected with Subscriber Interface Module SIM, master control control module also with clock generating model calling.

Described baseband processing module comprises a DSP, the 2nd DSP, a FPGA and the 2nd FPGA; The AIF2 interface of a described DSP is connected with radio frequency sending/receiving module, the AIF2 interface of the one DSP is also connected with the GTX interface of a FPGA, the PCIe*2 interface of the one DSP is connected with master control control module by PCIe Switch, one DSP is connected with the 2nd DSP respectively by HyperLink interface, SRIO interface, jtag interface, SGMII interface, and a DSP also indicates interface be connected with a FPGA respectively by GPIO interface, specialized configuration interface, state; The 2nd described DSP is connected with RJ-45 interface by SGMII interface, gigabit Ethernet chip successively, 2nd DSP is also connected with a FPGA respectively by GPIO interface, configuration pin, and the 2nd DSP is also connected with the 2nd FPGA respectively by the transmission pin of PI interface, pure parallel interface; The 2nd described FPGA is connected with a FPGA by the control pin realizing SELECTMAP; The control pin of a described FPGA and PCIe Switch connects, and a FPGA is also connected with the configuration signal of gigabit Ethernet chip.

AIF2 interface is HSSI High-Speed Serial Interface.

The model of a described DSP is TMS320C6670, and the model of the 2nd described DSP is TMS320C6670, and the model of a described FPGA is XC6VLX75T, and the model of the 2nd described FPGA is XC3S200AN.

The model of described PCIe Switch is PEX8617, and the model of described gigabit Ethernet chip is 88E1111.

The beneficial effects of the utility model are: a kind of LTE terminal comprehensive tester of the present utility model, have data process effects outstanding, realize double antenna and receive and dispatch synchronous advantage, especially when many for data, adopt the tupe of two CSTR and double FPGA, make the ability of data processing stronger.

Accompanying drawing explanation

Fig. 1 is the utility model structural representation;

Fig. 2 is baseband processing module structural representation.

Embodiment

Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection range of the present utility model is not limited to the following stated.

As shown in Figure 1, a kind of novel LTE terminal comprehensive tester, it comprises radio frequency sending/receiving module, baseband processing module, clock generating module, master control control module and Subscriber Interface Module SIM, described radio-frequency transmissions receiver module is connected with baseband processing module, baseband processing module is connected with master control control module, master control control module is connected with Subscriber Interface Module SIM, master control control module also with clock generating model calling.

Due to the high data rate of LTE, need high performance FPGA and DSP to complete the transfer of data of two-forty, therefore high-speed transfer seems particularly important.Transmitting-receiving and screening, Digital up and down convert, variable-speed data process, IQ amplitude imbalance, power and DC compensation, the radio frequency analog filter compensation etc. of double antenna data is realized in radio-frequency module.Wherein variable-speed data processing module is that Base-Band Processing provides more powerful interface disposal ability, all significantly reduces required hardware resource in design realizes two with FPGA simultaneously.Backoff algorithm then compensate for the otherness of analogue device widely.

Master control control module realizes the distribution of each module clock, Survey control and input and output and controls.Subscriber Interface Module SIM realizes the functions such as user task control, data acceptance, process, analysis, display.

As shown in Figure 2, described baseband processing module comprises a DSP, the 2nd DSP, a FPGA and the 2nd FPGA; The AIF2 interface of a described DSP is connected with radio frequency sending/receiving module, the AIF2 interface of the one DSP is also connected with the GTX interface of a FPGA, the PCIe*2 interface of the one DSP is connected with master control control module by PCIe Switch, one DSP is connected with the 2nd DSP respectively by HyperLink interface, SRIO interface, jtag interface, SGMII interface, and a DSP also indicates interface be connected with a FPGA respectively by GPIO interface, specialized configuration interface, state; The 2nd described DSP is connected with RJ-45 interface by SGMII interface, gigabit Ethernet chip successively, 2nd DSP is also connected with a FPGA respectively by GPIO interface, configuration pin, and the 2nd DSP is also connected with the 2nd FPGA respectively by the transmission pin of PI interface, pure parallel interface; The 2nd described FPGA is connected with a FPGA by the control pin realizing SELECTMAP; The control pin of a described FPGA and PCIe Switch connects, and a FPGA is also connected with the configuration signal of gigabit Ethernet chip.

The model of a described DSP is TMS320C6670, and the model of the 2nd described DSP is TMS320C6670, and the model of a described FPGA is XC6VLX75T, and the model of the 2nd described FPGA is XC3S200AN.

The model of described PCIe Switch is PEX8617, and the model of described gigabit Ethernet chip is 88E1111.

One FPGA is main FPGA, and primary responsibility, to the control of device, mainly completes following functions:

1, by being connected with the GPIO interface and other the pin that arranges of a DSP, control the work of this DSP, and be connected with the AIF2 interface of a DSP by GTX interface, to realize transmitting data;

2, being connected by arranging pin with some of the 2nd DSP, controlling the work of the 2nd DSP;

3, by being connected with the 2nd FPGA, through the conversion of the 2nd FPGA, realize the data link from PC-> the 2nd DSP-> the 2nd FPGA-> the one FPGA, by the 2nd FPGA instantiation SelectMAP interface with dynamic-configuration the one FPGA, and the straight-through connection of parallel interface to a FPGA of the 2nd DSP can be realized in normal work period;

4, be connected with the control pin of PCIe Switch, select mode of operation;

5, be connected with the configuration signal of gigabit Ethernet chip, control its working method.

One DSP is main DSP, is responsible for convergence and the transmitting-receiving of external interface, and collaborative FPGA controls other device simultaneously, mainly completes following functions:

1, receive from the data of the GTX interface of a FPGA and the AIF2 interface data from radio frequency sending/receiving module;

2, collaborative work is carried out by GPIO interface and a FPGA;

3, data interaction is carried out by HyperLink interface, SRIO interface and the 2nd DSP;

4, be connected with external piloting control computer with the 2nd DSP by SGMII interface;

5, be connected with master control control module by PCIe*2 interface.

2nd DSP is from DSP, what mainly bear is the Processing tasks that a collaborative DSP carries out data, when a DSP needs synchronous deal with data amount excessive time, a DSP can be transferred to the 2nd DSP process by HyperLink interface, SRIO interface, mainly completes following functions:

1, carry out exchanges data with a DSP, and connect the SGMII interface of external piloting control;

2, be connected with a FPGA by PI interface, the 2nd FPGA;

3, gigabit Ethernet chip is connected to by SGMII interface, common with outer net signal to convert to, serve as the comparatively look of switch.

2nd FPGA is auxiliary FPGA, the main route be used as between a FPGA and the 2nd DSP, and the object of realization mainly contains two:

1, when dynamic-configuration the one FPGA, a SelectMAP controller is invented by internal logic, the configuration data of coming with the parallel interface controlling the 2nd DSP;

2, after dynamic-configuration the one FPGA completes, the inside of the 2nd FPGA realizes the straight-through of the pin of a FPGA and the parallel interface of the 2nd DSP, is articulated in the parallel interface of the 2nd DSP to realize a FPGA.

Claims (4)

1. a novel LTE terminal comprehensive tester, it is characterized in that: it comprises radio frequency sending/receiving module, baseband processing module, clock generating module, master control control module and Subscriber Interface Module SIM, described radio-frequency transmissions receiver module is connected with baseband processing module, baseband processing module is connected with master control control module, master control control module is connected with Subscriber Interface Module SIM, master control control module also with clock generating model calling;

Described baseband processing module comprises a DSP, the 2nd DSP, a FPGA and the 2nd FPGA; The AIF2 interface of a described DSP is connected with radio frequency sending/receiving module, the AIF2 interface of the one DSP is also connected with the GTX interface of a FPGA, the PCIe*2 interface of the one DSP is connected with master control control module by PCIe Switch, one DSP is connected with the 2nd DSP respectively by HyperLink interface, SRIO interface, jtag interface, SGMII interface, and a DSP also indicates interface be connected with a FPGA respectively by GPIO interface, specialized configuration interface, state; The 2nd described DSP is connected with RJ-45 interface by SGMII interface, gigabit Ethernet chip successively, 2nd DSP is also connected with a FPGA respectively by GPIO interface, configuration pin, and the 2nd DSP is also connected with the 2nd FPGA respectively by the transmission pin of PI interface, pure parallel interface; The 2nd described FPGA is connected with a FPGA by the control pin realizing SELECTMAP; The control pin of a described FPGA and PCIe Switch connects, and a FPGA is also connected with the configuration signal of gigabit Ethernet chip.

2. the novel LTE terminal comprehensive tester of one according to claim 1, it is characterized in that: the model of a described DSP is TMS320C6670, the model of the 2nd described DSP is TMS320C6670, the model of a described FPGA is XC6VLX75T, and the model of the 2nd described FPGA is XC3S200AN.

3. the novel LTE terminal comprehensive tester of one according to claim 1, is characterized in that: the model of described PCIe Switch is PEX8617, and the model of described gigabit Ethernet chip is 88E1111.

4. the novel LTE terminal comprehensive tester of one according to claim 1, is characterized in that: it also comprises multiple DDR3 RAM, and described DDR3 RAM is connected with a DSP by the DDR3 interface of a DSP.