CN204066103U - A kind of usb signal for computing machine amplifies transmission circuit - Google Patents
A kind of usb signal for computing machine amplifies transmission circuit Download PDFInfo
- Publication number
- CN204066103U CN204066103U CN201420541301.0U CN201420541301U CN204066103U CN 204066103 U CN204066103 U CN 204066103U CN 201420541301 U CN201420541301 U CN 201420541301U CN 204066103 U CN204066103 U CN 204066103U
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- resistor
- triode
- field effect
- effect transistor
- capacitor
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 11
- 230000005669 field effect Effects 0.000 claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 108060009362 VPS41 Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
Abstract
The utility model discloses a kind of usb signal for computing machine and amplify transmission circuit, comprise the first resistor to the tenth resistor, the first triode to the 4th triode, potentiometer, the first capacitor, the second capacitor, the first field effect transistor and the second field effect transistor, applied signal voltage converts electric current to through the first triode and the second triode, convert voltage to by the 3rd triode and the 4th triode again, then amplify output signal further through the first field effect transistor and the second field effect transistor.Compared with prior art, the utility model can amplify the data transmission of USB structure, effectively can improve the data rate of USB structure, facilitate the data rate of USB, practical and convenient, has the value applied.
Description
Technical field
The utility model relates to a kind of computing machine USB circuit, particularly relates to a kind of usb signal for computing machine and amplifies transmission circuit.
Background technology
USB is a kind of USB (universal serial bus), and its Chinese is referred to as " logical get lines crossed ", is an external bus standard, for connection and the communication of specification computer and external unit.It is the interfacing being applied in PC field.The plug and play of USB interface support equipment and warm connection function.And in prior art, USB interface transmission speed is in the data transmission excessively slow, though in prior art for USB interface in continuous improvement, but be not enough to improve data rate, reason is, the insufficient strength of usb data signal, therefore, need to be improved further.
Utility model content
The purpose of this utility model is just to provide a kind of usb signal for computing machine to amplify transmission circuit to solve the problem.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model comprises the first resistor to the tenth resistor, first triode is to the 4th triode, potentiometer, first capacitor, second capacitor, first field effect transistor and the second field effect transistor, the first end of described potentiometer is as the signal input part of described signal amplifier, second end of described potentiometer is connected rear also ground connection with the first end of described 7th resistor, the sliding end of described potentiometer respectively with the first end of described second resistor and the first end of described 3rd resistor, second end of described second resistor is connected with the base stage of described first triode, the emitter of described first triode is connected with the first end of described 4th resistor and the base stage of described 3rd triode respectively, second end of described 4th resistor respectively with the collector of described second triode, the first end of described 5th resistor, the source electrode of described first field effect transistor is connected with the first end of described first capacitor and as the positive source input end of described signal amplifier, second end ground connection of described first capacitor, second end of described 5th resistor is connected with the first end of described 6th resistor and the collector of described 3rd triode respectively, second end of described 6th resistor is connected with the grid of described first field effect transistor respectively, the emitter of described 3rd triode respectively with the emitter of described 4th triode, second end of described 7th resistor is connected with the first end of described first resistor, second end of described 3rd resistor is connected with the base stage of described second triode, the emitter of described second triode is connected with the base stage of described 4th triode and the first end of described 8th resistor respectively, second end of described 8th resistor respectively with the collector of described first triode, the first end of described 9th resistor, the source electrode of described second field effect transistor is connected with the first end of described second capacitor and as the power cathode input end of described signal amplifier, second end ground connection of described second capacitor, the collector of described 4th triode is connected with the second end of described 9th resistor and the first end of described tenth resistor respectively, second end of described tenth resistor is connected with the grid of described second field effect transistor, the drain electrode of described second field effect transistor is connected with the drain electrode of described first field effect transistor and the second end of described first resistor and respectively as the signal output part of described signal amplifier.
The beneficial effects of the utility model are:
The utility model is that a kind of usb signal for computing machine amplifies transmission circuit, compared with prior art, the utility model can amplify the data transmission of USB structure, effectively can improve the data rate of USB structure, facilitate the data rate of USB, practical and convenient, there is the value applied.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail:
As shown in Figure 1: the utility model comprises the first resistor R1 to the tenth resistor R10, first triode VT1 is to the 4th triode VT4, potentiometer RP, first capacitor C1, second capacitor C2, first field effect transistor FET1, second field effect transistor FET2, the first end of potentiometer RP is as the signal input part of signal amplifier, second end of potentiometer RP is connected rear also ground connection with the first end of the 7th resistor R7, the sliding end of potentiometer RP respectively with the first end of the second resistor R2 and the first end of the 3rd resistor R3, second end of the second resistor R2 is connected with the base stage of the first triode VT1, the emitter of the first triode VT1 is connected with the first end of the 4th resistor R4 and the base stage of the 3rd triode VT3 respectively, second end of the 4th resistor R4 respectively with the collector of the second triode VT2, the first end of the 5th resistor R5, the source electrode of the first field effect transistor FET1 is connected with the first end of the first capacitor C1 and as the positive source input end of signal amplifier, the second end ground connection of the first capacitor C1, second end of the 5th resistor R5 is connected with the first end of the 6th resistor R6 and the collector of the 3rd triode VT3 respectively, second end of the 6th resistor R6 is connected with the grid of the first field effect transistor FET1 respectively, the emitter of the 3rd triode VT3 respectively with the emitter of the 4th triode VT4, second end of the 7th resistor R7 is connected with the first end of the first resistor R1, second end of the 3rd resistor R3 is connected with the base stage of the second triode VT2, the emitter of the second triode VT2 is connected with the base stage of the 4th triode VT4 and the first end of the 8th resistor R8 respectively, second end of the 8th resistor R8 respectively with the collector of the first triode VT1, the first end of the 9th resistor R9, the source electrode of the second field effect transistor FET2 is connected with the first end of the second capacitor C2 and as the power cathode input end of signal amplifier, the second end ground connection of the second capacitor C2, the collector of the 4th triode VT4 is connected with second end of the 9th resistor R9 and the first end of the tenth resistor R10 respectively, second end of the tenth resistor R10 is connected with the grid of the second field effect transistor FET2, the drain electrode of the second field effect transistor FET2 is connected with the drain electrode of the first field effect transistor FET1 and second end of the first resistor R1 and respectively as the signal output part of signal amplifier.
Principle of work of the present utility model is as follows:
As shown in Figure 1: applied signal voltage converts electric current to through the first triode VT1 and the second triode VT2, convert voltage to by the 3rd triode VT3 and the 4th triode VT4 again, then amplify output signal further through the first field effect transistor FET1 and the second field effect transistor FET2.After first resistance R1 converts output voltage to electric current, the emitter being added to the second field effect transistor FET2 forms Current Negative Three-Point Capacitance.Thus the electric current the 7th resistance R7 flow through is the electric current of the second field effect transistor FET2 and the difference of feedback current.
Component parameter of the present utility model is selected as follows:
First resistance R1 is 100 Ω, second resistance R2 is 400 Ω, 3rd resistance R3 is 500 Ω, 4th resistance R4 is 2k Ω, 5th resistance R5 is 27k Ω, 6th resistance R6 is 200 Ω to the 8th resistance R8, 9th resistance R9 is 479 Ω, tenth resistance R10 is 5.5k Ω, first triode VT1 is PNP type triode to the 4th triode VT4, potentiometer RP is 400k Ω, first electric capacity C1 is 300uf, second electric capacity C2 is 470uf, first field effect transistor FET1 is that the field effect of model K1056 is closed, second field effect transistor FET2 is the field effect transistor of model J160.
More than show and describe ultimate principle of the present utility model and principal character and advantage of the present utility model.The technician of the industry should understand; the utility model is not restricted to the described embodiments; what describe in above-described embodiment and instructions just illustrates principle of the present utility model; under the prerequisite not departing from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (1)
1. the usb signal for computing machine amplifies transmission circuit, it is characterized in that: comprise the first resistor to the tenth resistor, first triode is to the 4th triode, potentiometer, first capacitor, second capacitor, first field effect transistor and the second field effect transistor, the first end of described potentiometer is as the signal input part of described signal amplifier, second end of described potentiometer is connected rear also ground connection with the first end of described 7th resistor, the sliding end of described potentiometer respectively with the first end of described second resistor and the first end of described 3rd resistor, second end of described second resistor is connected with the base stage of described first triode, the emitter of described first triode is connected with the first end of described 4th resistor and the base stage of described 3rd triode respectively, second end of described 4th resistor respectively with the collector of described second triode, the first end of described 5th resistor, the source electrode of described first field effect transistor is connected with the first end of described first capacitor and as the positive source input end of described signal amplifier, second end ground connection of described first capacitor, second end of described 5th resistor is connected with the first end of described 6th resistor and the collector of described 3rd triode respectively, second end of described 6th resistor is connected with the grid of described first field effect transistor respectively, the emitter of described 3rd triode respectively with the emitter of described 4th triode, second end of described 7th resistor is connected with the first end of described first resistor, second end of described 3rd resistor is connected with the base stage of described second triode, the emitter of described second triode is connected with the base stage of described 4th triode and the first end of described 8th resistor respectively, second end of described 8th resistor respectively with the collector of described first triode, the first end of described 9th resistor, the source electrode of described second field effect transistor is connected with the first end of described second capacitor and as the power cathode input end of described signal amplifier, second end ground connection of described second capacitor, the collector of described 4th triode is connected with the second end of described 9th resistor and the first end of described tenth resistor respectively, second end of described tenth resistor is connected with the grid of described second field effect transistor, the drain electrode of described second field effect transistor is connected with the drain electrode of described first field effect transistor and the second end of described first resistor and respectively as the signal output part of described signal amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420541301.0U CN204066103U (en) | 2014-09-15 | 2014-09-15 | A kind of usb signal for computing machine amplifies transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420541301.0U CN204066103U (en) | 2014-09-15 | 2014-09-15 | A kind of usb signal for computing machine amplifies transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204066103U true CN204066103U (en) | 2014-12-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420541301.0U Expired - Fee Related CN204066103U (en) | 2014-09-15 | 2014-09-15 | A kind of usb signal for computing machine amplifies transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204066103U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808490A (en) * | 2016-03-02 | 2016-07-27 | 陕西理工学院 | Computer USB data transmission accelerating processor |
-
2014
- 2014-09-15 CN CN201420541301.0U patent/CN204066103U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808490A (en) * | 2016-03-02 | 2016-07-27 | 陕西理工学院 | Computer USB data transmission accelerating processor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141231 Termination date: 20180915 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |