CN203277349U - Field effect transistor - Google Patents
Field effect transistor Download PDFInfo
- Publication number
- CN203277349U CN203277349U CN 201320277682 CN201320277682U CN203277349U CN 203277349 U CN203277349 U CN 203277349U CN 201320277682 CN201320277682 CN 201320277682 CN 201320277682 U CN201320277682 U CN 201320277682U CN 203277349 U CN203277349 U CN 203277349U
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- pin
- insulating base
- effect transistor
- field effect
- chip
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Abstract
The utility model relates to the field of electronic components and discloses a field effect transistor which comprises an insulated base, a first pin, a second pin and a third pin which are installed on the insulated base, and a chip in the insulated base. The first pin is connected with a D electrode of the chip, the second pin is connected with an S electrode of the chip, and the third pin is connected with a G electrode of the chip. Both the upper surface and the lower surface of the insulated base are provided with bosses for bearing. The bosses are trapezoid platforms. The field effect transistor of the utility model has bearing capacity, and when the field effect transistor is connected with other electronic components to use, the possibility of disconnection is little.
Description
Technical field
The utility model relates to the electronic devices and components fields, relates in particular to a kind of field effect transistor.
Background technology
Field effect transistor is the abbreviation of field-effect transistor (Field Effect Transistor is abbreviated as FET), participates in conduction by majority carrier, also referred to as unipolar transistor.It belongs to the voltage-controlled type semiconductor device, has that input resistance high (10^8～10^9 Ω), noise are little, low in energy consumption, dynamic range large, it is integrated to be easy to, there is no the advantages such as secondary-breakdown phenomenon, safety operation area field width.What use was the most general at present is the square field effect transistor of sheet, its first pin, the second pin and the 3rd pin all are positioned on sheet square unified side, in use, be connected with the pole plate of electroacoustic original paper when using, can not play the carrying effect to pole plate, occur breaking thereby cause connecting.
Summary of the invention
The purpose of the utility model embodiment is: a kind of field effect transistor is provided, has bearing capacity, make to be connected with other electronic components when using, be not easy to disconnect.
A kind of field effect transistor that the utility model embodiment provides, comprise the first pin, the second pin and the 3rd pin on insulating base, installation and described insulating base, be positioned at the chip of described insulating base, described the first pin is connected with the D utmost point of described chip, described the second pin is connected with the S utmost point of described chip, described the 3rd pin is connected with the G utmost point of described chip, and the upper surface of described insulating base and lower surface are equipped with the boss for carrying.
For improvement of the technical scheme, described boss is bucking ladder.
For further improvement in the technical proposal, described the 3rd pin is installed on a surface of described insulating base, and described the first pin and the second pin all are installed on another relative surface of described insulating base.
For further improvement in the technical proposal, described the 3rd pin is installed on the upper surface of described insulating base, and described the first pin and the second pin all are installed on the lower surface of described insulating base.
For further improvement in the technical proposal, described the 3rd pin is installed on the lower surface of described insulating base, and described the first pin and the second pin all are installed on the upper surface of described insulating base.
Therefore the technical scheme of application the utility model embodiment has following beneficial effect:
(1) have bearing capacity, thereby make more firm with being connected of other electronic components, convenient;
(2) simple in structure;
(3) cost of manufacture is low.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present utility model, consists of the application's a part, does not consist of to improper restriction of the present utility model, in the accompanying drawings:
The structural representation of a kind of field effect transistor that Fig. 1 provides for the utility model embodiment 1;
Fig. 2 is the structural representation of a kind of field effect transistor of providing of the utility model embodiment 2.
Embodiment
Describe the utility model in detail below in conjunction with accompanying drawing and specific embodiment, be used for explaining the utility model in this illustrative examples of the present utility model and explanation, but not as to restriction of the present utility model.
Embodiment 1:
As shown in Figure 1, field effect transistor described in the utility model, comprise insulating base 1, be installed on the first pin 2, the second pin 3 and the 3rd pin 4 on described insulating base 1, be positioned at the chip 5 of described insulating base 1, described the first pin 2 is connected with the D utmost point of described chip 5, described the first pin 3 is connected with the S utmost point of described chip 5, and described the 3rd pin 4 is connected (S, D, the G of chip not drawn in figure) with the G utmost point of described chip 5.Simultaneously, described the 3rd pin 4 is installed on a surface of described insulating base 1, and described the first pin 2 and the second pin 3 all are installed on another relative surface of described insulating base 1.In order to solve described field effect transistor in use, the first pin 2, the second pin 3 and the 3rd pin 4 are convenient to be connected with other electronic components, thereby upper surface and lower surface at described insulating base 1 are equipped with for the boss 6 that carries, described boss 6 is bucking ladder, and described the 3rd pin 4 is installed on the upper surface of described insulating base 1, and described the first pin 2 and the second pin 3 all are installed on the lower surface of described insulating base 1.
Embodiment 2:
As shown in Figure 2, the present embodiment and embodiment 1 difference only are: described the 3rd pin 4 is installed on the lower surface of described insulating base 1, and described the first pin 2 and the second pin 3 all are installed on the upper surface of described insulating base 1.
The above technical scheme that the utility model embodiment is provided is described in detail, used specific case herein principle and the execution mode of the utility model embodiment are set forth, the explanation of above embodiment is only applicable to help to understand the principle of the utility model embodiment; Simultaneously, for one of ordinary skill in the art, according to the utility model embodiment, all will change on embodiment and range of application, in sum, this description should not be construed as restriction of the present utility model.
Claims (5)
1. field effect transistor, comprise the first pin (2), the second pin (3) and the 3rd pin (4) on insulating base (1), installation and described insulating base (1), be positioned at the chip (5) of described insulating base (1), described the first pin (2) is connected with the D utmost point of described chip (5), described the second pin (3) is connected with the S utmost point of described chip (5), described the 3rd pin (4) is connected with the G utmost point of described chip (5), it is characterized in that:
The upper surface of described insulating base (1) and lower surface are equipped with the boss (6) for carrying.
2. field effect transistor according to claim 1 is characterized in that:
Described boss (6) is bucking ladder.
3. field effect transistor according to claim 1 is characterized in that:
Described the 3rd pin (4) is installed on a surface of described insulating base (1), and described the first pin (2) and the second pin (3) all are installed on another relative surface of described insulating base (1).
4. field effect transistor according to claim 3 is characterized in that:
Described the 3rd pin (4) is installed on the upper surface of described insulating base (1), and described the first pin (2) and the second pin (3) all are installed on the lower surface of described insulating base (1).
5. field effect transistor according to claim 3 is characterized in that:
Described the 3rd pin (4) is installed on the lower surface of described insulating base (1), and described the first pin (2) and the second pin (3) all are installed on the upper surface of described insulating base (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320277682 CN203277349U (en) | 2013-05-16 | 2013-05-16 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320277682 CN203277349U (en) | 2013-05-16 | 2013-05-16 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203277349U true CN203277349U (en) | 2013-11-06 |
Family
ID=49507703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320277682 Expired - Fee Related CN203277349U (en) | 2013-05-16 | 2013-05-16 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203277349U (en) |
-
2013
- 2013-05-16 CN CN 201320277682 patent/CN203277349U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20140516 |