CN203104477U

CN203104477U - Device for receiving IEC61850-9-2 sampling values of multiple paths in real time by using programmable logic device

Info

Publication number: CN203104477U
Application number: CN 201320106848
Authority: CN
Inventors: 张杭; 张伟; 孙进伟; 王玉林
Original assignee: NANJING INTELLIGENT APPARATUS CO Ltd
Current assignee: NANJING INTELLIGENT APPARATUS CO Ltd
Priority date: 2013-03-11
Filing date: 2013-03-11
Publication date: 2013-07-31
Anticipated expiration: 2023-03-11

Abstract

The utility model discloses a device for receiving IEC61850-9-2 sampling values of multiple paths in real time by using a programmable logic device. The device for receiving the sampling values comprises more than two paths of 100M-FX optical fiber receivers, more than two paths of 100M Ethernets PHY, the programmable logic device, and an MCU/DSP (Micro Control Unit/Digital Signal Processor), wherein each path of 100M Ethernet PHY is connected to the programmable logic device through a single MII (Media Independent Interface) module; and the programmable logic device is connected with the MCU/DSP through an MII module and a parallel bus interface module. Each path of MII module corresponds to an MAC (Media Access Control) module; the MAC module is capable of judging whether a current data packet is an IEC61850-9-2 data packet or not; and if not, the current data packet is abandoned immediately, so that the influences of a net storm on system functions are eliminated on hardware.

Description

A kind of device that uses programmable logic device to receive multichannel IEC61850-9-2 sampled value in real time

Technical field

The present invention relates to a kind of device that uses programmable logic device to receive multichannel IEC61850-9-2 sampled value data in real time, be applicable to that occasions such as electric power digital transformer station, intelligent transformer station need to receive in real time the smart machine of multichannel IEC61850-9-2 sampled value data.

Background technology

Because the fiber optic Ethernet transmission has high reliability, transmission speed is fast, connecting up makes things convenient for the low advantage of cost, in intelligent transformer station, fiber optic Ethernet replaces most of cable to be become inevitable.IEC international organization is for using fiber optic Ethernet transmission transformer station analog quantity sampled value to propose the IEC61850-9-2 standard, and its physical layer just is to use 100M fiber optic Ethernet interface.

Because intelligent substation secondary devices such as digital protection or oscillograph generally all will be gathered the multi-analog signal, if the collection of these analog quantitys transmission will corresponding multichannel 100M fiber optic Ethernet interface input with the IEC61850-9-2 standard.Traditional way is to use Ethernet switching chip that the multichannel Ethernet data is merged to the Ethernet interface of sending into processor in one tunnel then in device, or directly uses the processor of band multichannel Ethernet interface.These two kinds of schemes all have drawback, first kind of scheme is owing to used Ethernet switching chip, the uncertainty that will cause every road Ethernet data receive delay, and the ability of resisting network storm also has problem, second kind of scheme accomplished the isolation of every road Ethernet data, but the processor that has the multichannel Ethernet interface generally all compares costliness and periphery circuit design complexity, and this scheme also exists and resists the indifferent shortcoming of network storm.

Summary of the invention

The objective of the invention is: a kind of device that uses programmable logic device to receive multichannel IEC61850-9-2 sampled value data in real time is provided, and accomplishes to resist the network storm abnormal conditions that may exist in the system fully.

Technical solution provided by the invention is: a kind of device that uses programmable logic device to receive multichannel IEC61850-9-2 sampled value in real time, it is characterized in that: it comprises the 100M-FX fiber optic receiver, 100M Ethernet PHY, programmable logic device, MCU/DSP, described 100M-FX fiber optic receiver and 100M Ethernet PHY are more than the two-way, described every road 100M Ethernet PHY all is connected to described programmable logic device by independent MII interface module, and described programmable logic device links to each other with described MCU/DSP with the parallel bus interface module by the MII interface module.

Described programmable logic device inside has 64 markers counters and a plurality of MAC module, and described MAC module is corresponding one by one with the MII interface module.

Device also comprises IRIG-B sign indicating number optic fiber transceiver module, described IRIG-B sign indicating number optic fiber transceiver module the B sign indicating number to the time signal send to described codified logical device, give 64 markers counters synchronously with temporal information after the decoding, be used for packet and stamp the absolute time value that receives.

Description of drawings

Fig. 1 adopts the mode of Ethernet switching chip that multichannel IEC61850-9-2 sampled value data are pooled on the way, sends the scheme schematic diagram of the ethernet controller of a processor then.

Fig. 2 adopts the network processing unit that has a plurality of ethernet controllers directly to receive the scheme schematic diagram of multichannel IEC61850-9-2 sampled value data.

Fig. 3 is the scheme schematic diagram that use programmable logic device of the invention process receives multichannel IEC61850-9-2 sampled value data in real time.

Fig. 4 is that use programmable logic device of the invention process receives in the scheme of multichannel IEC61850-9-2 sampled value data in real time, the functional block diagram of the inner specific implementation of programmable logic device.

Embodiment

The present invention is described in more detail below in conjunction with accompanying drawing and specific implementation method.

As shown in Figure 1 and Figure 2, be that the mode of available technology adopting Ethernet switching chip is pooled to multichannel IEC61850-9-2 sampled value data on the way, send the scheme schematic diagram (Fig. 1) of the ethernet controller of a processor then; The network processing unit that has a plurality of ethernet controllers with employing directly receives the scheme schematic diagram (Fig. 2) of multichannel IEC61850-9-2 sampled value data.

Use programmable logic device of the invention process receives the device of multichannel IEC61850-9-2 sampled value data in real time, use scale programmable logic device such as FPGA etc., as shown in Figure 3, for Ethernet input in every road realizes that separately the MII interface module is to receive the IEC61850-9-2 Ethernet sampled value packet of optical fiber input, then the packet that receives is unpacked and calculates the CRC check value by the MAC module, if check value correctly then with decoded packet during together with 64 of packet times of reception scale value together put into FIFO, wait for the processing of IEC61850-9-2 packet real-time processing module.Scale value is in order to realize receiving the real-time of sampled value packet in the time of these 64, specially realized the count value of one 64 bit time counter in FPGA inside, the counting precision of this counter is 20ns, is enough to satisfy the needs of IEC61850-9-2 packet real-time characteristic.Simultaneously, in order to accomplish to save CPU Ethernet interface bandwidth and effectively to resist network storm situation under the abnormal conditions, the MAC module can judge also whether the packet of current reception is the IEC61850-9-2 packet, if not then abandoning immediately, stopped the influence of network storm on the hardware for systemic-function.

The CPU that sends to that can both be more real-time for the data that make every road IEC61850-9-2 Ethernet interface handles, the IEC61850-9-2 packet real-time processing module every road of poll Ethernet in order receives FIFO, can guarantee that like this packet of every circuit-switched data interface can both obtain consistent relatively receive delay.Simultaneously since on the hardware for all having done target operation when beating the time of reception of each packet, CPU just can obtain the absolute moment that this packet receives simultaneously when receiving packet so, thereby eliminated the delay and jitter that multichannel data shared network passage is brought, improved the precision characteristic of system.

Obtained receiving the packet and time scale information of FIFO when IEC61850-9-2 packet real-time processing module after, just with the end of time scale information continued access to packet, together give mac controller then by sending FIFO, owing to the time scale information that packet has been increased by 64 has changed the CRC check value of packet, also to be responsible for carrying out the CRC check data bit that the final data bag was calculated and put into to CRC check again for sending packet so send mac controller.After calculating CRC finished, mac controller was responsible for the final data bag is sent to by the MII interface Ethernet interface of CPU.

Packet in the whole design receives FIFO and packet, and to send FIFO all be in order to solve the inconsistent and stationary problem that brings of former and later two data packet lengths.IEC61850-9-2 packet real-time processing module also must monitor the total bandwidth that total interface receives data speed, when the data speed addition of all data-interfaces greater than the 80%(of CPU Ethernet interface data speed 80Mbps just) time, will be by status register to CPU outputting alarm information, remind CPU network reception this moment load overweight, might lost data packets.

In order to obtain the absolute time of packet actual reception, also will for system insert IRIG-B to the time signal, this time signal can obtain by the IRIG-B interface from the gps satellite receiving system.The temporal information of utilizing the IRIG-B decoder module to decode will to obtain is given 64 markers counters synchronously, then each can be received packet and stamp the absolute time value that receives.If IRIG-B to the time dropout or not do not insert, then the time scale information of all packets can only reflect the relative moment of reception and not have the information of absolute time.

Though the present invention with preferred embodiment openly as above; but they are not to be used for limiting the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the invention; from when can doing various variations or retouching, so being as the criterion of should being defined with the application's claim protection range of protection scope of the present invention.

Claims

1. device that uses programmable logic device to receive multichannel IEC61850-9-2 sampled value in real time, it is characterized in that: it comprises 100M-FX fiber optic receiver, 100M Ethernet PHY, programmable logic device, MCU/DSP, described 100M-FX fiber optic receiver and 100M Ethernet PHY are more than the two-way, described every road 100M Ethernet PHY all is connected to described programmable logic device by independent MII interface module, and described programmable logic device links to each other with described MCU/DSP with the parallel bus interface module by the MII interface module.

2. device according to claim 1 is characterized in that: described programmable logic device inside has 64 markers counters and a plurality of MAC module, and described MAC module is corresponding one by one with the MII interface module.

3. device according to claim 2, it is characterized in that: it also comprises IRIG-B sign indicating number optic fiber transceiver module, described IRIG-B sign indicating number optic fiber transceiver module the B sign indicating number to the time signal send to described codified logical device, give 64 markers counters synchronously with temporal information after the decoding, be used for packet and stamp the absolute time value that receives.