CN202796957U - Array substrate and OLED display device - Google Patents

Array substrate and OLED display device Download PDF

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Publication number
CN202796957U
CN202796957U CN 201220505507 CN201220505507U CN202796957U CN 202796957 U CN202796957 U CN 202796957U CN 201220505507 CN201220505507 CN 201220505507 CN 201220505507 U CN201220505507 U CN 201220505507U CN 202796957 U CN202796957 U CN 202796957U
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tft
gate
drain
array substrate
source
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CN 201220505507
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Chinese (zh)
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牛菁
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京东方科技集团股份有限公司
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Abstract

The embodiment of the utility model provides an array substrate and an OLED display device which relate to the display device manufacture field, and enable the effective luminescence area of the display device to be improved, the manufacture process to be simplified, and the product production difficulty and production cost to be reduced. The array substrate comprises a plurality of sub-pixel units formed by using transverse and longitudinal crossed grid lines and data lines to divide the substrate, and each sub-pixel unit comprises a first TFT, a second TFT and a pixel electrode. The grids of the first TFTs are connected with the grid lines, and the sources of the first TFTs are connected with the data lines; the drains of the second TFTs are connected with the pixel electrodes, the sources and drains of the first TFTs and the grids of the second TFTs are located in a same layer, and the drains of the first TFTs are connected with the grids of the second TFTs directly. The embodiment of the utility model is used to manufacture the display device.

Description

—种阵列基板及OLED显示装置 - Species array substrate and the OLED display device

技术领域 FIELD

[0001] 本实用新型涉及显示装置制造领域,尤其涉及一种阵列基板及OLED显示装置。 [0001] The present invention relates to the field of manufacturing a display device, particularly, to an array substrate and an OLED display device. 背景技术 Background technique

[0002] 在现有的各种显示装置中,由于0LED(0rganic Light-Emitting Diode,有机发光二极管)显示器与CRT (Cathode Ray Tube,阴极射线管)显示器或TFT-LCD (Thin FilmTransistor-Liquid Crystal Display,薄膜晶体管液晶显示器)相比具有更轻和更薄的外观设计、更宽的可视视角、更快的响应速度以及更低的功耗等特点,因此OLED显示器已逐渐作为下一代显示设备而备受人们的关注。 [0002] In the conventional display various devices, since 0LED (0rganic Light-Emitting Diode, OLED) display and a CRT (Cathode Ray Tube, a cathode ray tube) display or a TFT-LCD (Thin FilmTransistor-Liquid Crystal Display , a thin film transistor liquid crystal display) compared to lighter and thinner design, visual wider viewing angle, faster response speed, and lower power consumption, etc., so the OLED display has gradually as a next generation display devices much attention.

[0003] OLED显示装置是自发光器件,其通常包括像素电极、与像素电极相对设置的对电极以及设置于像素电极与对电极之间的有机发光层。 [0003] OLED devices are self-luminous display apparatus, which generally comprises a pixel electrode, the pixel electrode and the organic light emitting layer disposed between the electrode and the pixel electrode and a counter electrode disposed opposite disposed pairs. OLED显示装置通过将电压施加到包括像素电极和对电极上以使设置于像素电极和对电极之间的有机发光层两端形成电场,从而使得电子和空穴能够在有机发光层中彼此复合而发光。 OLED display device by applying a voltage to the pixel electrode and including an upper electrode disposed on the pixel electrode so that an electric field formed on both ends of the organic light emitting layer between the electrodes, so that electrons and holes can recombine with each other in the organic light-emitting layer and light. 其中,可以通过具有电路单元的阵列基板控制施加在像素电极上的电压,从而控制OLED显示装置的显示效果。 Wherein, may control the voltage applied to the pixel electrodes by an array substrate having a circuit unit to control the display OLED display device.

[0004] 现有技术中,为了更好地控制OLED显示装置的显示效果,阵列基板的电路单元通常采用两个TFT (Thin Film Transistor,薄膜晶体管)的结构,其中,第一TFT是开关晶体管,第二TFT是驱动晶体管,局部像素单元的结构可以如图I所示,图2为图I的AA向截面图。 [0004] In the prior art, in order to better control the display unit of the OLED display device circuit, the array substrate structure usually two TFT (Thin Film Transistor, TFT), wherein the first TFT is a switching transistor, the second TFT is a driving transistor, the pixel unit may be a partial structure I shown in FIG, 2 is the AA cross-sectional view of FIG. I. 图I中,栅线13与TFTll的栅极即第一栅极111连接,数据线14与TFTll的源极即第一源极112相连,TFTll的第一漏极113透过过孔a连接到TFT12的栅极即第二栅极121。 FIG. I, the first gate line 13 that is connected to the gate TFTll gate electrode 111, the data line 14 and a source electrode that is connected to a first TFTll the source electrode 112, the first drain electrode 113 through vias TFTll connected to a a second gate, i.e. the gate of TFT12 121. 平行于数据线14的Vdd线15连接到TFT12的源极即第二源极122,TFT12的第二漏极123与像素电极16连接。 Parallel to the data line 15 is connected to the Vdd line 14 to TFT12 source 122 i.e., a second source electrode, second drain electrode 123 and the pixel electrode 16 is connected to TFT12. 由截面图2可知,两个TFT形成于基板10上,且均采用底栅结构,第一栅极111和第二栅极121上依次还形成有栅绝缘层101、由氧化物形成的有源层102以及刻蚀阻挡层103。 2 shows that the cross-sectional view, two TFT formed on the substrate 10, and a bottom gate structure are used, on the first gate 111 and second gate 121 are sequentially formed with a further gate insulating layer 101, the active form of oxide layer 102 and the etch stop layer 103. 第一漏极113通过过孔a与连接电极17相连,第二栅极121通过过孔b与连接电极17相连,这样,与像素电极16同层的连接电极17即可以连接第一漏极113与第二栅极121。 The first drain electrode 113 through the via hole is connected to a connection electrode 17, the second gate electrode 121 through the via hole 17 b is connected to the connection electrode such that the electrode 16 is connected with the pixel electrode layer 17 which can connect the first drain electrode 113 and a second gate electrode 121. 为避免连接电极17与其他电极之间出现短路,像素电极16覆盖区域应当避开连接电极17所在区域,如图I所示,相应的像素电极16上设置的有机发光层18也应当避开连接电极17所在区域,连接电极17所在区域需由遮光材料19覆盖,有机发光层18与遮光材料19的表面设置有对电极110从而构成OLED显示装置。 To avoid a short circuit occurs between the connection electrode 17 and other electrodes, the pixel electrode 16 covers the area of ​​the connecting electrode should be avoided Area 17, shown in FIG. I, the organic light emitting layer disposed on the corresponding pixel electrode 1618 is also connected to be avoided area electrodes 17, 17 connected to an electrode for an area 19 is covered by a light shielding material, the organic light emitting layer 18 and the surface light-shielding material 19 is provided with a pair of electrodes 110 is configured such that the OLED display device.

[0005] 由于连接电极17的存在,该连接电极17所在区域需要由黑矩阵覆盖,从而使得OLED显示装置的有效发光区域面积减少、显示亮度降低。 [0005] Because of the presence of the connecting electrode 17, the connector 17 Area electrode to be covered by the black matrix, such that the OLED display device to reduce the area of ​​the effective light emitting area, the display brightness is reduced. 另一方面,这样一种结构的OLED显示装置的阵列基板从栅极的设置到像素电极的设置需要经历7次掩模工序,以分别形成栅极层、栅绝缘层、有源层、刻蚀阻挡层、源漏电极层、树脂层以及像素电极和连接电极,同时为了连接第一漏极113和第二栅极121,需要在基板上设置多个过孔,这将导致OLED显示装置的制作工艺更加复杂,从而大大提高了产品的生产难度和生产成本。 On the other hand, such a configuration of the OLED display from the array substrate to a gate electrode of the pixel disposed to go through seven mask process to form a gate layer, respectively, a gate insulating layer, an active layer, etching barrier layer, source and drain electrode layer, a resin layer and a pixel electrode and the connection electrode, and in order to connect the first drain electrode 113 and the second gate electrode 121 is necessary to provide a plurality of through holes in the substrate, which would result in production of the OLED display device process is more complicated, thus greatly improving the production difficulty and production costs.

实用新型内容[0006] 本实用新型的实施例提供一种阵列基板及OLED显示装置,可以提高显示装置的有效发光面积,简化制作工艺,降低产品的生产难度和生产成本。 SUMMARY [0006] Example embodiments of the present invention provides an array substrate and OLED display device can be increased effective luminescence area of ​​the display device, to simplify the manufacturing process, reducing production difficulty and production cost.

[0007] 为达到上述目的,本实用新型的实施例采用如下技术方案: [0007] To achieve the above object, an embodiment of the present invention uses the following technical solutions:

[0008] 本实用新型实施例的一方面,提供一种阵列基板,包括:由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元包括第一TFT、第二TFT和像素电极,所述第一TFT的栅极连接所述栅线,所述第一TFT的源极连接所述数据线,所述第二TFT的漏极连接所述像素电极。 [0008] In one aspect of the present invention embodiment provides an array substrate, comprising: a vertical and horizontal intersecting gate lines and data lines divided on a substrate a plurality of sub-pixel units, each comprising a first sub-pixel units the TFT, the second TFT and a pixel electrode, the gate of the first TFT is connected to the gate line, a source electrode of the first TFT is connected to the data line, a drain of the second TFT is connected to the pixel electrode.

[0009] 所述第一TFT的源极和漏极与所述第二TFT的栅极形成于同一层,且所述第一TFT的漏极与所述第二TFT的栅极直接相连接。 [0009] The first TFT source and drain electrodes and the gate of the second TFT formed on the same layer, and the drain of the first TFT and the gate of the second TFT is connected directly.

[0010] 所述阵列基板还包括正电源输入Vdd线; [0010] The array substrate further includes a positive power supply input Vdd line;

[0011] 位于同一行的所述子像素单元中的所述第二TFT的源极均与所述Vdd线相连接。 [0011] The sub-pixel units located in the same row in the second source of the TFT are connected to the Vdd line.

[0012] 所述像素电极完全覆盖所述子像素单元区域。 [0012] The sub-pixel electrode completely covers the pixel unit region.

[0013] 所述第一TFT的栅极与所述第二TFT的源极和漏极均形成于所述基板的表面; [0013] The gate of the first TFT and the second TFT source and drain electrodes are formed on the surface of the substrate;

[0014] 所述像素电极通过过孔与所述第二TFT的漏极相连接。 [0014] The pixel electrode is connected to the drain electrode through the via hole and the second TFT.

[0015] 所述第一TFT的栅极、所述第二TFT的源极和漏极以及栅绝缘层通过一次构图工艺形成; A gate [0015] of the first TFT, the second TFT source and drain electrodes and the gate insulating layer is formed through one patterning process;

[0016] 在形成有上述结构的所述基板表面依次形成有有源层、刻蚀阻挡层、所述第一TFT的源极和漏极与所述第二TFT的栅极、树脂层以及所述像素电极。 [0016] surface of the substrate formed with the above-described structure of the active layer are sequentially formed, an etch stop layer of the first TFT and the source and the drain of the second TFT gate electrode, and the resin layer said pixel electrode.

[0017] 所述第二TFT的源极和漏极的边缘均为斜面; [0017] The second TFT source and drain electrodes of both the bevel edge;

[0018] 所述有源层形成在所述第二TFT的源极和漏极之间,通过所述斜面与所述第二TFT的源极和漏极接触。 [0018] The active layer is formed between the second source and drain of the TFT, through the inclined surface and the second TFT source and drain contacts. [0019] 所述过孔中填充有遮光材料; [0019] The via hole is filled with a light shielding material;

[0020] 所述遮光材料的表面与所述像素电极的表面相平。 The surface of the [0020] surface of the light-shielding material and the pixel electrode is flat.

[0021] 所述第一TFT的源极和漏极与所述第二TFT的栅极均形成于所述基板的表面; [0021] The source of the first TFT and a drain gate of the second TFT are formed on the surface of the substrate;

[0022] 所述像素电极通过过孔与所述第二TFT的漏极相连接。 [0022] The pixel electrode is connected to the drain electrode through the via hole and the second TFT.

[0023] 所述第一TFT的源极和漏极、所述第二TFT的栅极以及栅绝缘层通过一次构图工艺形成; [0023] The first TFT source and drain, a gate of the second TFT and the gate insulating layer is formed through one patterning process;

[0024] 在形成有上述结构的所述基板表面依次形成有有源层、刻蚀阻挡层、所述第一TFT的栅极与所述第二TFT的源极和漏极、树脂层以及所述像素电极。 [0024] surface of the substrate formed with the above-described structure of the active layer are sequentially formed, an etch stop layer, a gate electrode of the first TFT and the second TFT source and drain electrodes, the resin layer, and said pixel electrode.

[0025] 所述第一TFT的源极和漏极的边缘均为斜面; [0025] The first TFT and the source and drain are bevel edge;

[0026] 所述有源层形成在所述第一TFT的源极和漏极之间,通过所述斜面与所述第一TFT的源极和漏极接触。 The [0026] active layer is formed between the first TFT source and drain, through the inclined surface of the first TFT and the source and drain contacts.

[0027] 所述过孔中填充有遮光材料; [0027] The via hole is filled with a light shielding material;

[0028] 所述遮光材料的表面与所述像素电极的表面相平。 [0028] The surfaces of the light shielding material and the pixel electrode is flat.

[0029] 本实用新型实施例的另一方面,提供一种OLED显示装置,包括:阵列基板、对电极以及位于所述阵列基板的像素电极与所述对电极之间的有机发光层,所述阵列基板为如上所述的阵列基板。 [0029] Example embodiment of the present invention to another aspect, there is provided an OLED display device, comprising: an array substrate, a pair of electrodes and the pixel electrodes and the array substrate positioned on the organic light emitting layer between the electrodes, the the array substrate of the array substrate described above.

[0030] 本实用新型实施例提供的阵列基板及OLED显示装置,该阵列基板包括由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元又包括第一TFT、第二TFT和像素电极,该第一TFT的源极和漏极与该第二TFT的栅极形成于同一层。 [0030] OLED array substrate and the embodiment of the present invention provides a display device, the array substrate includes a plurality of sub-pixel units by the intersecting horizontal and vertical gate lines and data lines divided on the substrate, each subpixel element including a first TFT, the second TFT and the pixel electrode, the source and the drain of the first TFT and the gate of the second TFT formed on the same layer. 两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极。 With such a two TFT a gate, a bottom gate structure may be such that the gate of the first TFT and the second TFT drain electrode is directly connected to a drain connected to the first TFT and the second TFT may be provided without the gate electrode is connected. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,增大了开口率,提高了显示装置的显示亮度;同时,一顶栅、一底栅的双TFT结构也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序可以减少且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting region, increasing the aperture ratio, improving the display luminance of the display device; while double TFT structure of a top gate, a bottom gate is also such that the substrate is formed from a first metal layer to form the desired final masking step between the pixel electrode can be reduced and without forming a large number of through holes, which will greatly simplify the manufacturing process, reduce the difficulty and cost of production of the product.

附图说明 BRIEF DESCRIPTION

[0031] 为了更清楚地说明本实用新型实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0031] In order to more clearly illustrate the embodiments of the present invention or the technical solution in the prior art, accompanying drawings for describing the embodiments or the prior art described in the introduction required simply Apparently, the description below the drawings are only some embodiments of the present invention embodiments, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings. ·[0032] 图I为现有技术中一种阵列基板的局部结构俯视图; * [0032] Figure I is a partial plan view of the prior art structure of an array substrate;

[0033] 图2为图I的AA向剖视图; [0033] FIG 2 is a cross section taken along line AA I;

[0034] 图3a为本实用新型实施例提供的一种阵列基板的局部结构俯视图; Partial structure of an array substrate [0034] FIG. 3a embodiment the present invention provides a plan view;

[0035] 图3b为图3a的BB向剖视图; [0035] FIG. 3b is a cross section taken along BB of Figure 3a;

[0036] 图4为本实用新型实施例提供的另一阵列基板的结构示意图; [0036] Fig 4 a schematic structural diagram of another embodiment of an array substrate provided by the invention;

[0037] 图5为本实用新型实施例提供的一种OLED显示装置的结构示意图; It means a schematic structural diagram of OLED [0037] FIG. 5 embodiment the present invention provides a display;

[0038] 图6为本实用新型实施例提供的一种阵列基板的制造方法的流程示意图; The flow of the method for manufacturing an array substrate [0038] FIG. 6 embodiment the present invention provides a schematic view;

[0039] 图7a为形成第一金属层和栅绝缘层图案的基板结构示意图; [0039] FIG 7a is formed in the substrate structure and the gate insulating layer, a first metal layer pattern is a schematic diagram;

[0040] 图7b为形成有源层图案的基板结构不意图; [0040] FIG. 7b to form the substrate structure of the active layer pattern are not intended;

[0041] 图7c为形成刻蚀阻挡层图案的基板结构示意图; [0041] Figure 7c is a schematic view of the substrate structure is formed etch stop layer pattern;

[0042] 图7d为形成第二金属层图案的基板结构示意图; [0042] Figure 7d is a schematic view of the substrate structure is formed of a second metal layer pattern;

[0043] 图7e为形成树脂层和像素电极的基板结构示意图; [0043] Figure 7e is a structure of the resin layer and the substrate forming a schematic view of the pixel electrode;

[0044] 图8为本实用新型实施例提供的另一阵列基板的制造方法的流程示意图。 [0044] Figure 8 is a schematic flow diagram of another method of manufacturing the array substrate of the embodiment of the invention provided.

具体实施方式 detailed description

[0045] 下面将结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本实用新型一部分实施例,而不是全部的实施例。 [0045] below with reference to the present invention, the embodiment of the drawings, the present invention embodiment of the technical solution will be clearly and completely described, obviously, the described embodiments are merely embodiments of the present invention a part, rather than all embodiments. 基于本实用新型中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型保护的范围。 Based on the embodiments of the present invention, all other embodiments to those of ordinary skill in the art without any creative effort shall fall within the scope of protection of the present invention.

[0046] 本实用新型实施例提供的阵列基板30,如图3a所示,包括:由横纵交叉的栅线31和数据线32在基板300上划分出的多个子像素单元,每个子像素单元包括第一TFT33、第二TFT34和像素电极35,第一TFT33的栅极331连接栅线31,第一TFT33的源极332连接数据线32,第二TFT34的漏极343连接像素电极35。 The array substrate 30 [0046] embodiment of the present invention is provided in FIG. 3a, comprising: 32 a plurality of sub-pixel cells partitioned on the substrate 300 by the intersecting horizontal and vertical gate lines 31 and data lines, each sub-pixel unit It includes a first TFT 33, the pixel electrode 35 and the second TFT34, the first TFT 33 gate electrode 331 connected to the gate line 31, the source electrode 332 of the first TFT 33 connected to the data line 32, a drain connected to the second pixel electrode 343 of TFT34 35.

[0047] 其中,如图3b所示,第一TFT33的源极332和漏极333与第二TFT34的栅极341形成于同一层,且第一TFT33的漏极333与第二TFT34的栅极341直接相连接。 [0047] wherein, shown in Figure 3b, a first electrode 332 and a source of TFT33 drain electrode 333 and the gate 341 of the second TFT34 is formed in the same layer, and the first drain electrode 333 and the gate of TFT33 to TFT34 second 341 is directly connected.

[0048] 本实用新型实施例提供的阵列基板,包括由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元又包括第一TFT、第二TFT和像素电极,该第一TFT的源极和漏极与该第二TFT的栅极形成于同一层。 [0048] The array substrate of the present invention provides an embodiment comprising a plurality of sub-pixel units by the intersecting horizontal and vertical gate lines and data lines divided on the substrate, each subpixel element including a first TFT, a second TFT and a pixel electrode, the source and gate of the drain of the first TFT and the second TFT are formed on the same layer. 两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极。 With such a two TFT a gate, a bottom gate structure may be such that the gate of the first TFT and the second TFT drain electrode is directly connected to a drain connected to the first TFT and the second TFT may be provided without the gate electrode is connected. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,增大了开口率,提高了显示装置的显示亮度;同时,一顶栅、一底栅的双TFT结构也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting region, increasing the aperture ratio, improving the display luminance of the display device; while double TFT structure of a top gate, a bottom gate is also such that the desired substrate between the pixel electrode is formed from the mask to the final step of forming a first metal layer decreased from the prior art and six times to seven times without forming a large number of through holes, which will greatly simplify the production process, effective reduced production difficulties and production costs.

[0049] 需要说明的是,阵列基板30还包括正电源输入Vdd线36。 [0049] Incidentally, the array substrate 30 further includes a positive power supply input Vdd line 36. 在实际应用中,位于同一行的子像素单元中的第二TFT的源极均可以与该Vdd线相连接。 In practice, the sub-pixel units located in the same row of the second TFT source can be connected to the Vdd line.

[0050] 进一步地,在如图3a所示的阵列基板3中,像素电极35可以完全覆盖子像素单元区域。 [0050] Further, in the array substrate 3a shown in FIG. 3, the pixel electrode 35 may completely cover the sub-pixel unit. [0051] 在本实用新型实施例中,由于两个TFT分别采用一顶栅、一底栅的结构,其中,第一TFT的漏极应当与第二TFT的栅极直接相连接。 [0051] In the embodiment of the present invention, since the use of a two-gate TFT, respectively, a bottom gate structure, wherein the drain of the first TFT and the gate electrode of the second TFT should be directly connected. 因此在实际应用的过程中,阵列基板具体可以包括第一TFT仍然采用底栅结构、而第二TFT采用顶栅结构的阵列基板,或者第一TFT采用顶栅结构、而第二TFT仍然采用底栅结构的阵列基板。 Thus, in actual applications, the array substrate may include a first TFT specifically still uses a bottom-gate structure, and the second TFT array substrate using a top-gate structure, or a first top-gate structure TFT, the second TFT bottom still using the array substrate gate structure.

[0052] 在如图3b所示的阵列基板30中,即是以第一TFT仍然采用底栅结构、而第二TFT采用顶栅结构的阵列基板为例进行的说明。 [0052] In the array substrate 30 shown in Figure 3b, i.e., the first TFT is a bottom gate structure is still used, and the second TFT array substrate using a top-gate structure described in the example.

[0053] 如图3b所示,第一TFT33的栅极331与第二TFT34的源极342和漏极343均形成于基板300的表面。 [0053] shown in Figure 3b, a first gate electrode 331 and the second TFT33 to TFT34 source 342 and the drain electrode 343 are formed on the surface of the substrate 300.

[0054] 具体的,基板300具体可以是包括玻璃基板或透明树脂基板在内的透明基板。 [0054] Specifically, the substrate 300 may be specifically included a glass substrate or a transparent resin substrate having a transparent substrate. 在基板300的表面可以沉积金属层和栅绝缘层,通过一次构图工艺处理该金属层和栅绝缘层最终形成第一TFT33的栅极331、第二TFT34的源极342和漏极343以及栅绝缘层301的图形。 The surface of the substrate 300 may be a metal deposited layer and the gate insulating layer, forming a first gate electrode 331 by TFT33 a patterning process of the metal layer and the gate insulating layer, a second TFT34 source 342 and the drain 343 and the gate insulating graphics layer 301.

[0055] 像素电极35可以通过过孔c与第二TFT34的漏极343相连接。 [0055] The pixel electrode 35 may be a drain hole 343 c is connected via a second through TFT34.

[0056] 进一步地,可以在第一TFT33的栅极331与第二TFT34的源极342和漏极343的表面依次形成有有源层302、刻蚀阻挡层303、第一TFT33的源极332和漏极333与第二TFT34的栅极341、树脂层304以及像素电极35。 [0056] Further, the active layer may be sequentially formed on the first gate electrode 331 and the source of TFT33 to TFT34 second surface 342 and the drain electrode 343 302, the etch stop layer 303, a first source electrode 332 TFT33 and a drain electrode 333 and the gate 341, the pixel electrode 304 and the resin layer 35 of the second TFT34.

[0057] 具体的,需要通过6次构图工艺以逐层形成包括第一TFT33的栅极331、第二TFT34的源极342和漏极343、有源层302、刻蚀阻挡层303、第一TFT33的源极332和漏极333与第二TFT34的栅极341、树脂层304以及像素电极35。 [0057] Specifically, it is necessary to form a layer by layer 6 by patterning process comprising a first gate electrode 331 TFT33 second TFT34 source 342 and the drain electrode 343, the active layer 302, the etch stop layer 303, a first TFT33 source 332 and the drain electrode 333 and the gate 341, the pixel electrode 304 and the resin layer 35 of the second TFT34. 其中,以上各层级结构在位于第二TFT34的漏极343上方处均应当具有开口区域,以形成底部为第二TFT34的漏极343的过孔C。 Wherein, in the above hierarchy 343 of the drain is located above the second TFT34 shall have an open region to form a second bottom TFT34 via a drain 343 C.

[0058] 进一步地,第二TFT34的源极342和漏极343的边缘均可以为斜面,有源层302可以形成在第二TFT34的源极342和漏极343之间,通过该斜面与第二TFT34的源极342和漏极343接触,如图3b所示,有源层302可以形成在第二TFT34的源极342和漏极343之间。 [0058] Further, the second TFT34 source 342 and the drain 343 may each be an edge bevel, the active layer 302 may be formed between the electrode 342 and the drain 343 of a second source of TFT34, by the first bevel two TFT34 source electrode 342 and the drain contact 343, shown in FIG. 3B, the active layer 302 may be formed between the second source of TFT34 342 and the drain electrode 343.

[0059] 这样一来,可以保证第二TFT34的源极342和漏极343均与有源层302具有较大的接触面,从而确保了源漏极与有源层之间的电连接的稳定性,进一步提高了显示装置产品的质量。 [0059] Thus, the second TFT34 source 342 and the drain electrode can be guaranteed 343 has a larger contact area with the active layer 302, thereby ensuring a stable connection between the source and drain electrodes electrically connected to the active layer , and further improve the quality of the display device products.

[0060] 进一步地,过孔c中可以填充有遮光材料37,该遮光材料37的表面可以与像素电极35的表面相平。 [0060] Further, the via hole c, 37 may be filled with a light shielding material, a surface of the light shielding material 37 may be flush with the surface of the pixel electrode 35.

[0061] 在阵列基板的制作过程中,为了避免不必要的暗态漏光,通常需要在子像素单元边缘处,即栅线和数据线位置处形成一层黑矩阵,过孔c中填充的遮光材料37可以与子像素单元边缘处的黑矩阵在同一次构图工艺中形成。 Shielding [0061] in the production process of the array substrate, in order to avoid unnecessary light leakage, usually required in subpixel units at the edge, i.e. at the location of the gate and data lines form a black matrix, filled vias c material 37 may be formed with the black matrix at the edges of the sub-pixel units in a same patterning process. 这样一来,可以确保位于像素电极上的有机发光层厚度均匀,从而保证了子像素单元各个区域的有机发光层的发光量一致,提高了显示装置的显示质量。 Thus, to ensure a uniform pixel electrode positioned on the organic light-emitting layer thickness, thus ensuring uniform light emission amount of the organic light emitting layer in each sub-pixel region units, to improve the display quality of the display device.

[0062] 采用本实用新型实施例提供的这样一种阵列基板,两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极,令像素电极覆盖整个子像素区域。 [0062] The embodiment of the present invention to provide such an array substrate, a two TFT using a top gate, a bottom gate structure may be such that the drain and the gate of the first TFT, a second TFT directly is connected, it can be provided without connecting the drain electrode of the first TFT and the second TFT connected to the gate, so that the pixel electrode covers the entire sub-pixel region. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,提高了显示装置的显示亮度;同时,一顶栅、一底栅的双TFT结构也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting area, improving the display luminance of the display device; while double TFT structure of a top gate, a bottom gate makes from the substrate forming a first the final metal layer to form the desired masking step between the pixel electrode is decreased from the prior art to 6 and 7 without forming a large number of through holes, which will greatly simplify the manufacturing process, reduce the difficulty of the production and production costs.

[0063] 或者,本实用新型实施例提供的阵列基板30还可以如图4所示,其中,第一TFT采用顶栅结构、而第二TFT仍然采用底栅结构的阵列基板。 [0063] Alternatively, the array substrate 30 of the present invention may also be provided in the embodiment shown in Figure 4, wherein the first top-gate structure TFT, the second TFT array substrate still using a bottom gate structure.

[0064] 如图4所示,第一TFT33的源极332和漏极333与第二TFT34的栅极341均形成于基板300的表面。 [0064] As shown in FIG. 4, a first source electrode 332 TFT33 and the drain electrode 333 and the second gate electrode 341 TFT34 are formed on the surface of the substrate 300.

[0065] 像素电极35同样可以通过过孔d与第二TFT34的漏极343相连接。 [0065] The pixel electrode 35 may also be the drain hole 343 d is connected by a second through TFT34. 由于第二TFT34的漏极343位于第二TFT34的顶部,与前述实施例中的过孔c相比,这样一种结构的过孔d只需穿透树脂层而无需穿透栅绝缘层以及刻蚀阻挡层,这样一来使得过孔的制作变得相对简单,从而进一步降低了显示装置的生产难度。 Since the drain 343 at the top of the second TFT34 to TFT34 second, embodiment of the vias in comparison with the preceding embodiments c, such a configuration simply through hole penetrating d layer without penetrating the resin insulating layer and a gate cut etching the barrier layer, so that to create through-hole becomes relatively simple, further reducing the difficulty of producing the display device.

[0066] 与前述实施例类似的,在基板300的表面可以沉积金属层和栅绝缘层,通过一次构图工艺处理该金属层和栅绝缘层最终形成第一TFT33的源极332和漏极333、第二TFT34的栅极341以及栅绝缘层301的图形。 [0066] Similar to the foregoing embodiment, the surface of the substrate 300 may be a metal deposited layer and the gate insulating layer, a first electrode forming the final TFT33 source 332 and the drain electrode 333 through one patterning process of the metal layer and the gate insulating layer, a second gate electrode pattern TFT34 341 and the gate insulating layer 301.

[0067] 进一步地,可以在第一TFT33的源极332和漏极333与第二TFT34的栅极341的表面依次形成有栅绝缘层301、有源层302、刻蚀阻挡层303、第一TFT33的栅极331与第二TFT34的源极342和漏极343、树脂层304以及像素电极35。 [0067] Further, the drain electrode 333 may be sequentially formed, and the surface of the second electrode 332 TFT34 gate 341 in the first source of TFT33 gate insulating layer 301, the active layer 302, the etch stop layer 303, a first TFT33 second gate 331 and the source electrode 342 and the drain of TFT34 343, the resin layer 304 and the pixel electrode 35.

[0068] 在本实用新型实施例所提供的阵列基板中,同样需要通过6次构图工艺以逐层形成包括第一TFT33的源极332和漏极333、第二TFT34的栅极341以及栅绝缘层301、有源层302、刻蚀阻挡层303、第一TFT33的栅极331与第二TFT34的源极342和漏极343、树脂层304以及像素电极35。 [0068] In the array substrate of the present invention is provided in the embodiment, the same need to form a layer by layer comprising a first source of TFT33 332 and the drain electrode 333 through the patterning process 6, the second gate electrode 341 and the gate of TFT34 insulating layer 301, the active layer 302, the etch stop layer 303, a first gate electrode 331 and the second TFT33 to TFT34 source 342 and the drain electrode 343, the resin layer 304 and the pixel electrode 35. 这样,在基板上从形成第一层金属层到最终形成像素电极共需经历6次掩膜工序。 Thus, a first layer is formed from a metal layer on a substrate to form a final total of the pixel electrodes undergoes six mask processes.

[0069] 采用这样一种结构的阵列基板,由于第一TFT的漏极与第二TFT的栅极形成于同一层且直接相连接,从而进一步简化了生产工艺。 [0069] The array substrate of such a structure, since the drain and the gate of the first TFT, a second TFT formed on the same layer and is connected directly, thereby further simplifying the manufacturing process.

[0070] 进一步地,第一TFT33的源极332和漏极333的边缘均为斜面,有源层302可以形成在第一TFT33的源极332和漏极333之间,通过该斜面与第一TFT33的源极332接触,如图4所示,有源层302可以形成在第一TFT33的源极332和漏极333之间。 [0070] Further, the edge 332 and the drain electrode 333 of a first source of TFT33 are slant, the active layer 302 may be formed between the electrode 332 and the drain 333 of a first source of TFT33, by the first inclined surface and 333 between the electrode 332 and the drain electrode 332 contacting the source of TFT 33, as shown in FIG. 4, the active layer 302 may be formed in the first TFT 33 source. [0071] 这样一来,可以保证第二TFT34的源极342和漏极343均与有源层302具有较大的接触面,从而确保了源漏极与有源层之间的电连接的稳定性,进一步提高了显示装置产品的质量。 [0071] Thus, the second TFT34 source 342 and the drain electrode can be guaranteed 343 has a larger contact area with the active layer 302, thereby ensuring a stable connection between the source and drain electrodes electrically connected to the active layer , and further improve the quality of the display device products.

[0072] 进一步地,与前述实施例类似的,过孔d中同样可以填充有遮光材料37,该遮光材料37的表面可以与像素电极35的表面相平。 [0072] Further, similar to the previous embodiment, the vias may be filled with d in the same light shielding material 37, the surface of the light shielding material 37 may be flush with the surface of the pixel electrode 35.

[0073] 采用本实用新型实施例提供的这样一种阵列基板,两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连·,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极,令像素电极覆盖整个子像素区域。 [0073] The embodiment of the present invention to provide such an array substrate, a two TFT using a top gate, a bottom gate structure may be such that the drain and the gate of the first TFT, a second TFT directly · connected, it can be provided without connecting the drain electrode of the first TFT and the second TFT connected to the gate, so that the pixel electrode covers the entire sub-pixel region. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,增大了开口率,提高了显示装置的显示亮度;另一方面,该结构的采用也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting region, an aperture ratio is increased, improving the display luminance of the display device; on the other hand, also makes use of the structure of the substrate is formed from a metal layer to form the desired final masking step between the pixel electrode is decreased from the prior art to 6 and 7 without forming a large number of through holes, which will greatly simplify the manufacturing process, reduce the production of products the difficulty and cost of production.

[0074] 本实用新型实施例提供的阵列基板可以广泛地适用于各种现有的OLED显示装置中。 The array substrate [0074] embodiment of the present invention may be provided in a variety of widely applicable to a conventional OLED display device. 例如,在如图5所示的OLED显示装置50中,该OLED显示装置50具体可以包括: For example, as shown in FIG. 5 OLED display device 50, the OLED display device 50 may specifically comprise:

[0075] 阵列基板30、对电极51以及位于阵列基板30的像素电极35与对电极51之间的有机发光层52,其中,阵列基板30可以为如上所述的阵列基板30。 [0075] The array substrate 30, counter electrode 51 and the pixel electrode on the array substrate 30 and an organic light-emitting layer 35 between the electrodes 51 52, wherein the array substrate 30 may be an array substrate 30 as described above.

[0076] 需要说明的是,在本实用新型实施例中,OLED显示装置50中的阵列基板30是以图3b所示的阵列基板30为例进行的说明,而并不是对本实用新型所做的限制。 [0076] Incidentally, in the embodiment of the present invention, the OLED display device 50 of the array substrate 30 is described array substrate 30 shown in Figure 3b is an example, but the present invention is not done limit.

[0077] 由于阵列基板30的结构在前述实施例中已做了详细的描述,故此处不再赘述。 [0077] Since the structure of the array substrate 30 in the foregoing embodiments have been described in detail, it is not repeated herein.

[0078] 本实用新型实施例提供的OLED显示装置,包括阵列基板,该阵列基板包括由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元又包括第一TFT、第二TFT和像素电极,该第一TFT的源极和漏极与该第二TFT的栅极形成于同一层。 [0078] OLED of the present invention embodiment provides a display device includes an array substrate, the array substrate includes a plurality of sub-pixel units intersecting the vertical and horizontal gate lines and data lines divided on the substrate, each subpixel element including a first a TFT, the second TFT and the pixel electrode, the source and the drain of the first TFT and the gate of the second TFT formed on the same layer. 两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极。 With such a two TFT a gate, a bottom gate structure may be such that the gate of the first TFT and the second TFT drain electrode is directly connected to a drain connected to the first TFT and the second TFT may be provided without the gate electrode is connected. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,提高了显示装置的显示亮度;另一方面,由于采用底栅和顶栅相结合的方式,也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting area, improving the display luminance of the display device; the other hand, since the bottom-gate and top gate way combination, but also from the substrate such that a first metal layer formed between the pixel electrodes required for a mask is formed to the final reduction step from the prior art and six times to seven times without forming a large number of through holes, which will greatly simplify the manufacturing process, effectively reducing the product production difficulty and cost of production.

[0079] 本实用新型实施例提供的阵列基板的制造方法如图6所示,包括: [0079] The method of manufacturing the array substrate of the present invention is provided by the embodiment shown in FIG. 6, comprising:

[0080] S601、在基板上分别形成第一TFT的栅极、第二TFT的源极和漏极以及栅绝缘层的图形。 [0080] S601, respectively, are formed on the substrate gate of the first TFT, the second TFT source electrode pattern and a drain and a gate insulating layer.

[0081] 具体的,由于第一TFT的栅极需要与栅线相连接,同时第二TFT的源极需要与正电源输入Vdd线连接,因此可以在基板上通过一次构图工艺分别形成栅线、Vdd线、第一TFT的栅极、第二TFT的源极和漏极以及栅绝缘层的图形。 [0081] Specifically, since the gate of the first TFT is connected to the gate line needs, while a second source of the TFT needs to positive power supply input Vdd line, the gate line can be formed through one patterning process on the substrate, respectively, Vdd line, a gate of the first TFT, the second TFT source and drain electrodes and the gate insulating layer pattern.

[0082] S602、在该第一TFT的栅极与该第二TFT的源极和漏极的表面通过构图工艺依次形成栅绝缘层、有源层以及刻蚀阻挡层的图形。 [0082] S602, the insulating layer pattern, the active layer and the etch stop layer in the gate of the first surface of the second TFT and the TFT source and drain electrode forming a gate by patterning process.

[0083] 其中,第二TFT的源极和漏极的边缘均可以为斜面,有源层302可以形成在第二TFT34的源极342和漏极343之间,通过该斜面与第二TFT34的源极342和漏极343接触。 [0083] wherein the second TFT source and drain electrodes may each be an edge bevel, the active layer 302 may be formed between the second source electrode 342 and the drain of TFT34 343, through the inclined surface and the second TFT34 The source 342 and drain 343 contacts.

[0084] S603、形成该第一TFT的源极和漏极与该第二TFT的栅极的图形。 [0084] S603, forming the first TFT and the source and drain electrodes of the second pattern of the gate of the TFT. [0085] 具体的,由于第一TFT的源极需要与数据线相连接,因此可以通过一次构图工艺分别形成数据线、第一TFT的源极和漏极与第二TFT的栅极的图形。 [0085] Specifically, since the first TFT source electrode connected to the data lines needed, can be formed through one patterning process each data line, the first TFT source and drain and the gate of the second TFT pattern.

[0086] S604、形成具有过孔的树脂层,该过孔的底部为该第二TFT的漏极。 [0086] S604, a resin layer having a via hole, the drain of the second TFT for the bottom of the via hole.

[0087] S605、形成像素电极,该像素电极通过该过孔与第二TFT的漏极相连接。 [0087] S605, a pixel electrode, the pixel electrode connected to the drain of the second TFT through the via hole.

[0088] 本实用新型实施例提供的阵列基板的制造方法,该阵列基板包括由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元又包括第一TFT、第二TFT和像素电极,该第一TFT的源极和漏极与该第二TFT的栅极形成于同一层。 [0088] The method of manufacturing the array substrate of the present invention is provided by the embodiment, the array substrate includes a plurality of sub-pixel units by the intersecting horizontal and vertical gate lines and data lines divided on the substrate, each subpixel element including a first TFT , the second TFT and the pixel electrode, the source and the drain and the gate of the first TFT and the second TFT are formed on the same layer. 两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极。 With such a two TFT a gate, a bottom gate structure may be such that the gate of the first TFT and the second TFT drain electrode is directly connected to a drain connected to the first TFT and the second TFT may be provided without the gate electrode is connected. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,提高了显示装置的显示亮度;另一方面,由于采用底栅和顶栅相结合的方式,也使得基板从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting area, improving the display luminance of the display device; the other hand, since the bottom-gate and top gate way combination, but also from the substrate such that a first metal layer formed between the pixel electrodes required for a mask is formed to the final reduction step from the prior art and six times to seven times without forming a large number of through holes, which will greatly simplify the manufacturing process, effectively reducing the product production difficulty and cost of production. · ·

[0089] 进一步地,如图6所示,阵列基板的制造方法还可以包括: [0089] Further, as shown in FIG. 6, the method of manufacturing the array substrate may further comprise:

[0090] S606、在形成有像素电极的该阵列基板的过孔中填充遮光材料,该遮光材料的表面与该像素电极的表面相平。 [0090] S606, via the pixel electrode is formed in the array substrate of the light shielding material is filled, the surface of the light shielding material with a surface of the pixel electrode is flat.

[0091] 在阵列基板的制作过程中,为了避免不必要的暗态漏光,通常需要在子像素单元边缘处,即栅线和数据线位置处形成一层黑矩阵,过孔c中填充的遮光材料可以与子像素单元边缘处的黑矩阵在同一次构图工艺中形成。 Shielding [0091] in the production process of the array substrate, in order to avoid unnecessary light leakage, usually required in subpixel units at the edge, i.e. at the location of the gate and data lines form a black matrix, filled vias c the black matrix material may be formed at an edge of the sub-pixel units in a same patterning process. 这样一来,可以确保像素电极上的有机发光层厚度均匀,从而保证了子像素单元各个区域的有机发光层的发光量一致,提高了显示装置的显示质量。 Thus, to ensure uniform thickness of the organic light emitting layer on the pixel electrode, so as to ensure a consistent amount of light emission region of the organic light emitting layer in each sub-pixel unit, improving the display quality of the display device.

[0092] 以下对本实用新型实施例所提供的阵列基板的制造方法进行举例说明。 [0092] Hereinafter, the method of manufacturing the array substrate of the present invention will be provided by the embodiments illustrated.

[0093] 首先,需要在基板300上沉积第一金属层和栅绝缘层301,经过曝光、显影、刻蚀后得到图7a所示的图形结构,其中,第一金属层分别形成栅线31、Vdd线36 (栅线31和Vdd线36图7a中未示出)、第一TFT33的栅极331与第二TFT34的源极342和漏极343的图形,栅绝缘层301仅覆盖有金属存在的区域。 [0093] First, the substrate 300 needs to be deposited on the first metal layer and the gate insulating layer 301, exposed and developed, the resulting pattern is etched structure shown in FIG 7a, wherein the first metal layer 31 forming the gate line, respectively, Vdd line 36 (the gate line 31 and the Vdd line 36, not shown in FIG. 7a), a first pattern 331 and the gate of TFT33 to TFT34 second source 342 and drain 343, a gate insulating layer 301 covers only the presence of metal Area. 进一步地,可以通过控制成膜和刻蚀条件,令第二TFT34的源极342和漏极343均有较小坡度角,边缘为一斜面。 Further, by controlling the deposition and etching conditions, so that a second source of TFT34 342 and the drain electrode 343 are smaller slope angle, a bevel edges.

[0094] 直接在形成上述结构的基板300上沉积有源层302,经曝光、显影、刻蚀后得到图形化的有源层结构,其中,该有源层可以选择IGZ0(indium gallium zinc oxide,铟镓锌氧化物)材料制成,且该有源层302可以填充在第二TFT34的源极342和漏极343之间,其结构可以如图7b所示。 [0094] directly deposited on the substrate 300 to form the structure of the active layer 302, exposed, developed, etched to obtain a patterned after the active layer structure, wherein the active layer can be selected IGZ0 (indium gallium zinc oxide, made of indium gallium zinc oxide) material, and the active layer 302 may be filled between the electrode 342 and the drain 343 of a second source of TFT34, their structures shown in Figure 7b.

[0095] 接下来,如图7c所示,在基板300上沉积氧化硅材料形成刻蚀阻挡层303,刻蚀完成后得到的图形在第一TFT33位置与现有技术的结构一样都是充当刻蚀保护层,刻蚀阻挡层303在第二TFT34的漏极343位置处需要留出过孔c的图形,并将下层的栅绝缘层301一起刻蚀完全,同时在其他位置处覆盖基板表面以充当绝缘层。 [0095] Next, as shown in Figure 7c, the substrate 300 is deposited on a silicon oxide etch stop layer 303 forming material, after the completion of the etching pattern as obtained with the structure of the prior art are in a first position acts as a moment TFT33 etching the protective layer, the etch stop layer 303 at the position of the second drain electrode 343 need to leave the TFT34 via hole pattern c, the gate insulating layer 301 and the lower layer is completely etched together, while covering the surface of the substrate at other locations act as an insulating layer.

[0096] 在基板300上沉积第二金属层,经曝光、显影、刻蚀后得到图7d所示的结构。 [0096] depositing a second metal layer on the substrate 300, exposed and developed, etching the structure shown in FIG. 7d. 该段工艺中,数据线32、第一TFT33的源极332和漏极333与第二TFT34的栅极341的图形同时形成,且第一TFT33的源极332与第二TFT34的栅极341直接连接。 The process section, and a drain electrode 332 and the gate 333 of the second pattern 341 TFT34 32, a first source of TFT33 data lines are simultaneously formed, the gate electrode 332 and the first and second TFT34 to TFT33 source 341 directly connection.

[0097] 在基板300上涂覆树脂层并对其进行曝光、显影,得到在第二TFT34的漏极343处开口的树脂层304,然后再沉积像素电极层,通过构图工艺处理后形成分别覆盖单个子像素区域的像素电极35,其结构如图7e所示。 [0097] In the coating resin layer on the substrate 300 and subjected to exposure and development to obtain a resin layer 304 at the drain of TFT34 second opening 343, and then depositing a pixel electrode layer, are formed by covering the patterning process single sub-pixel region of the pixel electrode 35, the structure shown in FIG. 7e.

[0098] 在基板300上涂覆黑色树脂,通过构图工艺处理后得到黑矩阵图形,其正面投影与数据线和栅线的投影重合,且线宽略大于数据线和栅线。 [0098] In the black resin is coated on the substrate 300, and patterning the black matrix pattern obtained after processing, front projection projector which coincides with the data line and the gate line, and the line width slightly greater than the data line and the gate line. 同时,在过孔c中也填充了与像素电极35上表面齐平的遮光材料37,从而最终得到如图3b所示的阵列基板。 Meanwhile, the through hole is also filled with the c light shielding material 37 and the pixel electrode 35 is flush with the surface, thereby finally obtain the array substrate shown in FIG. 3b. 该结构可以保证上层有机发光体厚度的均匀性,保证了显示装置亮度的均匀。 This structure can ensure the uniformity of the thickness of the upper layer of the organic light emitting material, means to ensure uniform display brightness.

[0099] 在本实用新型实施例中,由于两个TFT分别采用一顶栅、一底栅的结构,其中,第一TFT的漏极应当与第二TFT的栅极直接相连接。 [0099] In the embodiment of the present invention, since the use of a two-gate TFT, respectively, a bottom gate structure, wherein the drain of the first TFT and the gate electrode of the second TFT should be directly connected. 因此在实际应用的过程中,阵列基板具体可以包括第一TFT仍然采用底栅结构、而第二TFT采用顶栅结构的阵列基板,或者第一TFT采用顶栅结构、而第二TFT仍然采用底栅结构的阵列基板。 Thus, in actual applications, the array substrate may include a first TFT specifically still uses a bottom-gate structure, and the second TFT array substrate using a top-gate structure, or a first top-gate structure TFT, the second TFT bottom still using the array substrate gate structure. 在上述实施例中,即是以第一TFT仍然采用底栅结构、而第二TFT采用顶栅结构的阵列基板为例进行的说明。 In the above embodiment, i.e., the first TFT is a bottom gate structure is still used, and the second TFT array substrate using a top-gate structure described in the example. [0100] 在阵列基板中,若第一TFT采用顶栅结构、而第二TFT仍然采用底栅结构,该阵列基板的制造方法如图8所示,包括: [0100] In the array substrate, if the first TFT top-gate structure, and the second bottom-gate structure TFT is still used, the method of manufacturing the array substrate shown in Figure 8, comprising:

[0101] S801、在基板上分别形成第一TFT的源极和漏极、第二TFT的栅极以及栅绝缘层的图形。 [0101] S801, respectively, are formed on a substrate of a first TFT source and drain electrodes, the second TFT gate pattern and a gate insulating layer.

[0102] 具体的,由于第一TFT的源极需要与数据线相连接,因此可以在基板上通过一次构图工艺分别形成数据线、第一TFT的源极和漏极、第二TFT的栅极以及栅绝缘层的图形。 [0102] Specifically, since the first TFT source electrode connected to the data lines needed, can be formed on the substrate by a patterning process of the data lines, respectively, the first TFT source and drain electrodes, the gate of the second TFT and the gate insulating layer pattern.

[0103] S802、在该基板的表面通过构图工艺依次形成有源层以及刻蚀阻挡层的图形。 [0103] S802, an active layer pattern is formed and etching the barrier layer by a patterning process on the surface of the substrate sequentially.

[0104] 其中,第一TFT的源极和漏极的边缘均为斜面,有源层302可以形成在第一TFT33的源极332和漏极333之间,通过该斜面与第一TFT33的源极332接触。 [0104] wherein the first edge of the TFT source and drain are inclined surfaces, the active layer 302 may be formed between the electrode 332 and the drain 333 of a first source of TFT33, by the inclined surface and the first source of TFT33 pole 332 contacts.

[0105] S803、形成该第一TFT的栅极与该第二TFT的源极和漏极的图形。 [0105] S803, forming a gate pattern of the first TFT and the second TFT source and drain.

[0106] 具体的,由于第一TFT的栅极需要与栅线相连接,同时第二TFT的源极需要与正电源输入Vdd线连接,因此可以通过一次构图工艺分别形成栅线、Vdd线、第一TFT的栅极与第二TFT的源极和漏极的图形。 [0106] Specifically, since the gate of the first TFT is connected to the gate line needs, while a second source of the TFT needs to positive power supply input Vdd line, the gate line can be formed, through one patterning process line Vdd, respectively, the gate of the first TFT and the source and the drain of the pattern of the second TFT.

[0107] S804、形成具有过孔的树脂层,该过孔的底部为第二TFT的漏极。 [0107] S804, a resin layer having a via hole, the via hole to the bottom drain of the second TFT.

[0108] S805、形成像素电极,该像素电极通过该过孔与第二TFT的漏极相连接。 [0108] S805, a pixel electrode, the pixel electrode connected to the drain of the second TFT through the via hole.

[0109] 本实用新型实施例提供的阵列基板的制造方法,该阵列基板包括由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元又包括第一TFT、第二TFT和像素电极,该第一TFT的源极和漏极与该第二TFT的栅极形成于同一层。 [0109] The method of manufacturing the array substrate of the present invention is provided by the embodiment, the array substrate includes a plurality of sub-pixel units by the intersecting horizontal and vertical gate lines and data lines divided on the substrate, each subpixel element including a first TFT , the second TFT and the pixel electrode, the source and the drain and the gate of the first TFT and the second TFT are formed on the same layer. 两个TFT采用这样一种一顶栅、一底栅的结构,可以使得第一TFT的漏极与第二TFT的栅极直接相连,从而可以无需设置连接第一TFT的漏极与第二TFT的栅极的连接电极。 With such a two TFT a gate, a bottom gate structure may be such that the gate of the first TFT and the second TFT drain electrode is directly connected to a drain connected to the first TFT and the second TFT may be provided without the gate electrode is connected. 这样一来,可以减少黑矩阵的覆盖面积,从而显著增加了有效发光区域的面积,提高了显示装置的显示亮度;另一方面,由于采用底栅和顶栅相结合的方式,也使得从形成第一层金属层到最终形成像素电极之间所需的掩膜工序由现有技术中的7次减少到6次且无需形成大量的过孔,这将大大简化制作工艺,有效降低了产品的生产难度和生产成本。 Thus, it is possible to reduce the coverage area of ​​the black matrix, thereby significantly increasing the area of ​​the effective light emitting area, improving the display luminance of the display device; the other hand, since the bottom-gate and top gate way combination, but also from the so formed the first metal layer to form the desired final masking step between the pixel electrode is decreased from the prior art to 6 and 7 without forming a large number of through holes, which will greatly simplify the manufacturing process, effectively reducing the product production difficulty and cost of production.

[0110] 进一步地,如图8所示,阵列基板的制造方法还可以包括: [0110] Further, as shown in FIG. 8, the method of manufacturing the array substrate may further comprise:

[0111] S806、在形成有像素电极的该阵列基板的过孔中填充遮光材料,该遮光材料的表面与该像素电极的表面相平。 [0111] S806, via the pixel electrode is formed in the array substrate of the light shielding material is filled, the surface of the light shielding material with a surface of the pixel electrode is flat.

[0112] 采用这样一种方法制作的阵列基板如图4所示,由于第二TFT34的漏极343位于第二TFT34的顶部,与前述实施例中的过孔c相比,这样一种结构的过孔d只需穿透树脂层而无需穿透栅绝缘层以及刻蚀阻挡层,这样一来使得过孔的制作变得相对简单,从而进一步降低了显示装置的生产难度。 [0112] With such a method of manufacturing an array substrate shown in Figure 4, since the drain 343 at the top of the second TFT34 to TFT34 second, embodiment of the vias in comparison with the preceding embodiments c, such a configuration d hole penetrating through the resin layer only, without penetrating the gate insulating layer and the etch stop layer, so that to create through-hole becomes relatively simple, further reducing the difficulty of producing the display device.

[0113] 以上所述,仅为本实用新型的具体实施方式,但本实用新型的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本实用新型的保护范围之内。 [0113] The above are only the present invention specific embodiments, the scope of protection of the present invention is not limited thereto, any skilled in the art in the art within the technical scope disclosed in the present invention can be easily variations or replacement that, shall fall within the scope of the present invention. 因此,本实用新型的保护范围应以所述权利要求的保护范围为准。 Accordingly, the scope of protection of the present invention should be defined by the scope of the claims.

Claims (12)

  1. 1. 一种阵列基板,包括:由横纵交叉的栅线和数据线在基板上划分出的多个子像素单元,每个子像素单元包括第一TFT、第二TFT和像素电极,所述第一TFT的栅极连接所述栅线,所述第一TFT的源极连接所述数据线,所述第二TFT的漏极连接所述像素电极,其特征在于, 所述第一TFT的源极和漏极与所述第二TFT的栅极形成于同一层,且所述第一TFT的漏极与所述第二TFT的栅极直接相连接。 1. An array substrate, comprising: a vertical and horizontal intersecting the gate lines and data lines divided on the substrate a plurality of sub-pixel units, each unit comprising a first sub-pixel TFT, a second TFT and a pixel electrode, the first TFT connected to the gate of the gate line, a source electrode of the first TFT is connected to the data line, the pixel electrode connected to the drain of the second TFT, wherein a source electrode of the first TFT a drain and a gate of the second TFT formed on the same layer, and the drain of the first TFT and the gate of the second TFT is connected directly.
  2. 2.根据权利要求I所述的阵列基板,其特征在于,所述阵列基板还包括正电源输入Vdd线. 位于同一行的所述子像素单元中的所述第二TFT的源极均与所述Vdd线相连接。 The array substrate of claim I, wherein the array substrate further includes a positive power supply input Vdd line. The source of the sub-pixel cells in the same row of the second TFT and the electrode were said wire is connected to Vdd.
  3. 3.根据权利要求I所述的阵列基板,其特征在于,所述像素电极完全覆盖所述子像素单元区域。 3. The array substrate according to claim I, wherein the pixel electrode completely covers the sub-pixel unit.
  4. 4.根据权利要求I至3任一所述的阵列基板,其特征在于,所述第一 TFT的栅极与所述第二TFT的源极和漏极均形成于所述基板的表面; 所述像素电极通过过孔与所述第二TFT的漏极相连接。 I according to any one of claims array substrate of claim 3, wherein the source and the drain gate of the first TFT and the second TFT are formed on the surface of the substrate; the said pixel electrode is connected through the via hole and the drain of the second TFT.
  5. 5.根据权利要求4所述的阵列基板,其特征在于, 所述第一TFT的栅极、所述第二TFT的源极和漏极以及栅绝缘层通过一次构图工艺形成; 在形成有上述结构的所述基板表面依次形成有有源层、刻蚀阻挡层、所述第一TFT的源极和漏极与所述第二TFT的栅极、树脂层以及所述像素电极。 The array substrate according to claim 4, wherein a gate of the first TFT, the second TFT source and drain electrodes and the gate insulating layer is formed through one patterning process; forming the above-described the substrate surface structure of the active layer are sequentially formed, an etch stop layer of the first TFT and the source and the drain of the second TFT gate electrode, the resin layer and the pixel electrode.
  6. 6.根据权利要求5所述的阵列基板,其特征在于,所述第二 TFT的源极和漏极的边缘均为斜面; 所述有源层形成在所述第二TFT的源极和漏极之间,通过所述斜面与所述第二TFT的源极和漏极接触。 6. The array substrate according to claim 5, characterized in that the edge of the source and the drain of the second TFT are ramp; the active layer formed in the second TFT source and drain between electrodes, by the inclined surface of the second TFT and the source and drain contacts.
  7. 7.根据权利要求4所述的阵列基板,其特征在于,所述过孔中填充有遮光材料; 所述遮光材料的表面与所述像素电极的表面相平。 7. The array substrate according to claim 4, characterized in that the pores are filled with a light shielding material therethrough; surfaces of the light shielding material and the pixel electrode is flat.
  8. 8.根据权利要求I至3任一所述的阵列基板,其特征在于,所述第一 TFT的源极和漏极与所述第二TFT的栅极均形成于所述基板的表面; 所述像素电极通过过孔与所述第二TFT的漏极相连接。 I according to any one of claims array substrate of claim 3, wherein the source and gate of the first TFT and the drain of the second TFT are formed on the surface of the substrate; the said pixel electrode is connected through the via hole and the drain of the second TFT.
  9. 9.根据权利要求8所述的阵列基板,其特征在于, 所述第一TFT的源极和漏极、所述第二TFT的栅极以及栅绝缘层通过一次构图工艺形成; 在形成有上述结构的所述基板表面依次形成有有源层、刻蚀阻挡层、所述第一TFT的栅极与所述第二TFT的源极和漏极、树脂层以及所述像素电极。 9. The array substrate of claim 8, wherein the first TFT source and drain electrodes, the gate of the second TFT and the gate insulating layer is formed through one patterning process; forming the above-described the substrate surface structure of the active layer are sequentially formed, the etch stop layer, a gate of the first TFT and the second TFT source and drain electrodes, the resin layer and the pixel electrode.
  10. 10.根据权利要求9所述的阵列基板,其特征在于,所述第一 TFT的源极和漏极的边缘均为斜面; 所述有源层形成在所述第一TFT的源极和漏极之间,通过所述斜面与所述第一TFT的源极和漏极接触。 10. The array substrate according to claim 9, characterized in that the edge of the first TFT source and drain are inclined surfaces; a first active layer of the TFT source and drain in the between electrodes, through the inclined surface and the drain contact and the source of the first TFT.
  11. 11.根据权利要求8所述的阵列基板,其特征在于,所述过孔中填充有遮光材料; 所述遮光材料的表面与所述像素电极的表面相平。 11. The array substrate of claim 8, wherein the pores are filled with a light shielding material therethrough; surfaces of the light shielding material and the pixel electrode is flat.
  12. 12. —种OLED显示装置,包括:阵列基板、对电极以及位于所述阵列基板的像素电极与所述对电极之间的有机发光层,其特征在于,所述阵列基板为如权利要求I至10任一所述的阵列基板。 12. - The OLED display device, comprising: an array substrate, a counter electrode and a pixel electrode on the array substrate and the organic light emitting layer between the electrodes, wherein the array substrate is as claimed in claim I to according to any one of the array substrate 10.
CN 201220505507 2012-09-28 2012-09-28 Array substrate and OLED display device CN202796957U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881712A (en) * 2012-09-28 2013-01-16 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and OLED (organic light emitting diode) display device
WO2015081652A1 (en) * 2013-12-05 2015-06-11 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device
WO2017128473A1 (en) * 2016-01-27 2017-08-03 深圳市华星光电技术有限公司 Tft substrate, display device, and manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881712A (en) * 2012-09-28 2013-01-16 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and OLED (organic light emitting diode) display device
US9099404B2 (en) 2012-09-28 2015-08-04 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, OLED display device
WO2015081652A1 (en) * 2013-12-05 2015-06-11 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device
US9515028B2 (en) 2013-12-05 2016-12-06 Boe Technology Group Co., Ltd. Array substrate, method of manufacturing the same and display device
WO2017128473A1 (en) * 2016-01-27 2017-08-03 深圳市华星光电技术有限公司 Tft substrate, display device, and manufacturing method

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