CN202694451U

CN202694451U - Multi-light source high-speed banknote image capturing and processing circuit

Info

Publication number: CN202694451U
Application number: CN2012203600704U
Authority: CN
Inventors: 王朋; 赵晓研; 于雁南; 王越明
Original assignee: Heilongjiang University of Science and Technology
Current assignee: Heilongjiang University of Science and Technology
Priority date: 2012-07-24
Filing date: 2012-07-24
Publication date: 2013-01-23
Anticipated expiration: 2022-07-24

Abstract

The utility model discloses a multi-light source high-speed banknote image capturing and processing circuit. The existing banknote detector have errors in banknote detection, does not give flashlight prompts and has the problems of low image capturing and processing speed, single currency type, low resolution and the like, so that a certain difficulty in sorting a mass of banknotes is caused to the financial mechanisms. The multi-light source high-speed banknote image capturing and processing circuit comprises a shell (1), wherein the shell is internally provided with an image capturing and processing recognition system circuit board (2) which is connected with a touch type image sensor (3); a banknote inlet (5) is arranged below the touch type image sensor; the banknote inlet is connected with a banknote channel (5) which is connected with a banknote outlet (6); and the sensor is connected with a lamplight recognition light source (7). The multi-light source high-speed banknote image capturing and processing circuit is used for the high-speed recognition and counterfeit distinguishing of the face value, the face direction, the aging degree and the serial number of the banknote.

Description

Multiple light courcess high speed banknote image acquisition process circuit

Technical field:

The utility model relates to a kind of multiple light courcess high speed banknote image acquisition process circuit.

Background technology:

Existing cash inspecting machine, the problem such as the accuracy rate of bank note has error respectively, and does not have flashing light prompting, and existing cash inspecting machine exists image acquisition and processing speed low, and Currency Type is single, and resolution is low causes certain difficulty to a large amount of paper currency sortings of financial institution.

Summary of the invention:

The purpose of this utility model provides a kind of financial machine and tool that can finish high speed bill handling task, and circuit that can the acquisition and processing banknote image is finished the paper currency sorter of banknote image acquisition and processing.

Above-mentioned purpose realizes by following technical scheme:

A kind of multiple light courcess high speed banknote image acquisition process circuit, its composition comprises: housing, image acquisition and processing recognition system circuit board is housed in the described housing, described image acquisition and processing recognition system circuit board connects contact-type image sensor, described contact-type image sensor below has back-note feeder, described back-note feeder connects banknote path, and described banknote path connects the bank note outlet, and described sensor connects light identification light source.

Described multiple light courcess high speed banknote image acquisition process circuit, described image acquisition and processing recognition system circuit board comprises AD converter and contact-type image sensor driver, described AD converter connects field programmable logic array (FPLA), described field programmable logic array (FPLA) link address bus, data bus and control bus, described field programmable logic array (FPLA) access phase data exchange unit, described address bus, described data bus, described control bus connected storage and digital signal processor, described digital signal processor connects serial line interface and to host computer output data-interface, described contact-type image sensor driver connects described sensor.

Described multiple light courcess high speed banknote image acquisition process circuit, described field programmable logic array (FPLA) comprises the image capture module controller, described image capture module controller connection layout is as the pretreater data channel, image data memory and timer manager, described image pretreater data channel connects bus and port controller, described port controller connects described data bus, described image data memory connection layout is as the pretreatment parameter storer, described image pretreatment parameter storer connects described address bus, described timer manager connects the manager that resets, and the described manager that resets connects described control bus.

Described multiple light courcess high speed banknote image acquisition process circuit, described light identification light source comprises red-light source, green-light source and infrared light light source.

Beneficial effect:

1. the utility model can be finished the collection of banknote image, can identify the true and false towards, new and old, breakage and sequence number and bank note of bank note denomination.

2. the utility model throughput is high, discriminating speed is fast, and this product is comprised of the multi-optical spectrum image sensor that three light sources form, and these three light sources are respectively ruddiness, green glow and infrared light, can finish the task of image data acquiring.

3. the utility model is to circuit board, the digital block, and the power district carries out rational layout, select power low, the device of good stability requires high-frequency line round and smooth during wiring, do not have sharp-pointed chamfering, the corner does not have the right angle, and the cabling between the flaggy should be vertical as far as possible up and down.

4. the utility model is the compactness of mutually relevant device, DSP SCM﹠FPGA layout, crystal oscillator.

5. of the present utility modelly digitally separate with simulation ground, ground wire is widened; Power input is put decoupling capacitor, places decoupling capacitor at all chip power pins; Circuit board arranges the GND layer.

Description of drawings:

Accompanying drawing 1 is the structural representation of this product.

Accompanying drawing 2 is structural representations of image acquisition and processing recognition system circuit board in the accompanying drawing 1.

Accompanying drawing 3 is to adopt AD9822 as the A/D convertor circuit figure of AD conversion chip in the accompanying drawing 2.

Accompanying drawing 4 is CIS control circuit for light source figure in the accompanying drawing 1.

Accompanying drawing 5 is FPGA program loaded circuit figure in the accompanying drawing 2.

Accompanying drawing 6 is the bus interface figure of FPGA in the accompanying drawing 2.

Accompanying drawing 7 is DSP solid-state memory figure in the accompanying drawing 2.

Accompanying drawing 8 is system power supply circuit diagrams of accompanying drawing 1.

Accompanying drawing 9 is RS232 serial communication interface circuit (MAX232) figure in the accompanying drawing 2.

Accompanying drawing 10 is image acquisition and work for the treatment of process flow diagram of accompanying drawing 1.

Accompanying drawing 11 is circuit diagrams of the programmable logic array of accompanying drawing 8.

Accompanying drawing 12 is circuit diagrams of the digital signal processor of accompanying drawing 8.

Embodiment:

Embodiment 1:

A kind of multiple light courcess high speed banknote image acquisition process circuit, its composition comprises: housing 1, image acquisition and processing recognition system circuit board 2 is housed in the described housing, described image acquisition and processing recognition system circuit board connects contact-type image sensor 3, described contact-type image sensor below has back-note feeder 4, described back-note feeder connects banknote path 5, and described banknote path connects bank note outlet 6, and described sensor connects light identification light source 7.Described light identification light source comprises red-light source, green-light source and infrared light light source.

Embodiment 2:

Embodiment 1 described multiple light courcess high speed banknote image acquisition process circuit, described image acquisition and processing recognition system circuit board comprises AD converter 8 and contact-type image sensor driver 9, described AD converter connects field programmable logic array (FPLA) 10, described field programmable logic array (FPLA) link address bus 11, data bus 12 and control bus 13, described field programmable logic array (FPLA) access phase data exchange unit 14, described address bus, described data bus, described control bus connected storage 15 and digital signal processor 16, described digital signal processor connects serial line interface 17 and to host computer output data-interface 18, described contact-type image sensor driver connects described sensor.

Embodiment 3:

Embodiment 2 described multiple light courcess high speed banknote image acquisition process circuit, described field programmable logic array (FPLA) comprises image capture module controller 19, described image capture module controller connection layout is as pretreater data channel 20, image data memory 21 and timer manager 22, described image pretreater data channel connects bus and port controller 23, described port controller connects described data bus, described image data memory connection layout is as pretreatment parameter storer 24, described image pretreatment parameter storer connects described address bus, described timer manager connects the manager 25 that resets, and the described manager that resets connects described control bus.

Embodiment 4:

Embodiment 1 or 2 or 3 described multiple light courcess high speed banknote image acquisition process circuit banknote image acquisition and processing hardware circuit design targets; Acquisition and processing speed is 8/second, 10/second of peak velocities; Width of paper money is 100 ~ 180 millimeters; The bank note height is 60 ~ 90 millimeters; Bank note angle of inclination maximal value is 15 degree; Supply voltage and electric current be+5V, and electric current is less than 1.5A ,+12V, and electric current is less than 5A; The circuit board mean free error time is 4500 hours; Working temperature is 0 ~ 50 degree centigrade; Working relative humidity is 0 ~ 90%RH; The discharge of bare metal partial electrostatic is 3000V, 15pF; When mechanical vibration are inoperative, vibration frequency 10 ~ 55 ~ 10Hz, amplitude 2mm, X, Y, Z three directions each 1 hour.

The banknote image collection adopts the CIS+FPGA+DSP mode to realize.The one-piece construction of this circuit is walked the paper money direction from left to right as shown in Figure 1 among the figure.

S10 is that light emitting diode, S11 are photoelectric tube, is used for detecting banknote as the preposition sensor of subsystem and arrives.

CIS:CIS is contact-type image sensor, and by the multi-optical spectrum image sensor that three light sources form, these three light sources are respectively ruddiness, green glow and infrared light, finish the image data acquiring task.

FPGA: be field programmable logic array (FPLA), finish image data acquiring control, view data storage organization and parts of images pretreatment operation and image pre-service calculation task;

DSP: be digital signal processor, finish image processing, denomination, towards with the realization of number recognizer;

Serial and CAN bus interface;

Other auxiliary circuits comprise the parts such as management, power management that reset.

Workflow:

Because this circuit gathers reflection to red light, green glow reflection and three images of infrared external reflection to same banknote, so the sensor output signal timesharing is input in the analog to digital converter, after conversion, all be saved in the on-chip memory of FPGA.After sensor had gathered delegation's view data, FPGA sent image line interrupt request (external interrupt) to DSP, with dma mode reading images row data from FPGA, and this journey data was processed after the DSP response image interrupt request.Form the several rows image in the DSP on-chip memory after, DSP begins image is carried out pre-service.When obtaining sensor signal, FPGA also carried out the pre-service computing of part.After DSP obtains entire image, process the correlation function of realizing paper currency sorting.Then recognition result is sent to host computer by serial ports, simultaneously next banknote of preparation for acquiring and processing.

Claims

1. multiple light courcess high speed banknote image acquisition process circuit, its composition comprises: housing, it is characterized in that: image acquisition and processing recognition system circuit board is housed in the described housing, described image acquisition and processing recognition system circuit board connects contact-type image sensor, described contact-type image sensor below has back-note feeder, described back-note feeder connects banknote path, and described banknote path connects the bank note outlet, and described sensor connects light identification light source.

2. multiple light courcess high speed banknote image acquisition process circuit according to claim 1, it is characterized in that: described image acquisition and processing recognition system circuit board comprises AD converter and contact-type image sensor driver, described AD converter connects field programmable logic array (FPLA), described field programmable logic array (FPLA) link address bus, data bus and control bus, described field programmable logic array (FPLA) access phase data exchange unit, described address bus, described data bus, described control bus connected storage and digital signal processor, described digital signal processor connects serial line interface and to host computer output data-interface, described contact-type image sensor driver connects described sensor.

3. multiple light courcess high speed banknote image acquisition process circuit according to claim 2, it is characterized in that: described field programmable logic array (FPLA) comprises the image capture module controller, described image capture module controller connection layout is as the pretreater data channel, image data memory and timer manager, described image pretreater data channel connects bus and port controller, described port controller connects described data bus, described image data memory connection layout is as the pretreatment parameter storer, described image pretreatment parameter storer connects described address bus, described timer manager connects the manager that resets, and the described manager that resets connects described control bus.

4. it is characterized in that according to claim 1 and 2 or 3 described multiple light courcess high speed banknote image acquisition process circuit: described light identification light source comprises red-light source, green-light source and infrared light light source.