CN202586931U

CN202586931U - Locomotive auxiliary control unit sampling processing circuit

Info

Publication number: CN202586931U
Application number: CN 201120317271
Authority: CN
Inventors: 丛巍; 何勇军
Original assignee: CNR Dalian Locomotive Research Institute Co Ltd
Current assignee: CRRC Dalian Institute Co Ltd
Priority date: 2011-08-26
Filing date: 2011-08-26
Publication date: 2012-12-05
Anticipated expiration: 2021-08-26

Abstract

The utility model discloses a locomotive auxiliary control unit sampling processing circuit, comprising a plurality of AD sampling circuits controlled by FPGA chips (on-site programmable logic array), wherein each AD sampling circuit controlled by FPGA comprises an EMC filter circuit, a current voltage converting circuit, a high frequency filter circuit, an amplification circuit, a bias circuit, an AD converting circuit performing analog-to-digital conversion on signals processed by a simulation circuit, an isolation circuit used for reading AD circuit digital values, arranging fault thresholds and triggering corresponding fault bit FPGA chips and DSP chips (high speed data processor) for reading FPGA processed data and fault codes and performing corresponding processing on software; the characteristics are that each AD sampling circuit controlled by FPGA has a same structure. According to the utility model, FPGA controls AD sampling circuits, which makes one circuit structure adapt for different measurement object requirements and reduces design manufacture costs and later maintenance costs.

Description

Locomotive Auxiliary Control Element sampling processing circuit

Technical field

The utility model relates to locomotive Auxiliary Control Element sampling processing circuit, comprises the AD sample circuit of multirouting FPGA control, and wherein the AD sample circuit of each route FPGA control all comprises: the EMC filter circuit; Current-to-voltage converting circuit; High-frequency filter circuit; Amplifying circuit; Biasing circuit; To pass through the signal of analog circuitry processes and make analog-to-digital A/D convertor circuit; Buffer circuit; Be used to read AD circuit digital value, fault threshold is set, trigger the fpga chip of corresponding failure position; Read data and failure code that FPGA handles, and on software, do the DSP process chip of handled.

Background technology

The locomotive Auxiliary Control Element is the core of locomotive supplementary controlled system; After sensor signals such as the voltage that it can measure peripheral sensor, electric current, temperature, air quantity are handled through the AD sample circuit; Be delivered to driver control centre, make things convenient for the locomotive driving personnel in time various situation to be handled.In the prior art,, designed different circuits respectively, to adapt to different sample object different features to different sample objects.Such design demand is to different measuring object design different circuits, the object of measuring at needs more for a long time, the workload of the Preliminary design work of circuit is very big.Because the circuit board of different objects can not exchange use, need to prepare the different circuits slave board simultaneously, could guarantee the needs of maintenance circuit to different circuits design.

The utility model content

The technical problem that the utility model will solve is to measure multichannel analog signals such as voltage, electric current, temperature, air quantity to the locomotive peripheral sensor; Through optimization circuit design by FPGA control AD sample circuit; Make a kind of circuit structure adapt to different measuring, reduce design and manufacture cost and later maintenance cost the amount requirement.

For solving the problems of the technologies described above; The technical scheme that the utility model adopts is: locomotive Auxiliary Control Element sampling processing circuit; The AD sample circuit that comprises multirouting FPGA control, wherein the AD sample circuit of each route FPGA control all comprises: the EMC filter circuit; Current-to-voltage converting circuit; High-frequency filter circuit; Amplifying circuit; Biasing circuit; To pass through the signal of analog circuitry processes and make analog-to-digital A/D convertor circuit; Buffer circuit; Be used to read AD circuit digital value, fault threshold is set, trigger the fpga chip of corresponding failure position; Read data and failure code that FPGA handles, and on software, do the DSP process chip of handled, it is characterized in that: the AD sample circuit structure of each route FPGA control is identical.

As a kind of optimized technical scheme of the utility model, said analog input signal AIN0+, AIN0-get into sample circuit by port J12_2, port J12_1.Said EMC filter circuit is made up of capacitor C 369, capacitor C 370, its common ends ground connection, and the other end links to each other with port J12_2, port J12_1 respectively.Said current-to-voltage converting circuit is composed in parallel by resistance R 452, resistance R 199, resistance R a, is used for converting current signal into voltage signal.Said high-frequency filter circuit constitutes high-frequency filter circuit by capacitor C 5, capacitor C 6, capacitor C 81, capacitor C 82 with adjacent resistor.The operational amplification circuit that said amplifying circuit is made up of resistance R R14, resistance R 15, resistance R 16 and operational amplifier A 21 to 0-3.33V, is fit to AD conversion chip AD7476 work with the input voltage signal amplitude transformation.Said biasing circuit is removed wire jumper R203 through the wire jumper R202 that burn-ons, and has just increased biasing circuit, guarantees passage operational amplification circuit output forward voltage when external AC signal.Said A/D convertor circuit mainly is chip AD7476, and it can convert the aanalogvoltage of 0-3.33V into 12 bit digital quantity.Described fpga chip is XC3S1500; FPGA is that AD7476 provides gating signal ADC_No_isolated_Csn read-write clock signal ADC_No_isolated_SCLK and serial input/output bus ADC_No_isolated_SData (0); Mode through bus I2C reads 12 bit digital quantity that AD7476 is converted to, and does further processing.Described fpga chip works in main string pattern.

The utility model is through the AD sample circuit optimal design by fpga chip control, and to the different identical circuit of measuring object design, the object of measuring at needs more for a long time.Make the workload of Preliminary design work of circuit less.Simultaneously because the circuit board of different objects can exchange use; Need not carry out repeated circuit design to different requirement; Thereby realize the facilitation design of Auxiliary Control Element sampling processing circuit; Just can guarantee the needs of maintenance circuit with a small amount of circuit board spare part, reduce design and manufacture cost and later maintenance cost.

Description of drawings

Fig. 1 is a locomotive Auxiliary Control Element sampling processing schematic block circuit diagram;

The electrical schematic diagram of the locomotive Auxiliary Control Element sampling processing circuit preferred version of Fig. 2

Embodiment

Locomotive Auxiliary Control Element sampling processing circuit as shown in Figure 1 comprises the circuit that multirouting FPGA control AD samples, and wherein the AD sample circuit of each route FPGA control all comprises: the EMC filter circuit; Current-to-voltage converting circuit; High-frequency filter circuit; Amplifying circuit; Biasing circuit; To pass through the signal of analog circuitry processes and make analog-to-digital A/D convertor circuit; Buffer circuit; Be used to read AD circuit digital value, fault threshold is set, trigger the fpga chip of corresponding failure position; Read data and failure code that FPGA handles, and on software, do the DSP process chip of handled, it is characterized in that: the AD sample circuit structure of each route FPGA control is identical.

As shown in Figure 2, outside analog signal of gathering is given the AD7476 chip and is done the A/D convertor circuit processing through EMC filter circuit, current-to-voltage converting circuit, high-frequency filter circuit and amplifying circuit.FPGA is that AD7476 provides gating signal, clock signal and universal serial bus, and 12 bit digital quantity of AD7476 are read in serial.

Analog input signal gets into the AD sample circuit by port AIN0+, AIN0-port.

Wherein capacitor C 369, capacitor C 370 common ends ground connection are played the EMC filter action.

Resistance R 452, resistance R 199, resistance R a parallel connection convert current signal into voltage signal.

Capacitor C 5, capacitor C 6, capacitor C 81, capacitor C 82 constitute high-frequency filter circuit with adjacent resistor.

Resistance R R14, resistance R 15, resistance R 16 and operational amplifier constitute operational amplification circuit.It does suitable conversion with the input voltage signal amplitude, converts the voltage magnitude 0-3.33V that is fit to the AD7476 chip into.

The wire jumper R202 that burn-ons removes wire jumper R203, has just increased biasing circuit, and this can guarantee passage operational amplification circuit output forward voltage when external AC signal.

AIN0 connects A21 6 pin, is analog signal processing circuit output.

By FPGA control A/D convertor circuit, mainly be chip AD7476.It can convert the aanalogvoltage of 0-3.33V into 12 bit digital quantity.FPGA is that AD7476 provides gating signal ADC_No_isolated_Csn, read-write clock signal ADC_No_isolated_SCLK and serial input/output bus ADC_No_isolated_SData (0); Mode through bus I2C reads 12 bit digital quantity that AD7476 is converted to, and does further processing.

The fpga chip that the utility model adopts is XC3S1500, and it belongs to the SPARTAN3 of Xilinx family series.FPGA works in main string pattern, and system powers on the back from 2 EPROM chips (XCF04S) loading procedure.The FPGA serial expands to 16 bit data after reading 12 bit digital quantity that AD7476 obtains, and after every sampling is made software filtering 10 times, gives DSP with data through 32 bit data bus and does further processing.In the software of writing for FPGA, fault threshold is set.When the data of sampling surpass thresholding,, and give DSP through bus with failure code with corresponding abort situation position.DSP can directly make the protection action through the fault position.The abort situation position of FPGA belongs to hardware mode, and speed is very fast, has guaranteed the reaction speed of system to fault like this.

The FPGA software programming adopts the Verilog hardware description language.

What should explain at last is: above embodiment is only in order to the technical scheme of explanation the utility model, but not to its restriction; Although the utility model has been carried out detailed explanation with reference to previous embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of each embodiment technical scheme of essence disengaging the utility model of relevant art scheme.

Claims

1. a locomotive Auxiliary Control Element sampling processing circuit comprises the AD sample circuit that multirouting FPGA controls, and wherein the AD sample circuit of each route FPGA control all comprises: the EMC filter circuit; Current-to-voltage converting circuit; High-frequency filter circuit; Amplifying circuit; Biasing circuit; To pass through the signal of analog circuitry processes and make analog-to-digital A/D convertor circuit; Buffer circuit; Be used to read AD circuit digital value, fault threshold is set, trigger the fpga chip of corresponding failure position; Read data and failure code that FPGA handles, and on software, do the DSP process chip of handled, it is characterized in that: the AD sample circuit structure of each route FPGA control is identical.

2. a kind of locomotive Auxiliary Control Element sampling processing circuit according to claim 1, it is characterized in that: said EMC filter circuit is made up of capacitor C 369, capacitor C 370, its common ends ground connection, the other end links to each other with port J12_2, port J12_1 respectively.

3. a kind of locomotive Auxiliary Control Element sampling processing circuit according to claim 2, it is characterized in that: said current-to-voltage converting circuit is composed in parallel by resistance R 452, resistance R 199, resistance R a, is used for converting current signal into voltage signal.

4. a kind of locomotive Auxiliary Control Element sampling processing circuit according to claim 3 is characterized in that: said high-frequency filter circuit constitutes high-frequency filter circuit by capacitor C 5, capacitor C 6, capacitor C 81, capacitor C 82 with adjacent resistor.

5. a kind of locomotive Auxiliary Control Element sampling processing circuit according to claim 4; It is characterized in that: the operational amplification circuit that said amplifying circuit is made up of resistance R R14, resistance R 15, resistance R 16 and operational amplifier A 21; The input voltage signal amplitude transformation to 0-3.33V, is fit to AD conversion chip AD7476 work.

6. a kind of locomotive Auxiliary Control Element sampling processing circuit according to claim 5; It is characterized in that: said biasing circuit is through the wire jumper R202 that burn-ons; Remove wire jumper R203, increased biasing circuit, guarantee passage operational amplification circuit output forward voltage when external AC signal.

7. according to the arbitrary described a kind of locomotive Auxiliary Control Element sampling processing circuit of claim 1 to 6, it is characterized in that: said A/D convertor circuit mainly is chip AD7476, and it converts the aanalogvoltage of 0-3.33V into 12 bit digital quantity.