CN202121505U - Frequency compensation device for convertor in DC-DC current mode - Google Patents

Abstract

The utility model relates to a frequency compensation device, in particular to a frequency compensation device for a convertor in DC-DC current mode, which is characterized by comprising an error amplifier and a frequency compensation circuit in sequential connection. The frequency compensation device has the advantages that firstly, transient response of a frequency compensation system is quickened, compensation capacitances can be directly integrated into a chip, and accordingly area of the whole circuit is saved, secondly, a dynamic zero point varying along with load current can be generated to counteract a pole point w1, and thirdly, the error amplifier is in a folded common-source common-grate structure, so that high direct-current gain and high output resistance can be provided, and a low-frequency main pole point is only generated at a transport input end.

Description

A kind of frequency compensation device of DC-DC converter of current-mode

Technical field

The utility model relates to a kind of frequency compensation device, especially relates to a kind of frequency compensation device of DC-DC converter of current-mode.

Background technology

High speed development along with power electronic technology; The relation of power electronic equipment and people's work, life is close day by day; And electronic equipment all be unable to do without reliable power supply, the Switching Power Supplyization that got into the computer power supply round Realization nineties, and the power supply that takes the lead in accomplishing computer is regenerated; Age Switching Power Supply (switch-mode power converter at the beginning of getting into 21 century; SMPC) get into various electronics, electric equipment field, stored-program control exchange, communication, electron detection device power supply, control appliance power supply etc. have all used Switching Power Supply widely, have more promoted developing rapidly of switch power technology.

At present, the control mode of Switching Power Supply has monocycle control and double loop control according to the difference of circuit sampling variable.Two independently variablees are arranged, i.e. inductive current and capacitance voltage in the DC/DC converter.Only sampling capacitance voltage be output voltage be voltage mode control; Sampling and outputting voltage and inductive current is Controlled in Current Mode and Based simultaneously.In the voltage-type control mode, the variation of duty ratio D is only caused by the variation of output voltage.When load current or input voltage variation; Converter must wait earlier output voltage to change accordingly, postpone one or several switch periods then after, modulation duty cycle D; Make output voltage stabilization at last, this time-delay makes that its speed when transient response is very slow.And in voltage mode, LC output filter unit has been introduced duopole, needs in its compensation loop to add a zero point, perhaps introduces a dominant pole that frequency is lower.Current control mode has also increased a current feedback ring except the Voltage Feedback ring that keeps voltage control mode, duty ratio D is determined by the peak current of error voltage and output jointly.Current-mode has been simplified current foldback circuit, has guaranteed the reliability of converter work, has reduced cost simultaneously; And transient response is very fast, and line regulation and load regulation are all fine.Therefore, general current control mode is used wider in the DC-DC converter.

As shown in Figure 1 is the structure chart of the DC-DC converter of current control mode, and this DC-DC converter comprises power switch pipe, filter circuit unit, resistance-feedback network, current detecting unit, frequency compensation network, PWM modulator and logic control and drive circuit.Its operation principle is laid: when system does not power on, and output voltage V _OutWith inductive current I _LBe 0.When system starts working, the feedback voltage bV of output _OutWith reference voltage V _RefThe two ends of incoming frequency compensating network, because system just powers on, this moment, frequency compensation network can be regarded a comparator as, and reference voltage is much larger than feedback voltage, so the output voltage V of frequency compensation network _aRise to supply voltage; V then _aVoltage V with the current detecting network measuring _sBe input to the two ends of PWM modulator, output control signal d (t), control logic driver element open switching tube, and converter begins electric current and charges to output capacitance, V _OutAnd I _LBeing both progressively increases.Through several so all after dates, it is stable that output voltage reaches.Simultaneously, again because DC-DC converter using negative feedback control so changed and can be regulated through negative feedback by the caused output voltage of the variation of input voltage or load current, makes output stable.

In the DC-DC of current control mode converter,, thereby influenced the stability of converter because a pair of compound limit that the LC filter is produced of current regulator and voltage control loop separates into two limit ω 1 and ω 2.According to the Theory of Stability of degeneration factor, when the gain of system dropped to 0, its phase shift should be less than 180 °, otherwise system will become positive feedback, makes system oscillation.In order to make the more stable work of system, generally require its phase margin greater than 45 °, so, then must make system in unity gain bandwidth, have only a limit, so frequency compensation is absolutely necessary in order to make the work that system can be stable.

In order to solve the unsteadiness that duopole brings, general method commonly used is to adopt the dominant pole penalty method.This method is the big electric capacity of output termination at error amplifier, thereby in the transfer function of system, introduces a low frequency dominant pole:

p ₁＝1/R _aC _c

R wherein _aBe the output resistance of error amplifier, C _cBe building-out capacitor.Has only a dominant pole p like this before its unity gain bandwidth ₁, guarantee that its phase margin at the unity gain bandwidth place is 90 °.

Yet traditional dominant pole frequency compensation method has limited system's transient response.Because when output voltage changes because of input voltage or load current, then must change the output voltage V of error amplifier fast _a, make the PWM modulator provide adjusted duty ratio D and make the output voltage fast and stable.And V _aVariation be to the large compensation capacitor C of output through error amplifier _CDischarge and recharge and realize, obvious big building-out capacitor C _CDirectly reduced V _aPace of change, so the dynamic responding speed of system is very slow.In addition, big building-out capacitor can not be integrated, increased the area of entire circuit.

In dominant pole compensation, guarantee in unity gain bandwidth, to have only a limit, then must make the frequency of dominant pole very low, otherwise just possibly let limit ω ₁Get in the GBW, make system unstable.Another kind method is on the basis of dominant pole compensation, takes the method for zero pole cancellation to improve the stability of system, and its principle is at building-out capacitor C _COn add the resistance R of a series connection _c, introduce like this one zero point z ₀:

z ₀＝1/C _CR _C

The purpose of introducing this zero point is to offset limit ω ₁, let the stability of system be improved like this.

Yet further analysis can be known, the method for employing zero pole cancellation is the stability problem of resolution system well.Because load resistance R _LSize and the load current relation of being inversely proportional to, then limit ω ₁Just be directly proportional with load current.Promptly when load current becomes big, limit ω ₁Also become big; Vice versa.Like this method of zero pole cancellation can only be under a certain fixing frequency good bucking-out system.Fig. 2 has provided under the different loads current conditions, adopts the frequency response of system behind dominant pole compensation method and the fixed zero counteracting method simultaneously.

Employing dominant pole frequency compensation has only a limit though can let in the unity gain bandwidth, and its shortcoming is that bandwidth is very little, and big building-out capacitor is very slow by system's transient response speed; Adopt the method for zero pole cancellation compensation, improved the bandwidth of system to a certain extent, but its shortcoming is under a certain load current, to adopt well compensation.

The utility model content

The utility model mainly is to solve the technical problem that existing in prior technology traditional dominant pole frequency compensation method has limited system's transient response etc.; A kind of frequency compensation system transients response accelerated is provided, and building-out capacitor can be integrated into directly in the sheet, save a kind of frequency compensation device of DC-DC converter of current-mode of the area of entire circuit.

It is to solve existing in prior technology to adopt the dominant pole frequency compensation that the utility model also has a purpose, has only a limit though can let in the unity gain bandwidth, and its shortcoming is that bandwidth is very little, and big building-out capacitor is very slow by system's transient response speed; Adopt the method for zero pole cancellation compensation, improved the bandwidth of system to a certain extent, but its shortcoming is under a certain load current, to adopt the good technical problem that compensates etc.; Provide a kind of and can produce a dynamic zero point that changes along with the variation of load current, offset limit ω 1; And error amplifier adopts the structure of collapsible cascade, and a high DC current gain and big output resistance can be provided, and only produces the frequency compensation device of DC-DC converter of a kind of current-mode of a low frequency dominant pole at the output of amplifier.

The above-mentioned technical problem of the utility model mainly is able to solve through following technical proposals:

A kind of frequency compensation device of DC-DC converter of current-mode is characterized in that, comprises the error amplifier and the frequency compensated circuit that connect successively.

At the frequency compensation device of the DC-DC of above-mentioned a kind of current-mode converter, described error amplifier comprises:

One difference input circuit: comprise first difference input PMOS pipe M1, second difference input PMOS pipe M2 and current mirror PMOS pipe M11;

Grid amplifying circuit altogether: comprise first grid NMOS amplifier tube M3, second grid NMOS amplifier tube M4, the 3rd grid NMOS amplifier tube M5 and the 4th grid NMOS amplifier tube M6 altogether altogether altogether altogether;

One common source source common-gate current mirror load: comprise the first current mirror PMOS load pipe M7, the second current mirror PMOS load pipe M8, the 3rd current mirror PMOS load pipe M9 and the 4th current mirror PMOS load pipe M10.

Frequency compensation device at the DC-DC of above-mentioned a kind of current-mode converter; The drain electrode of said first difference input PMOS pipe M1 is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether; Grid is connected to feedback voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of second difference input PMOS pipe M2 is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether, and grid is connected to reference voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of the first common grid NMOS amplifier tube M3 is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to bias voltage Vb2, and source electrode is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether; The drain electrode of the second common grid NMOS amplifier tube M4 is connected to the drain electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to bias voltage Vb2, and source electrode is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether; The drain electrode of the 3rd common grid NMOS amplifier tube M5 is connected to the drain electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to ground; The drain electrode of the 4th common grid NMOS amplifier tube M6 is connected to the drain electrode of second difference input PMOS pipe M2, and grid is connected to bias voltage Vb2, and source electrode is connected to ground; The drain electrode of the first current mirror PMOS load pipe M7 is connected to the source electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the second current mirror PMOS load pipe M8 is connected to the source electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the 3rd current mirror PMOS load pipe M9 is connected to first drain electrode of grid NMOS amplifier tube M3 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the first current mirror PMOS load pipe M7; The drain electrode of the 4th current mirror PMOS load pipe M10 is connected to second drain electrode of grid NMOS amplifier tube M4 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the second current mirror PMOS load pipe M8; The drain electrode of current mirror PMOS pipe M11 is connected to the source electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to supply voltage.

At the frequency compensation device of the DC-DC of above-mentioned a kind of current-mode converter, described compensating circuit comprises:

One Miller capacitance control unit: comprise building-out capacitor C _CAnd N frequency compensation NMOS pipe is first frequency compensation NMOS pipe Mc1 ... N frequency compensation NMOS manages McN;

One dynamic zero point control unit: comprise the NMOS pipe Mm of linear zone and control potential circuit zero point.

Frequency compensation device at the DC-DC of above-mentioned a kind of current-mode converter; Said first frequency compensation NMOS pipe Mc1 ... The drain electrode of N frequency compensation NMOS pipe McN all is connected to the output of above-mentioned error amplifier; Grid is connected to bias voltage Vb, and source electrode is connected to above-mentioned building-out capacitor C _C, the drain electrode of said NMOS pipe Mm is connected to said building-out capacitor Cc, and grid is connected to the output of controlling potential circuit zero point, and source electrode connects ground.

At the frequency compensation device of the DC-DC of above-mentioned a kind of current-mode converter, control potential circuit said zero point and comprise:

The transducer of one first voltage-to-current: comprise amplifier A1, resistance R 1, NMOS pipe Mm1 and the 4th NMOS pipe Mm4;

The transducer of one second voltage-to-current: comprise amplifier A2, resistance R 3, the 5th NMOS pipe Mm5 and the 8th NMOS pipe Mm8;

One first current mirror: comprise the 2nd NMOS pipe Mm2, the 3rd NMOS pipe Mm3 and amplifier A3;

One second current mirror: comprise the 6th NMOS pipe Mm6, the 7th NMOS pipe Mm7 and amplifier A4;

One sampling resistor R2;

One control voltage VC produces circuit: comprise resistance R 4, resistance R s and the 9th NMOS pipe Mm9.

At the frequency compensation device of the DC-DC of above-mentioned a kind of current-mode converter, the positive and negative input of said amplifier A1 connects the drain electrode of M NMOS pipe Mm and the source electrode of NMOS pipe Mm1 respectively; The drain electrode of the one NMOS pipe Mm1 is connected to the 2nd NMOS pipe Mm2 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to resistance R 1; The drain electrode of the 4th NMOS pipe Mm4 is connected to the 3rd NMOS pipe Mm3 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to sampling resistor R2; The two ends of resistance R 1 are connected respectively to source electrode and the ground of NMOS pipe Mm1; The positive and negative input of said amplifier A2 connects the grid of the 9th NMOS pipe Mm9 and the source electrode of the 5th NMOS pipe Mm5 respectively; The drain electrode of the 5th NMOS pipe Mm5 is connected to the 6th NMOS pipe Mm6 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 3; The drain electrode of the 8th NMOS pipe Mm8 is connected to the 7th NMOS pipe Mm7 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 2; The two ends of resistance R 3 are connected respectively to source electrode and the ground of the 5th NMOS pipe Mm5, and the drain electrode of said the 2nd NMOS pipe Mm2 is connected to the drain electrode of NMOS pipe Mm1, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The drain electrode of the 3rd NMOS pipe Mm3 is connected to the drain electrode of the 4th NMOS pipe Mm4, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The positive and negative input of amplifier A3 connects the drain electrode of the 2nd NMOS pipe Mm2 and the drain electrode of the 3rd NMOS pipe Mm3 respectively; The drain electrode of said the 6th NMOS pipe Mm6 is connected to the drain electrode of the 5th NMOS pipe Mm5, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The drain electrode of the 7th NMOS pipe Mm7 is connected to the drain electrode of the 8th NMOS pipe Mm8, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The positive and negative input of amplifier A4 connects the drain electrode of the 6th NMOS pipe Mm6 and the drain electrode of the 7th NMOS pipe Mm7 respectively, and said resistance R 4 is connected between the drain electrode of supply voltage and the 9th NMOS pipe Mm9; Resistance R s is connected between the source electrode and ground of the 9th NMOS pipe Mm9; The 9th NMOS pipe Mm9 drain electrode is connected to resistance R 4, and grid is connected to the in-phase input end of amplifier A2, and source electrode is connected to resistance R s.

Therefore, the utlity model has following advantage: 1. accelerated frequency compensation system transients response, and building-out capacitor can be integrated into directly in the sheet, save the area of entire circuit; 2. can produce a dynamic zero point that changes along with the variation of load current, offset limit ω 1; 3. error amplifier adopts the structure of collapsible cascade, and a high DC current gain and big output resistance can be provided, and only produces a low frequency dominant pole at the output of amplifier.

Description of drawings

Fig. 1 is the structure chart of the DC-DC converter of current-mode;

Fig. 2 is the frequency response of legacy frequencies compensating network under the different loads current conditions;

Fig. 3 is the frequency compensation network structure chart of the utility model;

Fig. 4 is the circuit diagram of error amplifier;

Fig. 5 is the Miller effect under the different mode, (a) voltage mode; (b) current-mode;

Fig. 6 is the Miller capacitance control circuit structure chart of current-mode;

Fig. 7 is dynamic control unit realization at zero point circuit;

Fig. 8 is the circuit diagram of novel frequency compensation method;

Fig. 9 is the ac small signal equivalent electric circuit of current mode DC-DC converter;

Figure 10 is the signal flow graph of current mode DC-DC converter;

Figure 11 is the frequency response of novel compensating network under the different loads current conditions;

Figure 12 is Z at dynamic zero point _0dynWith limit ω ₁Change curve with load current.

Embodiment

Pass through embodiment below, and combine accompanying drawing, do further bright specifically the technical scheme of the utility model.

Embodiment:

Fig. 3 comprises error amplifier and frequency compensated circuit for the circuit of the novel frequency compensating network of the utility model raising.

Fig. 4 has provided the circuit diagram of error amplifier, and it adopts collapsible cascodes, is made up of difference input circuit, common grid amplifying circuit and current mirror load.Error amplifier comprises: a difference input circuit: comprise first difference input PMOS pipe M1, second difference input PMOS pipe M2 and current mirror PMOS pipe M11; Grid amplifying circuit altogether: comprise first grid NMOS amplifier tube M3, second grid NMOS amplifier tube M4, the 3rd grid NMOS amplifier tube M5 and the 4th grid NMOS amplifier tube M6 altogether altogether altogether altogether; One common source source common-gate current mirror load: comprise the first current mirror PMOS load pipe M7, the second current mirror PMOS load pipe M8, the 3rd current mirror PMOS load pipe M9 and the 4th current mirror PMOS load pipe M10.

The drain electrode of first difference input PMOS pipe M1 is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether, and grid is connected to feedback voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of second difference input PMOS pipe M2 is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether, and grid is connected to reference voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of the first common grid NMOS amplifier tube M3 is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to bias voltage Vb2, and source electrode is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether; The drain electrode of the second common grid NMOS amplifier tube M4 is connected to the drain electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to bias voltage Vb2, and source electrode is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether; The drain electrode of the 3rd common grid NMOS amplifier tube M5 is connected to the drain electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to ground; The drain electrode of the 4th common grid NMOS amplifier tube M6 is connected to the drain electrode of second difference input PMOS pipe M2, and grid is connected to bias voltage Vb2, and source electrode is connected to ground; The drain electrode of the first current mirror PMOS load pipe M7 is connected to the source electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the second current mirror PMOS load pipe M8 is connected to the source electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the 3rd current mirror PMOS load pipe M9 is connected to first drain electrode of grid NMOS amplifier tube M3 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the first current mirror PMOS load pipe M7; The drain electrode of the 4th current mirror PMOS load pipe M10 is connected to second drain electrode of grid NMOS amplifier tube M4 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the second current mirror PMOS load pipe M8; The drain electrode of current mirror PMOS pipe M11 is connected to the source electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to supply voltage.

Amplifier as input stage, is accomplished the conversion of voltage-to-current with PMOS differential pair M1 and M2, and the current source of being made up of M11 simultaneously is that difference is imported current offset is provided.Cathode-input amplifier is made up of M3, M4, M5 and M6, and the grid step voltage of current mirror M5 and M6 is setovered by Vb3, and the gate voltage of amplifier tube M3 and M4 is setovered by Vb2.Single-ended output circuit is the load of error amplifier; The common-source common-gate current mirror of forming by M7, M8, M9 and M10; Wherein the grid voltage of M7 and M8 is setovered by Vb4, and M9 and M10 adopt automatic biasing, can make output voltage swing improve the threshold voltage of a PMOS like this.Collapsible cascade amplifier is for the amplifier of other structures, and its topmost advantage is exactly its high-gain, and the input voltage amplitude of oscillation is relatively large, but this is to obtain with bigger power consumption, lower pole frequency and higher noise cost.

For input stage, because employing is that PMOS imports as difference, the low side of its input voltage is 0, and high-end is V _DD-(| V _OD11|+| V _THP|).For output stage, owing to adopted collapsible cascodes, so its output voltage swing is just relatively smaller, it is high-end can to arrive V _DD-| V _OD10|-| V _OD8|, low side can arrive V _OD4+ V _OD6Further analysis can get, and its output resistance and gain are:

R _a＝g _m4r _o4r _o6||g _m10r _o8r _o10

A _v＝G _m1·R _a＝G _m1·(g _m4r _o4r _o6||g _m10r _o8r _o10)

Wherein Gm1 is the mutual conductance of M1, g _M4And g _M10Be the mutual conductance of M4 and M10, r _O4, r _O6, r _O8And r _O10Be respectively the resistance of M4, M6, M8 and M10.

Comprise two parts in the frequency compensated circuit in Fig. 3: a Miller capacitance control unit: comprise building-out capacitor C _CAnd N frequency compensation NMOS pipe is first frequency compensation NMOS pipe Mc1 ... N frequency compensation NMOS manages McN; One dynamic zero point control unit: comprise the NMOS pipe Mm of linear zone and control potential circuit zero point.

First frequency compensation NMOS pipe Mc1 ... The drain electrode of N frequency compensation NMOS pipe McN all is connected to the output of above-mentioned error amplifier, and grid is connected to bias voltage Vb, and source electrode is connected to above-mentioned building-out capacitor C _CThe drain electrode of NMOS pipe Mm is connected to said building-out capacitor Cc, and grid is connected to the output of controlling potential circuit zero point, and source electrode connects ground.

Controlling potential circuit zero point comprises: the transducer of one first voltage-to-current: comprise amplifier A1, resistance R 1, NMOS pipe Mm1 and the 4th NMOS pipe Mm4; The transducer of one second voltage-to-current: comprise amplifier A2, resistance R 3, the 5th NMOS pipe Mm5 and the 8th NMOS pipe Mm8; One first current mirror: comprise the 2nd NMOS pipe Mm2, the 3rd NMOS pipe Mm3 and amplifier A3; One second current mirror: comprise the 6th NMOS pipe Mm6, the 7th NMOS pipe Mm7 and amplifier A4; One sampling resistor R2; One control voltage V _CProduce circuit: comprise resistance R 4, resistance R s and the 9th NMOS pipe Mm9.

The positive and negative input of amplifier A1 connects the drain electrode of M NMOS pipe Mm and the source electrode of NMOS pipe Mm1 respectively; The drain electrode of the one NMOS pipe Mm1 is connected to the 2nd NMOS pipe Mm2 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to resistance R 1; The drain electrode of the 4th NMOS pipe Mm4 is connected to the 3rd NMOS pipe Mm3 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to sampling resistor R2; The two ends of resistance R 1 are connected respectively to source electrode and the ground of NMOS pipe Mm1; The positive and negative input of said amplifier A2 connects the grid of the 9th NMOS pipe Mm9 and the source electrode of the 5th NMOS pipe Mm5 respectively; The drain electrode of the 5th NMOS pipe Mm5 is connected to the 6th NMOS pipe Mm6 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 3; The drain electrode of the 8th NMOS pipe Mm8 is connected to the 7th NMOS pipe Mm7 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 2; The two ends of resistance R 3 are connected respectively to source electrode and the ground of the 5th NMOS pipe Mm5.

The drain electrode of the 2nd NMOS pipe Mm2 is connected to the drain electrode of NMOS pipe Mm1, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The drain electrode of the 3rd NMOS pipe Mm3 is connected to the drain electrode of the 4th NMOS pipe Mm4, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The positive and negative input of amplifier A3 connects the drain electrode of the 2nd NMOS pipe Mm2 and the drain electrode of the 3rd NMOS pipe Mm3 respectively; The drain electrode of said the 6th NMOS pipe Mm6 is connected to the drain electrode of the 5th NMOS pipe Mm5, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The drain electrode of the 7th NMOS pipe Mm7 is connected to the drain electrode of the 8th NMOS pipe Mm8, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The positive and negative input of amplifier A4 connects the drain electrode of the 6th NMOS pipe Mm6 and the drain electrode of the 7th NMOS pipe Mm7 respectively.

Resistance R 4 is connected between the drain electrode of supply voltage and the 9th NMOS pipe Mm9; Resistance R s is connected between the source electrode and ground of the 9th NMOS pipe Mm9; The 9th NMOS pipe Mm9 drain electrode is connected to resistance R 4, and grid is connected to the in-phase input end of amplifier A2, and source electrode is connected to resistance R s.

In Miller effect,, can be divided into the Miller effect of voltage mode and current-mode according to the method that the connects difference of electric capacity.Fig. 5 has provided the circuit structure diagram under two kinds of different modes respectively.

In the Miller effect of voltage mode, between the input and output of Miller capacitance cross-over connection and amplifier, the equivalent capacity C that then obtains at the input of amplifier _INEqual:

C _IN＝(1+A)C _F

In like manner too for current-mode.Shown in Fig. 3-8 (b), establish and flow through capacitor C _CElectric capacity be I _C, and another branch current parallelly connected with electric capacity is K _XI _C, then looking down from node A, equivalent current of being seen and electric capacity are:

I _eq＝k _xI _C+I _C

C _eq＝(1+k _x)C _C

In the Miller capacitance control unit of the utility model design, if adopt voltage mode, then need an amplifier again, make the structure of compensating circuit seem complicated like this, and be difficult to debugging; The inverse current pattern, it is simple in structure, is easy to design.So in paper, adopt the Miller capacitance control unit of current-mode, Fig. 6 has provided its circuit structure diagram.

In Fig. 6, the Miller control unit is made up of this N of Mc1～McN NMOS, and their drain electrode and source voltage all equate, select suitable bias voltage Vb to let them all be operated in the saturation region, and the breadth length ratio of Mc2-McN pipe and Mc1 is k: 1.In the Miller capacitance control unit, establish the voltage V between node A and the B _AB, the electric current that flows through first frequency compensation pipe Mc1 is I ₁, if there is not the Mc2-McN frequency compensation pipe of back, ignore the Mc1 conducting resistance, the building-out capacitor of then being seen toward ground from the A node is:

$C_{\mathrm{eq}}^{\′}=\frac{I_{\mathrm{ceq}}^{\′}}{{\mathrm{sV}}_{\mathrm{AB}}}=\frac{I_{c1}}{{\mathrm{sV}}_{\mathrm{AB}}}=C_m$

This is the same with traditional frequency compensation network.But after adding up Mc2-McN frequency compensation pipe, the equivalent capacity of then seeing from node A place this moment is:

$C_{\mathrm{eq}}=\frac{I_{\mathrm{ceq}}}{{\mathrm{sV}}_{\mathrm{AB}}}=\frac{I_{c1}+(N-1){\mathrm{<figure-callout\; id="1"\; label="kI\; c"\; filenames="HDA0000064193110000041.png,HDA0000064193110000051.png"\; state="\{\{state\}\}">kI</figure-callout>}}_c}{{\mathrm{sV}}_{\mathrm{AB}}}=[1+(N-1)k]C_m$

If according to traditional frequency compensation, the building-out capacitor that adds 0.1 μ F at the output of error amplifier is to obtain a low frequency dominant pole, and so big obviously electric capacity can not be integrated in the PWM controller, and accounts for very much the area of entire circuit plate.Yet if adopt the Miller capacitance control unit, when the breadth length ratio k of Mc2-McN and Mc1 gets 10, the frequency compensation pipe number N of back was got 10 o'clock, just can reach the compensation effect the same with traditional frequency compensation with the building-out capacitor of 1nf.Adopt novel Miller capacitance control unit to save very big chip area obviously, because building-out capacitor is very little, it is very of short duration that it discharges and recharges the time simultaneously, i.e. system's transient response speed is very fast.

In metal-oxide-semiconductor, different according to the voltage of the drain-gate source electrode of metal-oxide-semiconductor, can be divided into saturation region, linear zone and cut-off region.Wherein when MOS was operated in linear zone, its characteristic was equivalent to a voltage-controlled resistance, and this moment flows through the electric current of MOS and the resistance of the drain-source utmost point is:

$I_D=\frac{1}{2}{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}[2(V_{\mathrm{GS}}-V_{\mathrm{THN}})V_{\mathrm{DS}}-V_{\mathrm{DS}}^2]$

$R_{\mathrm{DS}}={\left(\frac{{\&PartialD;I}_D}{\&PartialD;V_{\mathrm{DS}}}\right)}^{-1}={\left[{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{GS}}-V_{\mathrm{THN}}-V_{\mathrm{DS}})\right]}^{-1}$

μ wherein _nBe the average mobility of NMOS pipe, C _OxBe the gate capacitance of unit are, W is the width of NMOS pipe, and L is the length of NMOS pipe, V _GSBe the gate source voltage of NMOS pipe, V _DSBe the drain source voltage of NMOS, V _THNThreshold voltage for NMOS.

Though being operated in the metal-oxide-semiconductor equivalence of linear zone is a voltage-controlled resistance, its linearity is bad, because its size and voltage V _GSAnd V _DSRelation is all arranged.In order to let the MOS of linear zone satisfy the Linear Control relation, then must let the gate source voltage of MOS satisfy:

V _GS＝V _C+V _DS/2

V wherein _CBe control voltage.Then flow through the electric current of MOS and the resistance of the drain-source utmost point can be expressed as this moment:

$I_D={\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}\left[(V_C-V_{\mathrm{THN}})V_{\mathrm{DS}}\right]$

$R_{\mathrm{DS}}={\left(\frac{{\&PartialD;I}_D}{\&PartialD;V_{\mathrm{DS}}}\right)}^{-1}={\left[{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_C-V_{\mathrm{THN}})\right]}^{-1}$

At this moment, the metal-oxide-semiconductor of linear zone has just become one and has received voltage V _CThe linear resistance of control, its concrete circuit is realized as shown in Figure 7.In Fig. 7, be operated in linear zone, essential satisfied relation in order to guarantee NMOS pipe Mm:

V _GS-V _THN＞V _DS

Then have:

V _C＝V _GS-V _DS/2≥V _THN+V _DS-V _DS/2＝V _THN+V _DS/2

Can know that by above analysis behind the frequency compensation method that adopts Miller capacitance control unit and control unit at dynamic zero point, dynamically the expression formula at zero point is:

${\mathrm{<figure-callout\; id="0"\; label="z"\; filenames="HDA0000064193110000051.png,HDA0000064193110000061.png"\; state="\{\{state\}\}">z</figure-callout>}}_{0\mathrm{dyn}}=\frac{1}{C_{\mathrm{eq}}{R}_V}=\frac{\left[{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_C-V_{\mathrm{THN}})\right]}{[1+(N-1)k]C_m}$

Be used to offset limit ω this dynamic zero point ₁So, must satisfy the following relationship formula:

$(I_O+{\mathrm{\&Delta;i}}_L)/C_O{V}_O=\frac{\left[{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}(V_C-V_{\mathrm{THN}})\right]}{[1+(N-1)k]C_m}$

Control voltage V is then arranged _CWith the relation of load current be:

$V_C=V_{\mathrm{THB}}+\left[\frac{[1+(N-1)k]C_{m}L}{C_O{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}W}\right]\frac{(I_O+\mathrm{\&Delta;}{i}_L)}{V_O}$

Fig. 8 is the circuit diagram of the novel frequency compensation method that this paper designed, and comprises the circuit of the circuit of Miller capacitance control unit and control unit at dynamic zero point among the figure.The introduction that the front is detailed the design of Miller capacitance control unit, introduce the design and the operation principle of control unit at dynamic zero point below.

Dynamically zero point, control unit circuit comprised the transducer of the metal-oxide-semiconductor Mm of linear zone, two voltage-to-currents, two current mirrors, sampling resistor R2 and control voltage V _CThe generation circuit constitutes.Wherein amplifier A1, resistance R 1 and M1 constitute first voltage-current converter, and amplifier A2, resistance R 3 and M5 constitute second voltage-current converter, and the size of current after its conversion is:

I ₁＝V _DS/R ₁，I ₂＝V _C/R ₃

Mm2 and Mm3, Mm6 and Mm7 constitute current mirror, in order to guarantee electric current I ₁And I ₂Accurate mirror image, in current mirror, added two amplifiers, wherein two of A3 inputs are connected on the drain electrode of Mm2 and Mm3 respectively, output is connected on their grid, A4 to connect method similar.The drain-gate source voltage of Mm2 and Mm3, Mm6 and Mm7 all equates like this, and electric current is mirror image accurately just.Behind the two-way current mirror, the electric current that flows through resistance R 2 is:

I _sum＝I ₁+I ₂＝V _DS/R ₁+V _C/R ₃

In dynamic zero point of this paper design control unit circuit, the breadth length ratio of M2 and M3, M6 and M7 all is identical, and the resistance of resistance R 1, R2 and R3 is respectively 2R, R and R.Then have:

V _GS＝I _sumR ₂＝R ₂(V _DS/R ₁+V _C/R ₃)＝V _DS/2+V _C

Resistance R _S, R4 and metal-oxide-semiconductor Mm9 constitute control voltage generation circuit, R among the figure _SAnd I _SBe used for detecting the size of inductive current.Can know that by figure control voltage and be this moment:

V _C＝V _THN+I _SR _S

The expression formula at like this, last dynamic zero point is:

${\mathrm{<figure-callout\; id="0"\; label="z"\; filenames="HDA0000064193110000051.png,HDA0000064193110000061.png"\; state="\{\{state\}\}">z</figure-callout>}}_{0\mathrm{dyn}}=\frac{1}{C_{\mathrm{eq}}{R}_V}=\frac{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}{I}_S{R}_S}{[1+(N-1)k]C_m}$

The novel frequency compensating network that proposes for further explanation the utility model is to the improvement of the stability of a system, below the transfer function of analytical system.Fig. 9 and Figure 10 are respectively the ac small signal equivalent electric circuit and the signal flow graph of current mode DC-DC converter, and then the transfer function of the DC-DC converter of current-mode is:

$T\left(s\right)=\frac{b{G}_c\left(s\right)G_{\mathrm{vd}}\left(s\right)}{V_m}=A\left(s\right)\frac{1+s/{\mathrm{<figure-callout\; id="0"\; label="z"\; filenames="HDA0000064193110000051.png,HDA0000064193110000061.png"\; state="\{\{state\}\}">z</figure-callout>}}_{0\mathrm{<figure-callout\; id="1"\; label="dyn"\; filenames="HDA0000064193110000041.png,HDA0000064193110000051.png"\; state="\{\{state\}\}">dyn</figure-callout>}}}{1+s/{\mathrm{\&omega;}}_0}\frac{b}{V_m}\frac{R_L\left|\right|R_{\mathrm{on}}}{{\mathrm{<figure-callout\; id="1"\; label="R\; f"\; filenames="HDA0000064193110000041.png,HDA0000064193110000051.png"\; state="\{\{state\}\}">R</figure-callout>}}_f}\frac{1+s/z_1}{(1+s/{\mathrm{\&omega;}}_1)(1+s/{\mathrm{\&omega;}}_2)}$

$=\frac{G_{m1}{R}_a[1+s\frac{[1+(N-1)k]C_m}{{\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}\frac{W}{L}{I}_S{R}_S}]}{1+s{R}_a[1+(N-1)k]C_c}\&CenterDot;\frac{b}{V_m}\&CenterDot;\frac{R_L\left|\right|R_{\mathrm{on}}}{R_f}\&CenterDot;\frac{1+s/{\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="HDA0000064193110000041.png,HDA0000064193110000051.png"\; state="\{\{state\}\}">z</figure-callout>}}_1}{1+s(\frac{1}{{\mathrm{\&omega;}}_1}+\frac{R_L\left|\right|R_{\mathrm{on}}}{R_f}\&CenterDot;\frac{1}{{\mathrm{\&omega;}}_2})+{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA0000064193110000032.png"\; state="\{\{state\}\}">s</figure-callout>}}^2\frac{1}{{\mathrm{\&omega;}}_1{\mathrm{\&omega;}}_w}}$

Wherein A (s) is the transfer function of frequency compensation network, and b is the feedback factor of resistance-feedback network, R _LBe load resistance, R _fBe the detection resistance of current detecting unit, 1/V _mBe the gain of PWM modulator, R _OnBe the equivalent resistance of storage inductance, Gm1 is the mutual conductance of error amplifier, R _aBe the output resistance of error amplifier, and

$b=\frac{R_{f2}}{{\mathrm{<figure-callout\; id="1"\; label="R\; f"\; filenames="HDA0000064193110000041.png,HDA0000064193110000051.png"\; state="\{\{state\}\}">R</figure-callout>}}_f+R_{f2}}$ $R_{\mathrm{on}}=\frac{L}{(n_1{D}^{\&prime;}-D)T}$

By the transfer function of system, can know easily that zero limit is:

Dominant pole ω ₀=1/ [1+ (N-1) k] C _CR _a

The first non-dominant pole ω ₁≈ 1/R _LC _O≈ (I _O+ Δ i _L)/C _OV _O

The second non-dominant pole ω ₂≈ 1/n ₁D ' T

Zero point z ₁=1/R _EsrC _O

Dynamic zero point $z_{}$ ${}_{0\mathrm{Dyn}}=\frac{1}{C_{\mathrm{Eq}}{R}_V}=\frac{{\mathrm{\&mu;}}_n{C}_{\mathrm{Ox}}\frac{W}{L}{I}_S{R}_S}{[1+(N-1)k]C_m}$

Dynamically zero point z _0dynOffset limit ω ₁And zero point z ₁With limit ω ₂All outside unity gain bandwidth, whole system has just become a single-stage dot system like this.This moment, the unity gain bandwidth of system was:

$\mathrm{GBW}=G_{m1}{R}_a\frac{b}{V_m}\frac{R_L\left|\right|R_{\mathrm{on}}}{R_f}\&CenterDot;{\mathrm{\&omega;}}_0$

In order to further specify the improvement of novel frequency compensation method to the stability of the DC-DC converter of current-mode, the utility model has carried out emulation to the open-loop frequency response of system under the different loads current conditions, and Figure 11 is the result of emulation.Can know the dominant pole ω of system by Figure 11 ₀Be 15Hz.When load current is 10mA, limit ω ₁With z at zero point ₀All be about about 1.4KHz; When load current is 200mA, limit ω ₁Be approximately 30KHz, zero point z ₀Be about 25KHz; When load current is 400mA, limit ω ₁Be approximately 57KHz, zero point z ₀Be about 53KHz.System has only a dominant pole ω in unity gain bandwidth like this ₀So its phase place desire degree is about 90 °.Therefore, the new type of frequency compensation method can both guarantee the work of system stability in full-load range.

In addition, Figure 12 gives by dynamic zero point, control unit produced z at dynamic zero point _0dynWith the curve of the variation of load current, simultaneously for z at dynamic zero point is described _0dynOffset limit ω ₁Situation, in Figure 12, also provided limit ω ₁Curve with the variation of load current.Can know by Figure 12, under different load current condition, dynamically can both offset limit ω zero point ₁

Specific embodiment described herein only is that the utility model spirit is illustrated.The utility model person of ordinary skill in the field can make various modifications or replenishes or adopt similar mode to substitute described specific embodiment, but can't depart from the spirit of the utility model or surmount the defined scope of appended claims.

Claims (7)

1. the frequency compensation device of the DC-DC converter of a current-mode is characterized in that, comprises the error amplifier and the frequency compensated circuit that connect successively.

2. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 1 is characterized in that, described error amplifier comprises:

One difference input circuit: comprise first difference input PMOS pipe M1, second difference input PMOS pipe M2 and current mirror PMOS pipe M11;

Grid amplifying circuit altogether: comprise first grid NMOS amplifier tube M3, second grid NMOS amplifier tube M4, the 3rd grid NMOS amplifier tube M5 and the 4th grid NMOS amplifier tube M6 altogether altogether altogether altogether;

One common source source common-gate current mirror load: comprise the first current mirror PMOS load pipe M7, the second current mirror PMOS load pipe M8, the 3rd current mirror PMOS load pipe M9 and the 4th current mirror PMOS load pipe M10.

3. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 2; It is characterized in that; The drain electrode of said first difference input PMOS pipe M1 is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether; Grid is connected to feedback voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of second difference input PMOS pipe M2 is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether, and grid is connected to reference voltage, and source electrode is connected to the drain electrode of current mirror PMOS pipe M11; The drain electrode of the first common grid NMOS amplifier tube M3 is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to bias voltage Vb2, and source electrode is connected to the 3rd drain electrode of grid NMOS amplifier tube M5 altogether; The drain electrode of the second common grid NMOS amplifier tube M4 is connected to the drain electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to bias voltage Vb2, and source electrode is connected to the 4th drain electrode of grid NMOS amplifier tube M6 altogether; The drain electrode of the 3rd common grid NMOS amplifier tube M5 is connected to the drain electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to ground; The drain electrode of the 4th common grid NMOS amplifier tube M6 is connected to the drain electrode of second difference input PMOS pipe M2, and grid is connected to bias voltage Vb2, and source electrode is connected to ground; The drain electrode of the first current mirror PMOS load pipe M7 is connected to the source electrode of the 3rd current mirror PMOS load pipe M9, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the second current mirror PMOS load pipe M8 is connected to the source electrode of the 4th current mirror PMOS load pipe M10, and grid is connected to the drain electrode of the 3rd current mirror PMOS load pipe M9, and source electrode is connected to supply voltage; The drain electrode of the 3rd current mirror PMOS load pipe M9 is connected to first drain electrode of grid NMOS amplifier tube M3 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the first current mirror PMOS load pipe M7; The drain electrode of the 4th current mirror PMOS load pipe M10 is connected to second drain electrode of grid NMOS amplifier tube M4 altogether, and grid is connected to bias voltage Vb4, and source electrode is connected to the drain electrode of the second current mirror PMOS load pipe M8; The drain electrode of current mirror PMOS pipe M11 is connected to the source electrode of first difference input PMOS pipe M1, and grid is connected to bias voltage Vb1, and source electrode is connected to supply voltage.

4. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 1 is characterized in that, described compensating circuit comprises:

One Miller capacitance control unit: comprise that building-out capacitor CC and N frequency compensation NMOS pipe is first frequency compensation NMOS pipe Mc1 ... N frequency compensation NMOS manages McN;

One dynamic zero point control unit: comprise the NMOS pipe Mm of linear zone and control potential circuit zero point.

5. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 4; It is characterized in that said first frequency compensation NMOS pipe Mc1 ... The drain electrode of N frequency compensation NMOS pipe McN all is connected to the output of above-mentioned error amplifier, and grid is connected to bias voltage Vb; Source electrode is connected to above-mentioned building-out capacitor CC; The drain electrode of NMOS pipe Mm is connected to said building-out capacitor Cc, and grid is connected to the output of controlling potential circuit zero point, and source electrode connects ground.

6. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 4 is characterized in that, controls potential circuit said zero point and comprises:

The transducer of one first voltage-to-current: comprise amplifier A1, resistance R 1, NMOS pipe Mm1 and the 4th NMOS pipe Mm4;

The transducer of one second voltage-to-current: comprise amplifier A2, resistance R 3, the 5th NMOS pipe Mm5 and the 8th NMOS pipe Mm8;

One first current mirror: comprise the 2nd NMOS pipe Mm2, the 3rd NMOS pipe Mm3 and amplifier A3;

One second current mirror: comprise the 6th NMOS pipe Mm6, the 7th NMOS pipe Mm7 and amplifier A4;

One sampling resistor R2;

One control voltage VC produces circuit: comprise resistance R 4, resistance R s and the 9th NMOS pipe Mm9.

7. the frequency compensation device of the DC-DC converter of a kind of current-mode according to claim 6 is characterized in that, the positive and negative input of said amplifier A1 connects the drain electrode of M NMOS pipe Mm and the source electrode of NMOS pipe Mm1 respectively; The drain electrode of the one NMOS pipe Mm1 is connected to the 2nd NMOS pipe Mm2 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to resistance R 1; The drain electrode of the 4th NMOS pipe Mm4 is connected to the 3rd NMOS pipe Mm3 drain electrode, and grid is connected to the output of amplifier A1, and source electrode is connected to sampling resistor R2; The two ends of resistance R 1 are connected respectively to source electrode and the ground of NMOS pipe Mm1; The positive and negative input of said amplifier A2 connects the grid of the 9th NMOS pipe Mm9 and the source electrode of the 5th NMOS pipe Mm5 respectively; The drain electrode of the 5th NMOS pipe Mm5 is connected to the 6th NMOS pipe Mm6 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 3; The drain electrode of the 8th NMOS pipe Mm8 is connected to the 7th NMOS pipe Mm7 drain electrode, and grid is connected to the output of amplifier A2, and source electrode is connected to resistance R 2; The two ends of resistance R 3 are connected respectively to source electrode and the ground of the 5th NMOS pipe Mm5, and the drain electrode of said the 2nd NMOS pipe Mm2 is connected to the drain electrode of NMOS pipe Mm1, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The drain electrode of the 3rd NMOS pipe Mm3 is connected to the drain electrode of the 4th NMOS pipe Mm4, and grid is connected to the output of amplifier A3, and source electrode is received on the supply voltage; The positive and negative input of amplifier A3 connects the drain electrode of the 2nd NMOS pipe Mm2 and the drain electrode of the 3rd NMOS pipe Mm3 respectively; The drain electrode of said the 6th NMOS pipe Mm6 is connected to the drain electrode of the 5th NMOS pipe Mm5, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The drain electrode of the 7th NMOS pipe Mm7 is connected to the drain electrode of the 8th NMOS pipe Mm8, and grid is connected to the output of amplifier A4, and source electrode is received on the supply voltage; The positive and negative input of amplifier A4 connects the drain electrode of the 6th NMOS pipe Mm6 and the drain electrode of the 7th NMOS pipe Mm7 respectively, and said resistance R 4 is connected between the drain electrode of supply voltage and the 9th NMOS pipe Mm9; Resistance R s is connected between the source electrode and ground of the 9th NMOS pipe Mm9; The 9th NMOS pipe Mm9 drain electrode is connected to resistance R 4, and grid is connected to the in-phase input end of amplifier A2, and source electrode is connected to resistance R s.

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