CN202013886U

CN202013886U - Single-grid double-film transistor and device applying same

Info

Publication number: CN202013886U
Application number: CN2011201043148U
Authority: CN
Inventors: 张航; 任庆荣; 张玉军; 郭炜; 王路
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2011-04-11
Filing date: 2011-04-11
Publication date: 2011-10-19
Anticipated expiration: 2021-04-11

Abstract

The utility model relates to the manufacturing field of a semiconductor and a photoelectric display device and provides a single-grid double-film transistor and a device applying same. As two film transistors in parallel connection are taken as a switching element, the stability is better; and compared with the prior art, a higher switch state current ratio can be acquired, larger gray-scale voltage is easier to achieve. With the adoption of the method, the single-grid double-film transistor solves the problems of smaller switch state current ratio caused by a single-film transistor used in the liquid crystal display industry at the moment and uneven display caused by the drifting of threshold voltage and the like.

Description

A kind of single grid double thin-film transistors and device thereof

Technical field

The utility model relates to semiconductor and photoelectric display device is made field, particularly a kind of single grid double thin-film transistors and device thereof.

Background technology

The present widespread of amorphous silicon hydride a-Si:H thin-film transistor in the manufacture process of LCD, as liquid crystal display pixel switch driven device, advantage such as it has easy preparation, and homogeneity is good, and cost is lower.Because the little electric current and the controllable characteristics thereof of a-Si:H thin-film transistor, make it in some field not high, have great application value for electric current and rate request; For example in large tracts of land shows, need many transistors to control luminous tube array, the a-Si:H thin-film transistor just can play a role well.

But also there are some obvious defects simultaneously in the a-Si:H thin-film transistor, wherein sixty-four dollar question is exactly the metastable characteristic of threshold voltage, such as increase along with service time, after the long period applies gate bias, its threshold voltage and subthreshold efficient all will be drifted about, deterioration can take place in the performance of a-Si:H thin-film transistor, causes the electrical properties instability of TFT.Because threshold voltage shift must cause the drift of drive current, and because OLED is a kind of luminescent device of current drives, the drift of drive current makes the a-Si:H thin-film transistor very poor to the driveability of OLED, the situation of display abnormality very easily occurs.In addition, uneven if threshold voltage drifts about in face, also may cause the problem of liquid crystal display inequality.

How to improve the performance of thin-film transistor, particularly improve the character of its performance degradation, become the key issue that current LCD is made.Occurred some technology at present, wherein the most effective is exactly LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon) technology, and concrete grammar is to utilize polysilicon to form active layer, stable threshold voltage effectively.But the LTPS technical costs is higher, and become the homogeneity of film also unsatisfactory, the device OFF leakage current is easy to more greatly puncture, low temperature large-area preparation difficulty is higher simultaneously, complex process, these have all restricted the LTPS The Application of Technology.With regard to present state of development, the LTPS technology is still waiting further improvement, uses still not extensive.

Generally speaking, amorphous silicon has advantages such as with low cost and large tracts of land manufacturing, therefore can be used to make the picture element matrix that plays the addressing effect in demonstration or the image device, and making and addressing matrix be produced on the display driver circuit of glass substrate simultaneously, remains in the current actual production and use maximum thin-film transistor technologies.But its carrier mobility is low and poor stability, therefore is subjected to certain restriction in the occasion that requires high device density.

The utility model content

(1) technical problem that will solve

At the shortcoming of prior art, the utility model designs the character of improving thin-film transistor in order to solve the performance issue of existing a-Si:H film by improving thin-film transistor structure, can obtain better performances, lower-cost product.

(2) technical scheme

Solve the problems of the technologies described above, the utility model specifically adopts following scheme to carry out for this reason:

At first, the utility model provides a kind of single grid double thin-film transistors, and described transistor comprises:

Two thin-film transistors, described two thin-film transistors are vertical distribution spatially, a shared grid, described two thin-film transistors lay respectively at the above and below of described grid.

Preferably, described single grid double thin-film transistors is made of successively substrate 1, first active layer 2, first ohmic contact layer 4, first grid insulating barrier 3, grid layer 5, second grid insulating barrier 6, second active layer 7, second ohmic contact layer 8, source-drain electrode layer 9, protective layer 10.

Preferably, described source-drain electrode layer 9 forms with first ohmic contact layer 4 and contacts, and described first active layer 2, described first ohmic contact layer 4, described first grid insulating barrier 3, described grid layer 5 and described source-drain electrode layer 9 constitute the first film transistor; Described grid layer 5, described second grid insulating barrier 6, described second active layer 7, described second ohmic contact layer 8 and described source-drain electrode layer 9 constitute second thin-film transistor.

Preferably, described first active layer 2 and described second active layer 7 adopt amorphous silicon, polysilicon, crystalline silicon, microcrystal silicon, oxide semiconductor material and/or organic semiconducting materials to constitute intrinsic, the n type mixes or p type doped semiconductor.

Preferably, at least a formation in described first grid insulating barrier 3, described second grid insulating barrier 6 and described protective layer 10 employing inorganic insulating materials and/or the organic insulating material.

Preferably, at least a formation in described grid layer 5 and described source-drain electrode layer 9 employing metal, polysilicon or the conductive film.

Preferably, described first ohmic contact layer 4 and described second ohmic contact layer 8 adopt amorphous silicon, polysilicon, crystalline silicon, microcrystal silicon, oxide semiconductor material and/or organic semiconducting materials to constitute doping of n type or p type doped semiconductor.

Preferably, described substrate 1 is made of glass, plastics, silicon chip or pottery.

Further, the utility model also provides a kind of display panels that adopts above-mentioned single grid double thin-film transistors to make, and described display panels adopts described single grid double thin-film transistors as the liquid crystal cell supporter.

(3) beneficial effect

The utility model adopts two thin-film transistors in parallel as switching device, by two thin-film transistors making in vertical direction, have better stability, can obtain the switch attitude current ratio higher, more help realizing bigger gray scale voltage than prior art.

Description of drawings

Fig. 1 is the structural representation of single grid double thin-film transistors provided by the utility model;

Fig. 2 is the equivalent circuit diagram of single grid double thin-film transistors provided by the utility model;

Fig. 3 is that thin-film transistor provided by the utility model is as liquid crystal cell supporter schematic diagram.

Embodiment

Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is a part of embodiment of the present utility model, rather than whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skills are obtained under the prerequisite of not making creative work belongs to the scope that the utility model is protected.

At first; referring to Fig. 1; single grid double thin-film transistors in the utility model is successively superposeed and is constituted by substrate 1, first active layer 2, first ohmic contact layer 4, first grid insulating barrier 3, grid layer 5, second grid insulating barrier 6, second active layer 7, second ohmic contact layer 8, source-drain electrode layer 9, protective layer 10 successively.Wherein, by etching source-drain electrode layer 9 is formed with first ohmic contact layer 4 and contact, first active layer 2, first ohmic contact layer 4, first grid insulating barrier 3, grid layer 5 and 9 equivalence of source-drain electrode layer constitute the first film transistor, and main body is positioned at grid layer 5 belows; Grid layer 5, second grid insulating barrier 6, second active layer 7, second ohmic contact layer 8 and 9 equivalence of source-drain electrode layer constitute second thin-film transistor, and main body is positioned at grid layer 5 tops.The shared grid layer 5 of above-mentioned two thin-film transistors, in source-drain electrode layer 9 source electrode of the two equivalence be parallel form and the two drain electrode also equivalence be parallel form.

Described substrate 1 material is any of glass, plastics, silicon chip and pottery.

The material that described first active layer 2 and second active layer 7 adopt is any in amorphous silicon, polysilicon, microcrystal silicon, oxide semiconductor material and the organic semiconducting materials, constitutes intrinsic semiconductor, n type doped semiconductor or p type doped semiconductor thus.

Described first grid insulating barrier 3, described second grid insulating barrier 6 and described protective layer 10 material therefors are organic insulating material and/or inorganic insulating material (as nitride, oxide, nitrogen oxide etc.); can also can be two or more combination for wherein a kind of.

Described grid layer 5 and described source-drain electrode layer 9 material therefor are the one or more combination in metal, polysilicon or the conductive film.

Described first ohmic contact layer 4 and described second ohmic contact layer, 8 material therefors semi-conducting material for mixing, a kind of in amorphous silicon, polysilicon, microcrystal silicon, oxide semiconductor material, the organic semiconducting materials, doping can be that the n type mixes also can be that the p type mixes.

Fig. 2 is the equivalent circuit diagram of the single grid double thin-film transistors in the utility model, wherein 12 is grids, the 13rd, source electrode, the 14th, drain electrode, as can be seen, in equivalent circuit diagram, the source of two thin-film transistors in single grid double thin-film transistors of the present utility model, drain electrode parallel connection, a shared grid, described two thin-film transistors are arranged at the top and bottom of described grid respectively.

Particularly, each structure sheaf of the single grid double thin-film transistors in the utility model can take following step successively to prepare according to the structure sheaf order:

1. select suitable substrate substrate for use, substrate is cleaned;

2. prepare first active layer 2 and the figure thereof at substrate surface;

3. deposit one deck gate insulating film and form first grid insulating barrier 3;

4. the preparation gate electrode forms grid layer 5 on dielectric film, and forms gate patterns;

5. deposit gate insulating film (forming second grid insulating barrier 6), second active layer 7 successively;

6. form second active layer, 7 figures;

7. etch the contact hole that arrives ground floor active layer 2;

8. the ohmic contact layer of dopant deposition and source-drain electrode metal (form source-drain electrode layer 9) and form figure successively, wherein, form second ohmic contact layer 8 in other zones, 7. the described contact hole place that etches in step forms first ohmic contact layer 4, and source-drain electrode layer 9 metal contact with first ohmic contact layer 4 at described contact hole place;

9. deposit protective layer 10 and prepare drain contact hole 11;

10. prepare pixel electrode and form figure.

Further, also adopt above-mentioned single grid double thin-film transistors to make display panels in the utility model, as shown in Figure 3, described display panels adopts above-mentioned single grid double thin-film transistors 16 as the liquid crystal cell supporter, and it is thick to form stable box between substrate 1 and CF substrate 15.The display panels that this mode is made has reduced the sprinkling operation of liquid crystal cell supporter and can obtain stable box thick, thereby cost is lower, performance is better.

Above execution mode only is used to illustrate the utility model; and be not to restriction of the present utility model; the those of ordinary skill in relevant technologies field; under the situation that does not break away from spirit and scope of the present utility model; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and real protection scope of the present utility model should be defined by the claims.

Claims

1. single grid double thin-film transistors is characterized in that described transistor comprises:

2. single grid double thin-film transistors according to claim 1; it is characterized in that described single grid double thin-film transistors is made of successively substrate (1), first active layer (2), first ohmic contact layer (4), first grid insulating barrier (3), grid layer (5), second grid insulating barrier (6), second active layer (7), second ohmic contact layer (8), source-drain electrode layer (9), protective layer (10).

3. single grid double thin-film transistors according to claim 2, it is characterized in that, described source-drain electrode layer (9) forms with first ohmic contact layer (4) and contacts, and described first active layer (2), described first ohmic contact layer (4), described first grid insulating barrier (3), described grid layer (5) and described source-drain electrode layer (9) constitute the first film transistor; Described grid layer (5), described second grid insulating barrier (6), described second active layer (7), described second ohmic contact layer (8) and described source-drain electrode layer (9) constitute second thin-film transistor.

4. single grid double thin-film transistors according to claim 2, it is characterized in that described first active layer (2) and described second active layer (7) adopt amorphous silicon, polysilicon, crystalline silicon, microcrystal silicon, oxide semiconductor material and/or organic semiconducting materials to constitute intrinsic, the n type mixes or p type doped semiconductor.

5. single grid double thin-film transistors according to claim 2; it is characterized in that described first grid insulating barrier (3), described second grid insulating barrier (6) and described protective layer (10) adopt at least a formation in inorganic insulating material and/or the organic insulating material.

6. single grid double thin-film transistors according to claim 2 is characterized in that, described grid layer (5) and described source-drain electrode layer (9) adopt at least a formation in metal, polysilicon or the conductive film.

7. single grid double thin-film transistors according to claim 2, it is characterized in that described first ohmic contact layer (4) and described second ohmic contact layer (8) adopt amorphous silicon, polysilicon, crystalline silicon, microcrystal silicon, oxide semiconductor material and/or organic semiconducting materials to constitute the n type and mix or p type doped semiconductor.

8. single grid double thin-film transistors according to claim 2 is characterized in that described substrate (1) is made of glass, plastics, silicon chip or pottery.

9. adopt the display panels of making as the arbitrary described single grid double thin-film transistors of claim 1-8, it is characterized in that described display panels adopts described single grid double thin-film transistors as the liquid crystal cell supporter.