CN201955353U - Semiconductor chip test socket - Google Patents

Abstract

The utility model relates to a semiconductor chip test socket, comprising a socket main body (4), a probe retaining plate (5) and loop probes (2 and 3), wherein two parallel holes are arranged between the socket main body (4) and the probe retaining plate (5); and a voltage loop probe (2) and a current loop probe (3) are respectively arranged into the two parallel holes. The two loop probes are simultaneously contacted with a semiconductor chip contact point (1), and the other ends of the two loop probes are respectively contacted with a test main board (6). In the semiconductor chip test, since the semiconductor chip test socket adopts one chip contact point (1) to be contacted with the two probes (2 and 3) simultaneously, the test main board is connected into different loops so as to separate the current to be tested and the voltage to be tested, and the current loop probe (3) is connected into a high-resistance loop. The resistance of one probe can be ignored to be zero; the other path of the probes is used for a test loop for voltage transmission, and the voltage drop on the voltage loop probe is also basically zero, therefore, the test accuracy of a semiconductor chip is greatly improved, and the influence of the test probes on the chip test can be basically ignored.

Description

A kind of semiconductor die testing socket

Technical field

The utility model belongs to semicon industry, particularly Kelvin's test jack of semiconductor die testing.

Background technology

Along with the raising day by day of semiconductor integrated circuit chip travelling speed, chip testing industry requirement chip testing anchor clamps have the integrated performance of better high-frequency signal.In the actual test of semi-conductor chip, test fixture necessarily requires the resistance of test probe itself the smaller the better.Before the utility model was made, the semiconductor die testing socket mainly was made up of three parts: i.e. probe holding plate, chip carrier socket main body and test probe.This test jack, a chip contact only contacts with a test probe, because the physical property the subject of knowledge and the object of knowledge decision of test probe own, outwardness resistance between test chip and mainboard, has directly influenced the accuracy of measured value.

The utility model content

The purpose of this utility model is to provide a kind of and can effectively reduces the resistance of test probe own, thereby guarantees test semiconductor die testing socket as far as possible accurately.

The purpose of this utility model is to realize by following technical measures: the utility model be on the prior art basis, carry out improved.The utility model still comprise socket main body and with the close-connected probe holding plate in socket main body bottom.Different is, the middle part has the hole that can insert probe, and be two independences that run through socket main body and probe holding plate separately, parallel hole so that the current return probe is inserted in a hole; The voltage circuit probe is inserted in a hole.The upper end of two loop probes should be an inclined-plane, and corresponding.The top of two loop probes can be pushed up simultaneously toward chip contact; And the bottom of loop probe, engaged test mainboard respectively.

Because the utility model has adopted a chip contact to use the Kelvin method of testing of two probes simultaneously, two probes pass through testing host, insert in the different loops, these two probes are used for voltage and current to be measured is separated, the probe that wherein is used for current delivery inserts the high resistance loop, the resistance of probe is for external high resistance like this, and it is zero that its resistance can be ignored; And another road is used for the test loop of voltage transmission, voltage drop on test probe also equals zero substantially, so just reached the purpose of this utility model, entire chip test process precision is greatly improved, test probe can be ignored substantially to the influence of chip testing.

Description of drawings

Accompanying drawing 1 is a structural representation of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with drawings and Examples.In conjunction with the accompanying drawings 1, embodiment has comprised socket main body 4 and probe holding plate 5, has two parallel holes with one heart, and its profile is not done requirement.In 4 two holes of socket main body, insert voltage circuit probe 2 and current return probe 3 respectively, then in the bottom of socket main body 4, voltage circuit probe 2 and current return probe 3 are inserted in probe holding plate 5, and socket main body 4 is connected with screw with 5 of probe holding plates.Two probes keep certain spacing, and the upper end is an inclined-plane, is symmetry shape, contact with chip testing point 1 simultaneously, and the other end then offsets with testing host 6 respectively.

Claims (2)

1. semiconductor die testing socket, comprise socket main body (4), and bottom and the close-connected probe holding plate of socket main body (4) (5), it is characterized in that: in the centre of socket main body (4) and probe holding plate (5), have two parallel holes, be respectively charged into voltage circuit probe (2) and current return probe (3), two loop probes (2,3) are contact chip test point (1) simultaneously, and the other end then contacts with testing host (6) respectively.

2. a kind of semiconductor die testing socket according to claim 1 is characterized in that: the upper end of voltage circuit probe (2) and current return probe (3) is an inclined-plane, and corresponding.