CN201909812U - Novel phase difference detection circuit - Google Patents
Novel phase difference detection circuit Download PDFInfo
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- CN201909812U CN201909812U CN2010206302869U CN201020630286U CN201909812U CN 201909812 U CN201909812 U CN 201909812U CN 2010206302869 U CN2010206302869 U CN 2010206302869U CN 201020630286 U CN201020630286 U CN 201020630286U CN 201909812 U CN201909812 U CN 201909812U
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Abstract
The utility model relates to a phase difference detection circuit in the field of the signal detection, and in particular relates to a phase difference detection circuit for detecting the size of the phase difference of two signals and the advance or retardation relationship. The phase difference detection circuit aims at solving the problem that the method for detecting the size of the phase difference of the two signals and the advance or retardation relationship of the phase is complex in the prior art. The novel phase difference detection circuit is used for accurately detecting the size of the phase difference of two input singles and the advance or retardation relationship, so that the detection circuit is simple and reliable. The phase difference detection circuit has the technical scheme that the detection circuit comprises a phase detecting module 1, a phase detecting module 2, a phase-shift circuit, an analog-to-digital (A/D) conversion circuit 1, an A/D conversion circuit 2 and a field programmable gate array (FPGA) processor. The phase difference detection circuit is mainly used for detecting the phase error of two sine wave signals or square wave signals and the occasion of the advance or retardation relationship.
Description
Technical field
The utility model relates to a kind of phase difference detecting circuit in input field, particularly relates to a kind of phase difference detecting circuit that detects two paths of signals phase differential size and leading or lagged relationship.
Background technology
In the input field, often need to detect two phase difference between signals, phase differential comprises the leading or lagged relationship of phase place extent and phase place.General phase-detecting chip (as AD8302 etc.) can be measured two paths of signals phase place extent, its scope is 0 °～180 °, or actually but not the phase differential of energy measurement two paths of signals 0 °～+ 180 ° 0 °～-180 ° scope, so can't judge the leading or lagged relationship of two paths of signals phase place.
" China's test " delivered the article that is entitled as " based on two longitudinal mode double frequency laser interferometer signal disposal systems of AD8302 " in May, 2009, in the literary composition to utilizing the AD8302 chip that the detection of two paths of signals phase differential is described, it adopted will be wherein 90 ° of one tunnel signal delays, and then carry out the detection of phase differential, thereby identify the leading or lagged relationship of two paths of signals phase place with other one road signal.The shortcoming of this method is must be with 90 ° of the accurate phase shifts of signal, and this makes circuit design become complicated, and easily produces erroneous judgement when the phase shift angle is inaccurate.In addition, the article of " utilizing the shake of phase place to overcome the two-value of AD8302 " has been delivered and be entitled as to " Chinese new technology new product " the 2nd phase in 2009, it adds continuous square-wave pulse to one road signal wherein and carries out phase modulation (PM), utilize the shake of phase place to discern the leading or lagged relationship of two paths of signals phase place, the shortcoming of this method is to need to add complicated phase-modulation circuit.
The utility model content
The purpose of this utility model is to solve in the prior art detected phase difference size and phase place is leading or lagged relationship method challenge too, a kind of novel phase difference detecting circuit is provided, accurately detect two-way phase of input signals difference size and lead lag relationship, testing circuit is simple, reliable.
For achieving the above object, the technical solution adopted in the utility model is:
A kind of novel phase difference detecting circuit, comprise phase-detecting detection module 1, phase-shift circuit, phase-detecting detection module 2, signal processing module, signal processing module comprises A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2, FPGA processor, wherein phase-shift circuit, phase-detecting detection module 2, A/D analog to digital conversion circuit 1, FPGA processor are electrically connected in proper order, and phase-detecting detection module 1, A/D analog to digital conversion circuit 2, FPGA processor are electrically connected in proper order.
Described phase-detecting detection module comprises phase-detecting chip AD8302 and peripheral circuit, input signal A is connected with first phase-detecting chip AD8302 second pin, input signal B is connected with first phase-detecting chip AD8302 the 6th pin, and first phase-detecting chip AD8302 the 9th pin, first phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 1 input end as output terminal jointly; Input signal A is connected with second phase-detecting chip AD8302 second pin by phase-shift circuit, input signal B is connected with second phase-detecting chip AD8302 the 6th pin, and second phase-detecting chip AD8302 the 9th pin, second phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 2 input ends as output terminal jointly; A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2 output terminals are connected with the FPGA processor respectively.
Described novel phase difference detecting circuit utilizes the A/D analog to digital conversion circuit by increasing by one tunnel phase-detecting detection module and phase-shift circuit, judges the leading or lagged relationship of two paths of signals phase place through FPGA processor adopting corresponding detecting method.
Described FPGA processor is also replaced by band analog-to-digital microprocessor of A/D or dsp processor.
From above-mentioned architectural feature of the present utility model as can be seen, its advantage is: detect two-way phase of input signals difference and lead lag relationship effectively, testing circuit is simple, reliable.
Description of drawings
The utility model will illustrate by way of compared with accompanying drawings and combined with example:
Fig. 1 is a schematic block circuit diagram of the present utility model.
Fig. 2 is a circuit design drawing of the present utility model.
Fig. 3 is the process flow diagram of the leading or lagged relationship of judgement two paths of signals phase place of the present utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Mentality of designing: as shown in Figure 1, phase-detecting detection module 1 can directly detect two-way input signal A and B phase place extent, its scope is 0 °～180 °, by phase-detecting detection module 2 and phase-shift circuit that increases an identical function, the A/D module is converted to digital signal with two phase-detecting detection module output signal voltage values and sends into FPGA (or having microprocessor of A/D translation function etc.), and FPGA judges two paths of signals phase difference value and lead lag relationship by specific algorithm.
Overall design: novel phase difference detecting circuit, comprise phase-detecting detection module 1, phase-shift circuit, phase-detecting detection module 2, signal processing module, signal processing module comprises A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2, FPGA processor, wherein phase-shift circuit, phase-detecting detection module 2, A/D analog to digital conversion circuit 1, FPGA processor are electrically connected in proper order, and phase-detecting detection module 1, A/D analog to digital conversion circuit 2, FPGA processor are electrically connected in proper order.The phase-detecting detection module comprises phase-detecting chip AD8302 and peripheral circuit, input signal A is connected with first phase-detecting chip AD8302 second pin, input signal B is connected with first phase-detecting chip AD8302 the 6th pin, and first phase-detecting chip AD8302 the 9th pin, first phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 1 input end as output terminal jointly; Input signal A is connected with second phase-detecting chip AD8302 second pin by phase-shift circuit, input signal B is connected with second phase-detecting chip AD8302 the 6th pin, and second phase-detecting chip AD8302 the 9th pin, second phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 2 input ends as output terminal jointly; A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2 output terminals are connected with the FPGA processor respectively, and wherein phase-detecting chip and A/D analog to digital conversion circuit are poor with digital form precise quantification phase of input signals.
Fig. 2 is the phase difference detecting circuit design drawing, and R1 and R2 are build-out resistors, is generally 50 Ω; C1～C4, C6～C9 are the electric capacity of 1nF; C5 and C10 are the electric capacity of 22pF.
Resistance R and capacitor C are formed the simplest sinusoidal wave phase-shift circuit, and it is typical low-pass first order filter.Low-pass first order filter has phase shift function to input signal, regulates the parameter of R and C, can make phase of input signals generation phase shift, and the phase shift size changes in 0 °～90 ° scopes.Also can change sinusoidal wave phase-shift circuit into the square wave phase-shift circuit, the square wave of input is handled.
Two phase-detecting chip AD8302 directly detect two-way phase of input signals difference size, mode with aanalogvoltage is exported, corresponding phase range is 0 °～180 °, after phase-detecting chip AD8302 output is carried out the A/D analog to digital conversion through the A/D module, utilize FPGA processor (or having little processing of A/D analog-digital conversion function or dsp processor etc.) to judge the lead lag relationship of input signal A and input signal B phase place, export in the mode of high-low level then by specific algorithm.For example, as the leading input signal B of phase place of output high level interval scale input signal A, as the phase lag input signal B of output low level interval scale signal A.Specific design is crossed and is called:
Phase place is that the input signal A of α (180＜α≤180) and input signal B that phase place is β (180＜β≤180) import phase-detecting detection module 1 respectively, phase-detecting detection module 1 detects input signal A and input signal B phase place extent, form output with aanalogvoltage is converted to the corresponding digital quantity of angle γ value through A/D analog to digital conversion circuit 1 with magnitude of voltage; Input signal A inserts the phase-shift circuit with phase shift function simultaneously again, the angle of setting phase shift is θ (0＜θ≤90), through after the phase-shift circuit, the phase place of input signal A is α+θ, and then import phase-detecting detection module 2 with input signal B, phase-detecting detection module 2 detected phase differential sizes with the output of the form of aanalogvoltage, are converted into angle through A/D analog to digital conversion circuit 2 with magnitude of voltage
The digital quantity that value is corresponding; With angle γ and angle
Corresponding digital quantity input FPGA processor, be converted to corresponding γ and
By the FPGA processor according to θ, γ and
Analyze, when γ ≠ 0, judge the magnitude relationship of α and β, also, judge the relation that input signal A and input signal B phase place are leading or lag behind.The phase-detecting chip can be the chip of AD8302 or identical phase-detecting function.
Fig. 3 is the algorithm flow chart of the leading or lagged relationship of judgement two paths of signals phase place of the present utility model.The phase differential size of input signal A and input signal B is γ, promptly has: | alpha-beta |=γ.When the different phase times of input signal A, two kinds of situations are arranged with input signal B:
First kind of situation, if the phase place of the leading input signal B of phase place of input signal A, i.e. alpha-beta＜0 o'clock has:
When γ＜θ, have
When θ≤γ＜180-θ, have
When 180-θ≤γ≤180, have
Second kind of situation, if the phase place of the phase lag input signal B of input signal A, i.e. alpha-beta＞0 o'clock has:
When γ＜θ, have
When θ≤γ＜180-θ, have
When 180-θ≤γ≤180,, have because of γ+θ 〉=180
By as can be seen to the analysis of above two kinds of situations, when γ＜θ, θ≤γ＜180-θ or 180-θ≤γ≤180, lead lag relationship is a separation with θ, γ and 180-θ respectively, so the algorithm with lagged relationship before judge input signal A and the input signal B ultrasonic is arranged: if γ＜θ and
Or θ≤γ＜180-θ and
Or γ 〉=180-θ and
The phase place of the leading input signal B of the phase place of input signal A then; If γ＜θ and
Or θ≤γ＜180-θ and
Or γ 〉=180-θ and
The phase place of the phase lag input signal B of input signal A then.
Disclosed all features in this instructions except mutually exclusive feature, all can make up by any way.
Disclosed arbitrary feature in this instructions (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
Claims (3)
1. novel phase difference detecting circuit, comprise phase-detecting detection module 1, it is characterized in that also comprising phase-shift circuit, phase-detecting detection module 2, signal processing module, signal processing module comprises A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2, FPGA processor, wherein phase-shift circuit, phase-detecting detection module 2, A/D analog to digital conversion circuit 1, FPGA processor are electrically connected in proper order, and phase-detecting detection module 1, A/D analog to digital conversion circuit 2, FPGA processor are electrically connected in proper order.
2. a kind of novel phase difference detecting circuit according to claim 1, it is characterized in that described phase-detecting detection module comprises phase-detecting chip AD8302 and peripheral circuit, input signal A is connected with first phase-detecting chip AD8302 second pin, input signal B is connected with first phase-detecting chip AD8302 the 6th pin, and first phase-detecting chip AD8302 the 9th pin, first phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 1 input end as output terminal jointly; Input signal A is connected with second phase-detecting chip AD8302 second pin by phase-shift circuit, input signal B is connected with second phase-detecting chip AD8302 the 6th pin, and second phase-detecting chip AD8302 the 9th pin, second phase-detecting chip AD8302 the tenth pin are connected with A/D analog to digital conversion circuit 2 input ends as output terminal jointly; A/D analog to digital conversion circuit 1, A/D analog to digital conversion circuit 2 output terminals are connected with the FPGA processor respectively.
3. a kind of novel phase difference detecting circuit according to claim 1 is characterized in that described FPGA processor is also replaced by band analog-to-digital microprocessor of A/D or dsp processor.
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| CN2010206302869U CN201909812U (en) | 2010-11-26 | 2010-11-26 | Novel phase difference detection circuit |
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| CN2010206302869U CN201909812U (en) | 2010-11-26 | 2010-11-26 | Novel phase difference detection circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102298089A (en) * | 2010-11-26 | 2011-12-28 | 中国工程物理研究院流体物理研究所 | Novel phase difference detection circuit and method thereof |
| CN102589413A (en) * | 2012-02-17 | 2012-07-18 | 清华大学 | Multi-axis displacement signal processing method for double-frequency laser interferometer |
| CN102645585A (en) * | 2012-05-14 | 2012-08-22 | 中国航空工业集团公司北京长城计量测试技术研究所 | Synchronous rapid measuring method and device for ultralow frequency sinusoidal signal phase difference |
| CN104034963A (en) * | 2013-03-07 | 2014-09-10 | 鸿富锦精密工业(武汉)有限公司 | Alternating-current phase detection system |
| CN104049147A (en) * | 2014-05-27 | 2014-09-17 | 国家电网公司 | Circuit for testing admittance and phase angle of secondary circuit through pilot frequency admittance method |
| CN114264877A (en) * | 2021-12-27 | 2022-04-01 | 中国电子科技集团公司第三十四研究所 | Sine wave phase difference accurate measurement circuit and measurement method thereof |
-
2010
- 2010-11-26 CN CN2010206302869U patent/CN201909812U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102298089A (en) * | 2010-11-26 | 2011-12-28 | 中国工程物理研究院流体物理研究所 | Novel phase difference detection circuit and method thereof |
| CN102589413A (en) * | 2012-02-17 | 2012-07-18 | 清华大学 | Multi-axis displacement signal processing method for double-frequency laser interferometer |
| CN102589413B (en) * | 2012-02-17 | 2014-06-18 | 清华大学 | Multi-axis displacement signal processing method for double-frequency laser interferometer |
| CN102645585A (en) * | 2012-05-14 | 2012-08-22 | 中国航空工业集团公司北京长城计量测试技术研究所 | Synchronous rapid measuring method and device for ultralow frequency sinusoidal signal phase difference |
| CN104034963A (en) * | 2013-03-07 | 2014-09-10 | 鸿富锦精密工业(武汉)有限公司 | Alternating-current phase detection system |
| CN104049147A (en) * | 2014-05-27 | 2014-09-17 | 国家电网公司 | Circuit for testing admittance and phase angle of secondary circuit through pilot frequency admittance method |
| CN104049147B (en) * | 2014-05-27 | 2017-02-15 | 国家电网公司 | Circuit for testing admittance and phase angle of secondary circuit through pilot frequency admittance method |
| CN114264877A (en) * | 2021-12-27 | 2022-04-01 | 中国电子科技集团公司第三十四研究所 | Sine wave phase difference accurate measurement circuit and measurement method thereof |
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Granted publication date: 20110727 |
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