CN201813391U - Signaling-voice acquisition gateway - Google Patents
Signaling-voice acquisition gateway Download PDFInfo
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- CN201813391U CN201813391U CN2009202706165U CN200920270616U CN201813391U CN 201813391 U CN201813391 U CN 201813391U CN 2009202706165 U CN2009202706165 U CN 2009202706165U CN 200920270616 U CN200920270616 U CN 200920270616U CN 201813391 U CN201813391 U CN 201813391U
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- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
The utility model relates to a signaling-voice acquisition gateway which mainly comprises a shell, a signaling-voice acquisition board arranged inside the shell, an embedded processor and a double-path optical interface board, wherein a voice and signaling data processing passage of the signaling-voice acquisition board comprises a time slot interchange chip, a clock synchronization chip, an FPGA (Field Programmable Gate Array) and a DSP (digital signal processor); and a data processing passage of the double-path optical interface board comprises a time slot interchange chip, an FPGA, a transceiver and an SFP module. A single signaling-voice acquisition gateway can provide four pairs of 155M optical fiber access at most; the signaling-voice acquisition gateway can acquire 1024 64K full-load signaling channels or 32 one-way high-speed 2Mbps signaling links simultaneously, supports the mixed acquisition of 64K signaling links and high-speed 2M signaling links, can rank all channel data according to receiving time and send out the channel data through an Ethernet port, and also can support the voice acquisition and superposition of 2048 channels, the superposed use of multiple equipment, and the connection of a plurality of client sides simultaneously; and the embedded processor is connected with a serial port of a computer by a serial port for system configuration and debugging.
Description
Technical field
But the utility model extensive use is at the legal monitoring system of operation maintenance management system, increment service system or the department of mandate of signaling network.Specifically can be used for No. 7 signaling network monitoring, value-added service, traffic monitoring, mobile transmission network optimization, STM-1 is provided interface based on monitoring signaling.
Background technology
Along with the continuous development of the communication technology, communication network is complicated day by day.Signaling is the nerve of communication network, supports and controlling the normal operation of communication network.Signaling System Number 7 is present domestic topmost interoffice signaling, has all obtained extensive employing on fixed network, mobile network.No.7 signalling system is maximum common channel signal technology that adopts in the digital communication network, along with popularizing of Signaling System Number 7, the traffic carrying capacity of Signaling System Number 7 constantly increases, and is particularly online at mobile signaling protocol, and original 64kbps signaling link can not adapt to the demand that traffic carrying capacity increases fully; At present, our company existing embedded type multichannel signal collecting equipment can overcome the above problems, and is very obvious but current signal transmission form has expanded to the advantage of utilizing optical fiber, signal to transmit in optical fiber, and the fiber optic network coverage rate is more and more wider, should make full use of.
Summary of the invention
Little in order to overcome existing signaling acquisition system capacity, autgmentability is poor, the low deficiency that waits of transmission rate, and the purpose of this utility model provides a kind of signaling voice collecting gateway, and this equipment adopts modularized design, and separate unit provides maximum 4 pairs of 155M optical fiber to insert; Equipment is gathered 1024 64K full load signalling paths or 32 unidirectional high speed 2Mbps signaling links simultaneously; Support the mixing collection of 64K signaling link and high speed 2M signaling link; Can sort by the time that receives to all channel datas, and Message Signal Unit is sent by Ethernet interface; Simultaneously, this equipment is also supported voice collecting, the stack of 2048 passages, and sends by Ethernet interface; Support that multiple devices pile up use, to obtain bigger capacity; Can support a plurality of clients to connect simultaneously; Adopt high-speed dsp processor, high performance embedded type CPU.
To achieve these goals, the utility model by the following technical solutions: a kind of signaling voice collecting gateway, it mainly is made of housing and the signaling voice collecting plate, flush bonding processor and the two-way Optical Fiber Interface Board that are built in the housing; Signaling voice collecting plate is fixed in the housing, and flush bonding processor links to each other with signaling voice collecting plate by connector, is in signaling voice collecting plate top, and the two-way Optical Fiber Interface Board links to each other with signaling voice collecting plate by the connector of side;
The voice of described signaling voice collecting plate and signaling data are handled path and are made of Time Slot Switching Circuit, clock synchronizer, on-site programmable gate array FPGA, Digital Signal Processing DSP circuit; The data processing path of two-way Optical Fiber Interface Board is made of Time Slot Switching Circuit, on-site programmable gate array FPGA, transceiver, SFP module; Time Slot Switching Circuit mainly is made of the time gas exchange chip;
The address bus of Time Slot Switching Circuit, FPGA, DSP, flush bonding processor, data/address bus, control bus link to each other; Time gas exchange chip output code flow in the Time Slot Switching Circuit has both direction, and one the tunnel is connected with the time gas exchange chip of two-way Optical Fiber Interface Board, and another road links to each other with the serial code stream input of FPGA; The EDMA synchronous signal output end of FPGA links to each other with the parallel data input EMIFA of DSP; The I/O end EMIFB of DSP links to each other with the I/O end that extends out SDRAM; The output code flow MCBSP mouth of DSP links to each other with FPGA; The PCI/HPI multiplexing port of DSP links to each other with the PCI mouth of flush bonding processor; Signaling voice collecting plate is provided with two gigabit network interfaces and a serial ports; Signaling voice collecting plate links to each other with computer gigabit network interface by the gigabit networking interface circuit; The debug signal of flush bonding processor links to each other with the serial ports of computers interface circuit by the serial ports of signaling voice collecting plate.
Time gas exchange chip one road code stream of two-way Optical Fiber Interface Board links to each other with the time gas exchange chip of signaling voice collecting plate, and another road links to each other with the FPGA of two-way Optical Fiber Interface Board; Another road serial code stream of FPGA links to each other with transceiver; Transceiver has the two-way serial code stream to link to each other with two SFP modules respectively.
This equipment also is provided with SONET/SDH system clock synchronizer, mainly is to produce the system synchronization clock to give time gas exchange chip, FPGA, DSP, transceiver; In addition, also has a phase-locked loop, for transceiver provides reference clock.
Described housing is made up of upper and lower two parts, and upper and lower casing by screw together; Power module and signaling voice collecting plate are fixed on the lower house, and two gigabit network interfaces, serial ports, power supply indicator, system's run indicator and 8 road light mouth run indicator are arranged on the lower house front panel; On the lower house rear board 4 two-way Optical Fiber Interface Board sockets, power interface and mains switches.
Characteristics of the present utility model are: big capacity, single device can provide 4 couples of STM-1 to insert, and gather the Signaling System Number 7 on the STM-1 circuit in real time, and the voice channel on the STM-1 circuit is recorded.
Description of drawings
Fig. 1 forms schematic block diagram for the utility model circuit board
Fig. 2 is the theory diagram of the utility model signaling voice collecting plate control circuit
Fig. 3 is the theory diagram of the utility model two-way Optical Fiber Interface Board control circuit
Fig. 4 is the concrete connection layout of each pin of time gas exchange chip on the signaling voice collecting plate
Fig. 5 is the concrete connection layout of A each pin of part of FPGA on the signaling voice collecting plate
Fig. 6 is the concrete connection layout of B, C each pin of part of FPGA on the signaling voice collecting plate
Fig. 7 is each pin connection layout of A part of DSP
Fig. 8 is each pin connection layout of B part of DSP
Fig. 9 is C, D, the concrete connection layout of each pin of F three parts of DSP
Figure 10 is the concrete connection layout of E each pin of part of DSP
Figure 11 is the concrete connection layout of each pin of time gas exchange chip of two-way Optical Fiber Interface Board
Figure 12 is the concrete connection layout of each pin of FPGA on the two-way Optical Fiber Interface Board
Figure 13 is the concrete connection layout of A, B each pin of part of transceiver on the two-way Optical Fiber Interface Board
Figure 14 is C, D, the concrete connection layout of E each pin of part of transceiver on the two-way Optical Fiber Interface Board
Figure 15 is the concrete connection layout of SFP module on the two-way Optical Fiber Interface Board
Embodiment
As shown in Figure 1, the utility model signaling voice collecting gateway mainly is made of signaling voice collecting plate, flush bonding processor and two-way Optical Fiber Interface Board; On lower house, flush bonding processor places the top of signaling voice collecting plate by connector to signaling voice collecting plate by screw, and the two-way Optical Fiber Interface Board is inserted on the signaling voice collecting plate by connector.
As shown in Figure 2, signaling voice collecting plate control circuit of the present utility model comprises Time Slot Switching Circuit (mainly being made of the time gas exchange chip), FPGA module, digital signal processing circuit (mainly being made of two DSP), clock synchronizer, flush bonding processor.
The 16M serial code stream I/O port of time gas exchange chip links to each other with the serial code stream I/O port of 4 two-way Optical Fiber Interface Boards; Another group 16M serial code stream I/O port of time gas exchange chip links to each other with the serial code stream I/O port of FPGA; 64 parallel-by-bit data of FPGA conversion link to each other with the EMIFA parallel data input of DSP; The EMIFB parallel data I/O end of DSP links to each other with the I/O end that extends out SDRAM; The code stream input of DSP links to each other with the time gas exchange chip, and output links to each other with FPGA; The PCI/HPI multiplexing port of DSP links to each other with the PCI mouth of flush bonding processor; The gigabit of flush bonding processor and serial interface circuit link to each other with the computer interface circuit.
As shown in Figure 3, two-way Optical Fiber Interface Board control circuit of the present utility model comprises Time Slot Switching Circuit (mainly being made of the time gas exchange chip), FPGA module, transceiver, phase-locked loop, 2 SFP modules.
16 road 16M serial code stream I/O ports of time gas exchange chip link to each other with the serial code stream I/O port of FPGA; 11 road 32M serial code stream I/O ports of FPGA link to each other with the serial code stream I/O port of receiver; The clock signal output terminal of phase-locked loop links to each other with the reference clock signal input of receiver; Two groups of serial code stream I/O ports of receiver link to each other with the serial code stream I/O port of SFP module respectively.
As shown in Figure 4,8 circuit-switched data line input/output terminals of time gas exchange chip link to each other with the data wire input/output terminal of U45A shown in Figure 5; 16 circuit-switched data line input/output terminals of time gas exchange chip link to each other with the data wire input/output terminal of U2A shown in Figure 11; 14 tunnel address wire input/output terminals of time gas exchange chip (pin 31～23,20～16) link to each other with the address wire input/output terminal (pin 31～16) of U2A shown in Figure 11; 6 tunnel address wire input/output terminals of time gas exchange chip (pin 31～29,14～16) link to each other with the address wire input/output terminal (pin 202,197,196,179,175,174) of U45A shown in Figure 5; The serial code stream input of time gas exchange chip links to each other with the output of U45A shown in Figure 5; The serial code stream output of time gas exchange chip links to each other with the input of U45A shown in Figure 5, also links to each other with the serial code stream input of the time gas exchange chip U2A of 4 two-way Optical Fiber Interface Boards shown in Figure 11 simultaneously; 4 groups of serial code stream inputs of time gas exchange chip link to each other with the serial code stream output of the time gas exchange chip U2A of 4 two-way Optical Fiber Interface Boards shown in Figure 11 respectively.
As Fig. 5, shown in Figure 6, the serial code stream input port of FPGA links to each other with the delivery outlet of time gas exchange chip, is converted into parallel data after receiving serial code stream.The parallel data delivery outlet of FPGA links to each other with the parallel data input port of U1A shown in Figure 7 (DSP).
As shown in Figure 8, the address wire of DSP (pin A14, C14, D14, A15, B15, C15, D15, A16, B16, C16, D16, A17, B17, C17, D17) links to each other with the address wire that extends out SDRAM (pin 23～26,29～34,22,35,36,20,21), and the data wire of DSP (pin B10, D10, A9, C10, B9, D9, B8, C9, A7, C8, B7, D8, A6, C7, B6, D7) links to each other with the data wire that extends out SDRAM ( pin 2,4,5,7,8,10,11,13,42,44,45,47,48,50,51,53).
As shown in Figure 9, DSP links to each other with flush bonding processor by the PCI mouth, and the data processed that will sort is sent to flush bonding processor.
As shown in figure 10, the synchronizing signal input port of DSP links to each other with the synchronizing signal delivery outlet of FPGA, receives that starting parallel data after the synchronizing signal receives.
As shown in figure 11, the serial code stream input of time gas exchange chip links to each other with the delivery outlet of FPGA among Figure 12; The serial code stream output of time gas exchange chip links to each other with the input of U3 among Fig. 4; The data wire of time gas exchange chip links to each other with the data wire of transceiver among the data wire of FPGA, Figure 13; Among the address wire of time gas exchange chip (pin 16～20,23～31) and Figure 12 among the address wire ( pin 24,29,52,48,47) of FPGA, Figure 13 the address wire (pin U27～U25, V30～V26, W30～W27, Y30, Y29, AA30, AA29) of transceiver link to each other.
Shown in Figure 12,11 road serial data stream inputs of FPGA link to each other with the serial data output of U10E shown in Figure 14; The 8 circuit-switched data lines of FPGA link to each other with the data wire of U10A shown in Figure 13.
Shown in Figure 13, the serial data input of transceiver links to each other with the serial data output of U7A shown in Figure 15, U8A; The serial data output of transceiver links to each other with the serial data input of U7A shown in Figure 15, U8A.
As shown in figure 14, other 3 tunnel serial data inputs of transceiver link to each other with the serial data output of U1 shown in Figure 12.
The utility model control circuit board carries the serial interface module, can directly link to each other with computer by serial to carry out exchanges data, conveniently equipment is configured, debugs.
Claims (4)
1. signaling voice collecting gateway is characterized in that: it mainly is made of housing and the signaling voice collecting plate, flush bonding processor and the two-way Optical Fiber Interface Board that are built in the housing; Signaling voice collecting plate is fixed in the housing, and flush bonding processor links to each other with signaling voice collecting plate by connector, is in signaling voice collecting plate top, and the two-way Optical Fiber Interface Board links to each other with signaling voice collecting plate by the connector of side;
The voice of described signaling voice collecting plate and signaling data are handled path and are made of Time Slot Switching Circuit, clock synchronizer, on-site programmable gate array FPGA, digital signal processing circuit DSP; The data processing path of two-way Optical Fiber Interface Board is made of Time Slot Switching Circuit, on-site programmable gate array FPGA, transceiver, SFP module; Time Slot Switching Circuit mainly is made of the time gas exchange chip;
The address bus of Time Slot Switching Circuit, FPGA, DSP, flush bonding processor, data/address bus, control bus link to each other; Time gas exchange chip output code flow in the electricity crack switched circuit has both direction, and one the tunnel is connected with the time gas exchange chip of two-way Optical Fiber Interface Board, and another road links to each other with the serial code stream input of FPGA; The EDMA synchronous signal output end of FPGA links to each other with the parallel data input EMIFA of DSP; The I/O end EMIFB of DSP links to each other with the I/O end that extends out SDRAM; The output code flow MCBSP mouth of DSP links to each other with FPGA; The PCI/HPI multiplexing port of DSP links to each other with the PCI port of flush bonding processor; Signaling voice collecting plate links to each other with computer gigabit network interface by the gigabit networking interface circuit; The debug signal of flush bonding processor links to each other with the serial ports of computers interface circuit by the serial ports of signaling voice collecting plate;
Time gas exchange chip one road code stream of two-way Optical Fiber Interface Board links to each other with the time gas exchange chip of signaling voice collecting plate, and another road links to each other with the FPGA of two-way Optical Fiber Interface Board; Another road serial code stream of FPGA links to each other with transceiver; Transceiver also has the two-way serial code stream to link to each other with two SFP modules respectively.
2. a kind of signaling voice collecting gateway according to claim 1, it is characterized in that: it also is provided with SONET/SDH system clock synchronizer, mainly is to produce the system synchronization clock to give time gas exchange chip, FPGA, DSP, transceiver; In addition, also has a phase-locked loop, for transceiver provides reference clock.
3. a kind of signaling voice collecting gateway according to claim 1 is characterized in that: described signaling voice collecting plate is provided with two gigabit network interfaces, a serial ports.
4. a kind of signaling voice collecting gateway according to claim 1, it is characterized in that: described housing is made up of upper and lower two parts, and upper and lower casing is by screw together; Power module and signaling voice collecting plate are fixed on the lower house, and two gigabit network interfaces, serial ports, power supply indicator, system's run indicator and 8 road light mouth run indicator are arranged on the lower house front panel; On the lower house rear board 4 two-way Optical Fiber Interface Board sockets, power interface and mains switches.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009202706165U CN201813391U (en) | 2009-11-20 | 2009-11-20 | Signaling-voice acquisition gateway |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009202706165U CN201813391U (en) | 2009-11-20 | 2009-11-20 | Signaling-voice acquisition gateway |
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| CN201813391U true CN201813391U (en) | 2011-04-27 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN104683228A (en) * | 2015-02-10 | 2015-06-03 | 海南宝通实业公司 | FPGA-based digital switch media gateway implementation method |
| CN116208479A (en) * | 2022-12-09 | 2023-06-02 | 四川天邑康和通信股份有限公司 | Voice port matching method, system, electronic equipment and readable storage medium |
-
2009
- 2009-11-20 CN CN2009202706165U patent/CN201813391U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN102833002B (en) * | 2012-08-23 | 2014-12-10 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN104683228A (en) * | 2015-02-10 | 2015-06-03 | 海南宝通实业公司 | FPGA-based digital switch media gateway implementation method |
| CN104683228B (en) * | 2015-02-10 | 2018-07-24 | 海南宝通实业公司 | A kind of digital switch media gateway realization method based on FPGA |
| CN116208479A (en) * | 2022-12-09 | 2023-06-02 | 四川天邑康和通信股份有限公司 | Voice port matching method, system, electronic equipment and readable storage medium |
| CN116208479B (en) * | 2022-12-09 | 2024-05-28 | 四川天邑康和通信股份有限公司 | Voice port matching method, system, electronic equipment and readable storage medium |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110427 Termination date: 20161120 |