CN201622408U - Liquid crystal display panel - Google Patents
Liquid crystal display panel Download PDFInfo
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- CN201622408U CN201622408U CN201020032950XU CN201020032950U CN201622408U CN 201622408 U CN201622408 U CN 201622408U CN 201020032950X U CN201020032950X U CN 201020032950XU CN 201020032950 U CN201020032950 U CN 201020032950U CN 201622408 U CN201622408 U CN 201622408U
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- test pin
- pixel electrode
- group
- electrode test
- tft
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- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 9
- 238000012360 testing method Methods 0.000 claims abstract description 135
- 239000000758 substrate Substances 0.000 claims description 29
- 239000010409 thin film Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 9
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000011056 performance test Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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Abstract
The utility model discloses a liquid crystal display panel, through the chip test pin with control chip and liquid crystal display panel's panel test pin electric connection to utilize the necessary test pin of panel to replace and draw this chip test pin to the chip test of control chip outside the region is applied in the subsides, and then improve the utilization ratio of the regional finite space of TFT step.
Description
Technical field
The utility model relates to technical field of liquid crystal display, particularly a kind of display panels.
Background technology
Display panels (Liquid Crystal Display Panel, LCD Panel) have low pressure, little power consumption, display message amount big, be easy to advantage such as colorize, now be widely used in the display device of electronic equipments such as robot calculator, electronic notebook, mobile phone, video camera, HDTV.The most basic structure of display panels as shown in Figure 1, it comprises TFT substrate 11 and the CF substrate 12 of fitting with described TFT substrate 11 relative configurations.Insert and put liquid crystal layer between TFT substrate 11 and the CF substrate 12, be applied to the molecular orientation of the electric field controls liquid crystal layer on the liquid crystal layer, and then reach the purpose of modulation by the light intensity of liquid crystal layer by two substrates.The size of CF substrate 12 is usually less than TFT substrate 11, and TFT substrate 11 forms TFT stepped area 111 in the zone that is not covered by CF substrate 12.Can stick control chip (IC) 13 on the TFT stepped area 111, be used to control the function of this panel.And, be formed with one group of panel test pin (panel test pad) 14 on the TFT stepped area 111, be used for counter plate and carry out electric performance test.Control chip 13 has a plurality of chip testing pins (not shown), in order after sticking control chip 13, conveniently to carry out the chip electric performance test, need these a plurality of chip testing pins are drawn out to sticking outside the zone of control chip 13, draw pin 15 thereby form a core assembly built-in testing.
Fig. 2 has further shown the basic structure synoptic diagram of TFT stepped area in the above-mentioned display panels.Among Fig. 2, this group panel test pin 14 comprises red pixel electrode test pin R, green pixel electrode test pin G, blue pixel electrode test pin B and a public electrode test pin Com.Sticking of control chip 13 is formed with 6 thin film transistor (TFT)s (TFT) in the zone, public electrode test pin Com controls this 6 transistorized conductings and shutoff.One end of each thin film transistor (TFT) is electrically connected to a pixel electrode test pin (red pixel electrode test pin R or green pixel electrode test pin G or blue pixel electrode test pin B), and the other end is electrically connected to a respective pixel electrode that is formed in the TFT substrate.3 chip testing pins 131 of control chip 13 are drawn out to sticking outside the zone of control chip 13, form a core assembly built-in testing and draw pin 15.Yet this core assembly built-in testing is drawn the finite space that pin 15 has additionally taken the TFT stepped area, is subjected to great restriction when the design of narrow step and different in nature product (such as circular LCD).
The utility model content
The purpose of this utility model is to provide a kind of display panels, with the finite space of drawing shared TFT stepped area of the chip testing pin that reduces control chip.
The utility model provides a kind of display panels, it comprises TFT substrate and configuration relative with described TFT substrate and the CF substrate of fitting, be formed with a plurality of pixel electrodes in the described TFT substrate, described TFT substrate forms the TFT stepped area in the zone that is not covered by described CF substrate, be formed with one group of panel test pin on the described TFT stepped area, described one group of panel test pin comprises a plurality of pixel electrode test pin, described a plurality of pixel electrode test pin is used to test described a plurality of pixel electrode, and sticked control chip on the described TFT stepped area, described control chip has a plurality of chip testing pins, it is characterized in that described a plurality of chip testing pins electrically connect with described a plurality of pixel electrode test pin respectively.
Preferably, described a plurality of chip testing pin electrically connects with described a plurality of pixel electrode test pin respectively sticking outside the zone of described control chip.
Preferably, described a plurality of chip testing pin electrically connects with described a plurality of pixel electrode test pin respectively sticking in the zone of described control chip.
Preferably, sticking of described control chip is formed with a plurality of on-off elements in the zone, described one group of panel test pin also comprises a public electrode test pin, described public electrode test pin is controlled the conducting and the shutoff of described a plurality of on-off elements, one end of described each on-off element is electrically connected to a described pixel electrode test pin, and the other end is electrically connected to the described pixel electrode of a correspondence, and described a plurality of chip testing pins electrically connect with the described end of described a plurality of on-off elements respectively.
Preferably, sticking of described control chip is formed with first group of on-off element and second group of on-off element in the zone, described one group of panel test pin also comprises a public electrode test pin, described public electrode test pin is controlled the conducting and the shutoff of described first group of on-off element and described second group of on-off element, an end of each on-off element is electrically connected to a described pixel electrode test pin in described first group of on-off element, the other end of each on-off element is electrically connected to an end of each on-off element in described second group of on-off element in described first group of on-off element, the other end of each on-off element is electrically connected to the described pixel electrode of a correspondence in described second group of on-off element, described a plurality of chip testing pins respectively with described first group of on-off element in the described end of each on-off element electrically connect.
Preferably, described on-off element is a thin film transistor (TFT).
Compared with prior art, a kind of display panels that the utility model provides, by the chip testing pin of control chip and the panel test pin of display panels are electrically connected, thereby utilize the necessary test pin of panel to substitute the chip testing that sticks outside the zone that this chip testing pin is drawn out to control chip and draw pin, and then improve the utilization factor of the finite space of TFT stepped area.
Description of drawings
Fig. 1 is the basic structure synoptic diagram of display panels;
Fig. 2 is the basic structure synoptic diagram of TFT stepped area in the display panels of prior art;
Fig. 3 is the basic structure synoptic diagram according to TFT stepped area among first embodiment of display panels of the present utility model;
Fig. 4 is the basic structure synoptic diagram according to TFT stepped area among second embodiment of display panels of the present utility model;
Fig. 5 is the basic structure synoptic diagram according to TFT stepped area among the 3rd embodiment of display panels of the present utility model.
Embodiment
For the purpose of this utility model, feature are become apparent, embodiment of the present utility model is further described below in conjunction with accompanying drawing.
Core concept of the present utility model is, electrically connect by panel test pin, draw pin thereby utilize the necessary test pin of panel to substitute the chip testing that sticks outside the zone that this chip testing pin is drawn out to control chip with the chip testing pin of control chip and display panels.
Display panels of the present utility model comprises TFT substrate and configuration relative with described TFT substrate and the CF substrate of fitting.Be formed with a plurality of pixel electrodes in the described TFT substrate, described TFT substrate forms the TFT stepped area in the zone that is not covered by described CF substrate.Be formed with one group of panel test pin on the described TFT stepped area, described one group of panel test pin comprises a plurality of pixel electrode test pin (for example, red pixel electrode test pin R, green pixel electrode test pin G, blue pixel electrode test pin B).Described a plurality of pixel electrode test pin is used to test described a plurality of pixel electrode.And, having sticked control chip on the described TFT stepped area, described control chip has a plurality of chip testing pins, and wherein, described a plurality of chip testing pins can electrically connect with described a plurality of pixel electrode test pin respectively in many ways.Thus, utilize the necessary test pin of panel to substitute the chip testing that sticks outside the zone that will these a plurality of chip testing pins be drawn out to control chip and draw pin, improved the utilization factor of the finite space of TFT stepped area.When needs carry out the electric performance test of control chip, only the probe of equipment need be visited the pixel electrode test pin of correspondence.
Fig. 3 is the basic structure synoptic diagram according to TFT stepped area among first embodiment of display panels of the present utility model.In the present embodiment, control chip 13 has 131, one groups of panel test pins 14 of 3 chip testing pins and comprises red pixel electrode test pin R, green pixel electrode test pin G and blue pixel electrode test pin B.In Fig. 3,3 chip testing pins 131 electrically connect with red pixel electrode test pin R, green pixel electrode test pin G and blue pixel electrode test pin B respectively sticking outside the zone of control chip 13.
Certainly, in other embodiment of the present utility model, 3 chip testing pins 131 of control chip 13 can also electrically connect with red pixel electrode test pin R, green pixel electrode test pin G and blue pixel electrode test pin B respectively sticking in the zone of control chip 13.Below just further describe in conjunction with specific embodiments.
Fig. 4 is the basic structure synoptic diagram according to TFT stepped area among second embodiment of display panels of the present utility model.Sticking of control chip 13 is formed with 6 on-off elements 161 in the zone.One group of panel test pin 14 comprises red pixel electrode test pin R, green pixel electrode test pin G, blue pixel electrode test pin B and a public electrode test pin Com.Public electrode test pin Com controls the conducting and the shutoff of these 6 on-off elements 161.And an end of each on-off element is electrically connected to a pixel electrode test pin (red pixel electrode test pin R or green pixel electrode test pin G or blue pixel electrode test pin B), and the other end is electrically connected to a corresponding pixel electrode.Wherein, 3 of control chip 13 chip testing pins 131 electrically connect with the end that is connected to the pixel electrode test pin of these 6 on-off elements 161 respectively.Preferably, all on-off elements are thin film transistor (TFT) in the present embodiment.
Fig. 5 is the basic structure synoptic diagram according to TFT stepped area among the 3rd embodiment of display panels of the present utility model.Sticking of control chip 13 is formed with first group of on-off element 162 (comprising 3 on-off elements among Fig. 5) and second group of on-off element 163 (comprising 6 on-off elements among Fig. 5) in the zone.One group of panel test pin 14 comprises red pixel electrode test pin R, green pixel electrode test pin G, blue pixel electrode test pin B and a public electrode test pin Com.Public electrode test pin Com controls the conducting and the shutoff of first group of on-off element 162 and second group of on-off element 163.An end of each on-off element is electrically connected to a pixel electrode test pin (red pixel electrode test pin R or green pixel electrode test pin G or blue pixel electrode test pin B) in first group of on-off element 162, the other end of each on-off element is electrically connected to an end of each on-off element in second group of on-off element 163 in first group of on-off element 162, and the other end of each on-off element is electrically connected to a corresponding pixel electrode in second group of on-off element 163.Wherein, 3 of control chip 13 chip testing pins 131 respectively with first group of on-off element 162 in the end that is connected to the pixel electrode test pin of each on-off element electrically connect.Preferably, all on-off elements are thin film transistor (TFT) in the present embodiment.
In sum, a kind of display panels that the utility model provides, by the chip testing pin of control chip and the panel test pin of display panels are electrically connected, thereby utilize the necessary test pin of panel to substitute the chip testing that sticks outside the zone that this chip testing pin is drawn out to control chip and draw pin, and then improve the utilization factor of the finite space of TFT stepped area.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (6)
1. display panels, it comprises TFT substrate and configuration relative with described TFT substrate and the CF substrate of fitting, be formed with a plurality of pixel electrodes in the described TFT substrate, described TFT substrate forms the TFT stepped area in the zone that is not covered by described CF substrate, be formed with one group of panel test pin on the described TFT stepped area, described one group of panel test pin comprises a plurality of pixel electrode test pin, described a plurality of pixel electrode test pin is used to test described a plurality of pixel electrode, and sticked control chip on the described TFT stepped area, described control chip has a plurality of chip testing pins, it is characterized in that described a plurality of chip testing pins electrically connect with described a plurality of pixel electrode test pin respectively.
2. display panels as claimed in claim 1 is characterized in that, described a plurality of chip testing pins electrically connect with described a plurality of pixel electrode test pin respectively sticking outside the zone of described control chip.
3. display panels as claimed in claim 1 is characterized in that, described a plurality of chip testing pins electrically connect with described a plurality of pixel electrode test pin respectively sticking in the zone of described control chip.
4. display panels as claimed in claim 3, it is characterized in that, sticking of described control chip is formed with a plurality of on-off elements in the zone, described one group of panel test pin also comprises a public electrode test pin, described public electrode test pin is controlled the conducting and the shutoff of described a plurality of on-off elements, one end of described each on-off element is electrically connected to a described pixel electrode test pin, and the other end is electrically connected to the described pixel electrode of a correspondence, and described a plurality of chip testing pins electrically connect with the described end of described a plurality of on-off elements respectively.
5. display panels as claimed in claim 3, it is characterized in that, sticking of described control chip is formed with first group of on-off element and second group of on-off element in the zone, described one group of panel test pin also comprises a public electrode test pin, described public electrode test pin is controlled the conducting and the shutoff of described first group of on-off element and described second group of on-off element, an end of each on-off element is electrically connected to a described pixel electrode test pin in described first group of on-off element, the other end of each on-off element is electrically connected to an end of each on-off element in described second group of on-off element in described first group of on-off element, the other end of each on-off element is electrically connected to the described pixel electrode of a correspondence in described second group of on-off element, described a plurality of chip testing pins respectively with described first group of on-off element in the described end of each on-off element electrically connect.
6. as each described display panels in claim 4 or 5, it is characterized in that described on-off element is a thin film transistor (TFT).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020032950XU CN201622408U (en) | 2010-01-12 | 2010-01-12 | Liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020032950XU CN201622408U (en) | 2010-01-12 | 2010-01-12 | Liquid crystal display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201622408U true CN201622408U (en) | 2010-11-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201020032950XU Expired - Lifetime CN201622408U (en) | 2010-01-12 | 2010-01-12 | Liquid crystal display panel |
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| CN (1) | CN201622408U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336598A (en) * | 2013-06-07 | 2013-10-02 | 业成光电（深圳）有限公司 | Touch display device |
| CN110189671A (en) * | 2019-06-26 | 2019-08-30 | 滁州惠科光电科技有限公司 | At box test circuit, array substrate and liquid crystal display device |
-
2010
- 2010-01-12 CN CN201020032950XU patent/CN201622408U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336598A (en) * | 2013-06-07 | 2013-10-02 | 业成光电（深圳）有限公司 | Touch display device |
| CN103336598B (en) * | 2013-06-07 | 2016-06-08 | 业成光电（深圳）有限公司 | Touch control display apparatus |
| CN110189671A (en) * | 2019-06-26 | 2019-08-30 | 滁州惠科光电科技有限公司 | At box test circuit, array substrate and liquid crystal display device |
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|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101103 |
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| CX01 | Expiry of patent term |