CN201177747Y - Electrohydraulic ratio controller based on field programmable gate array (FPGA) - Google Patents

Abstract

The utility model relates to an electro-hydraulic proportional controller based on a field programmable gate array FPGA. The electro-hydraulic proportional controller is characterized in that two input signal ports are connected with an FPGA unit after passing through two input conditioning circuits and an analog-digital conversion circuit, an upper machine is connected with the FPGA unit through a serial circuit, and a nixie tube is connected with the FPGA unit; two proportional control objects are connected with the FPGA unit after respectively passing through two sampling circuits and two preamplifier circuits as well as the other analog-digital conversion circuit; and two output signal lines of the FPGA unit are connected with the two proportional control objects after respectively passing through two linear isolating circuits and two power amplification circuit. Since the electro-hydraulic proportional controller adopts the FPGA controlling circuit to replace the analog circuit or the monolithic processor, thereby having the advantages of high reliability, good control real time and simple and flexible programming.

Description

Electrohydraulic proportional controller based on on-site programmable gate array FPGA

Technical field

The utility model relates to a kind of electrohydraulic proportional controller based on on-site programmable gate array FPGA, is applicable to electro-hydraulic proportional control system.

Background technology

Electro-hydraulic proportional valve is a kind of electricity-liquid conversion element that the continually varying electrical input signal is converted pro rata to hydraulic signal output, its performance is near the performance of electrohydraulic servo valve, simultaneously have the advantage that contamination resistance is strong, cost is low again, in hydrostatic control, obtained widespread use.Electrohydraulic proportional controller is the electronic installation that control signal is converted to the power drive signal that is adapted to electro-hydraulic proportional valve.

At present, take a broad view of the research and the production status of domestic and international electrohydraulic proportional controller, extensively adopt based on simulation control or based on monolithic processor controlled method and design, but based on the electrohydraulic proportional controller of simulation control because the dispersiveness of analog device and the characteristics of built-up circuit, be difficult to adapt to various needs occasions, and there are temperature drift and zero point drift, and need a large amount of peripheral logical circuits in actual applications based on monolithic processor controlled electrohydraulic proportional controller, and stable want some doing, in case because external disturbance causes program fleet or resets, will cause grave error output, be difficult to satisfy the constantly requirement of the mechanical-electrical-hydraulic integration technology of development.

Summary of the invention

The utility model proposes a kind of electrohydraulic proportional controller based on on-site programmable gate array FPGA at the defective that exists in the prior art, can improve its reliability and control real-time, and the programming simple and flexible.

For achieving the above object, the utility model adopts following technical proposals: two input signal ports are respectively behind two input modulate circuits, connect a FPGA unit through an analog to digital conversion circuit again, a host computer connects described FPGA unit through a serial port circuit, and a charactron connects described FPGA unit; Two proportional control objects behind two sample circuits and two pre-amplification circuits, connect described FPGA unit through another analog to digital conversion circuit respectively again; Two output signal lines of described FPGA unit are connected described two proportional control objects through two circuit linearity insulating circuits respectively with two power amplification circuits.

Described electric current input modulate circuit is made up of U11, U12, U13 and some resistance, above-mentioned U11, U12, U13 are that model is the operational amplifier of 0P-07, connected mode is: interface JP6 input current, through the circuit that resistance R 37 and R36, U11, U12, U13 form, the voltage of a U-IN-2 of output; Described voltage input modulate circuit is made up of U14 and U15, and wherein U14 is a jumper switch, and U15 is photoelectrical coupler TLP521, and connected mode is: interface JP7 input voltage, and U-IN and U-IN-2 insert U14, and U15 inserts U14; Described two analog to digital conversion circuits are formed by U5, wherein U5 is A/D conversion chip AD7819, connected mode is: the signal U-IN-1 of U14 inserts 2 pin of U5 through resistance R 6,16 terminations of U5+5V power supply, and the pin 8,9,10,11,12,13,14,15 of U5 inserts the I/O mouth of U1; Described FPGA is made up of U1 the unit, wherein U1 is that model is the fpga chip of EP1C6T144C8, connected mode is: 9 of U1,30,116,138,80,101,43,65,45,54,63,119,127,136 end ground connection, 87 of U1,86,14 ends connect+the 3.3V level through resistance, 22 of U1,23,13,24 end resistance groundeds, 8 of U1,29,115,137,81,102,44,66 terminations+3.3V level, and through capacitor C 6 ground connection, 135 of U1,126,117,64,55,46 terminations+1.5V level, and through capacitor C 5 ground connection, 26 ends of U1 connect 5 pin of U2 through resistance, 81 of U1,59,90,95 termination socket JP2, the I/O mouth of U1 receives the input quantity of U5 and the signal of U7, receives host computer through U8; Described serial port circuit is made up of U8, wherein U8 is serial ports level transferring chip MAX3232, connected mode is: 1 of U8,3 ends connect through capacitor C 21,4,5 ends connect through capacitor C 22,11 ends are through resistance R 41, diode DS2 connects+3.3V, and receive the I/O mouth of U1,12 ends are through resistance R 40, diode DS1 connects+3.3V, and receive the I/O mouth of U1,10 ends are through resistance R 42, diode DS3 connects+3.3V, and receives the I/O mouth of U1, and 9 ends are through resistance R 43, diode DS4 connection+3.3V, and connect the I/O mouth of U1,7 ends and 14 terminations are gone into JP3, and 13 ends and 5 terminations are gone into JP4, JP3, JP4 inserts 2 ends and 3 ends of JP5,2 ends are through capacitor C 24,6 ends are through capacitor C 25,15 end ground connection, 16 terminations+3.3V level; Described two circuit linearity insulating circuits (S8, S9) are all selected HCNR200 for use; Described two power amplification circuits and two sample circuits are formed by Darlington transistor Q1, Q2 and some resistance, and connected mode is: I-1 holds input, socket JP8 external load, and the signal of I-f1 and I-f2 end inserts pre-amplification circuit; Described two pre-amplification circuits are formed by U7 (LM358) and some resistance, electric capacity, and connected mode is: I-f1 and the input of I-f2 end, and the I-f termination is gone into the Vin end of analog to digital conversion circuit; Described host computer is a PC; Described two proportional control objects are power control type or Stroke Control type proportion electro-magnet.

Control module, communication module and driver module are set in described fpga chip; Control module, communication module and driver module interconnect.

Compared with prior art, the beneficial effects of the utility model are embodied in: because the utility model adopts FPGA to realize its function, reliability is better than existing electrohydraulic proportional controller; Because fpga chip has very fast speed, can reduce the signal operation cycle, improve the performance of system; Because fpga chip is able to programme, can upgrade to the utility model at any time, has very high dirigibility.

Description of drawings

Fig. 1 is the structured flowchart of an embodiment of the present utility model;

Fig. 2 is the electric current input modulate circuit schematic diagram of Fig. 1 example;

Fig. 3 is the voltage input modulate circuit schematic diagram of Fig. 1 example;

Fig. 4 is the switching power circuit schematic diagram of Fig. 1 example;

Fig. 5 is the analog to digital conversion circuit schematic diagram of Fig. 1 example;

Fig. 6 is the FPGA unit schematic diagram of Fig. 1 example;

Fig. 7 is the serial port circuit schematic diagram of Fig. 1 example;

Fig. 8 is the circuit linearity insulating circuit cut-away view of Fig. 1 example;

Fig. 9 is the power amplification circuit and the sample circuit schematic diagram of Fig. 1 example;

Figure 10 is the pre-amplification circuit schematic diagram of Fig. 1 example;

Figure 11 is the fpga chip functional block diagram and the interface specification of Fig. 1 example;

Figure 12 is the fpga chip driver module block diagram of Fig. 1 example.

Below pass through embodiment, and the utility model is described in further detail in conjunction with the accompanying drawings.

Embodiment

Details are as follows in conjunction with the accompanying drawings for a preferred embodiment of the present utility model:

Referring to Fig. 1, the controlling object of present embodiment is power control type or Stroke Control type proportion electro-magnet, and host computer and proportion electro-magnet do not belong in the utility model among the figure.Two input signal port E1, E2 are respectively behind two input modulate circuit S1, S2, connect a FPGA cell S 5 through an analog to digital conversion circuit S3 again, a host computer E3 connects described FPGA unit through a serial port circuit S6, and a charactron S4 connects described FPGA cell S 5; Two proportional control object E5, E6 behind two sample circuit S14, S15 and two pre-amplification circuit S10, S11, connect described FPGA cell S 5 through another analog to digital conversion circuit S7 respectively again; Two output signal lines of described FPGA unit are connected described two proportional control object E5, E6 through two circuit linearity insulating circuit S8, S9 respectively with two power amplification circuit S12, S13.

Analog control signal by the input of analog quantity input interface, has current input terminal mouth E1 and voltage input end mouth E2 by peripheral hardware.Described electric current input modulate circuit S2 becomes voltage signal with current input terminal mouth E1 conversion of signals, and it is nursed one's health in the voltage range of standard, by interface JP6 input, is output as U-IN-2, and inserts jumper switch U14, and its circuit theory diagrams as shown in Figure 2; Described voltage input modulate circuit S1 can stir U14 and select input channel, and by interface JP7 input, U-IN and U-IN-2 insert U14, are output as U-IN-1, insert the Vin end of U5, and its circuit theory diagrams as shown in Figure 3.

Switching Power Supply is made up of U9 (LM2575) and U10 (MC34063), and to the operational amplifier power supply, its circuit theory as shown in Figure 4.

Analog-digital conversion circuit as described S3, S7 are converted to digital quantity with analog quantity, the present invention has the analog conversion circuit of 2 same principle, only introduces a place here, and input signal U-IN-1 inserts 2 pin of U5 (AD7819), the output of U5 inserts the I/O mouth of U1, and its circuit theory diagrams as shown in Figure 5.

5 pairs of given input signals of described FPGA cell S and feedback current signal carry out computing, export 2 road PWM drive signals, 5 pin of the 26 termination U2 (active crystal oscillator) of U1 (EP1C6T144C8), 81,59,90, the 95 termination socket JP2 of U1, the current signal that input quantity after the I/O mouth access U5 conversion of U1 and U7 handled, receive host computer by U8, U4 (LT1084) provides+1.5V voltage, U3 (LT1084) provides+3.3V voltage, U2 provides clock signal, JP2 is a jtag interface, socket JP1 external power supply, and its circuit theory diagrams are as shown in Figure 6.

The present embodiment PC is a host computer, and serial ports is the RS-232-C communication interface.Described serial port circuit S6 is used for being connected of host computer E3 and FPGA cell S 5, and 11 ends of U8 (MAX3232), 12 ends, 10 ends, 9 terminations are gone into the I/O mouth of U1, and its 7 end and 14 terminations are gone into JP3, and 13 ends and 5 terminations are gone into JP4, and its circuit theory diagrams as shown in Figure 7.

Two-way PWM drive signal must linearly be isolated.Described two circuit linearity insulating circuit S8, S9 select linear optical coupling HCNR200 for use, by external different discrete device, can realize multiple photoelectricity isolation change-over circuit, and its cut-away view as shown in Figure 8.

Output signal just can drive the ratio controlling object after need carrying out power amplification.Described two power amplification circuit S12, S13 and two sample circuit S14, S15 amplify the PWM drive signal, and finish the sampling of feedback current, pwm signal is gone into from the I-1 termination, socket JP8 is used for external, resistance R 46 and R47 are sample resistances, I-f1 and I-f2 termination are gone into two pre-amplification circuit S10, S11, and its circuit theory diagrams as shown in Figure 9.

Described two pre-amplification circuit S10, S11 to current sampling signal carry out comprehensively, filtering and amplification, constitute the negative feedback of the electric current degree of depth, I-f1 and the input of I-f2 end, output terminal I-f inserts the Vin end of analog to digital conversion circuit, its circuit theory diagrams as shown in figure 10.

Described fpga chip carries out computing and processing to given input signal and feedback current signal, controlled variable is given by host computer E3, its functional block diagram and interface specification are as shown in figure 11, input parameter is sent into control module S51 and driver module S53 after the fpga chip internal priority is judged, communication module S52 is a functional module of handling above-mentioned host computer E3 and 5 data interactions of FPGA cell S.Host computer procedure adopts Visual Basic to write, and comprises the transmission and acceptance and the relevant parameter that is provided with of serial ports.

Referring to Figure 12, driver module S53 carries out processing such as PWM waveform generation, dead area compensation processing, ramp signal generation with the signal of control module S51 output, produces the digital signal with Dead Time able to programme; The PWM waveform generator can produce corresponding PWM carrier wave according to pulsewidth, and its frequency adjustable, dutycycle are 5% ~ 95%; The Dead Time that dead area compensation is handled is adjustable, and is defined as minimum Dead Time, and setting value is less than the Dead Time of driven signal; The lifting time parameter that ramp signal takes place produces ramp signal according to the performance setting of proportioning valve; According to the selection of Controlled valve, exportable one the road or two-way PWM drive signal; Current feedback signal can show the current value of load by step-by-step counting in charactron (S4); Current feedback is made of the state machine of a band house dog, powers up the back house dog and changes its mode of operation and drive its continuous sampling by state machine.Each function " circuit " is explained with Verilog HDL, realizes by digital circuit.

Claims (4)

1. electrohydraulic proportional controller based on on-site programmable gate array FPGA, it is characterized in that: two input signal port E1, E2 are respectively behind two input modulate circuits (S1, S2), connect a FPGA unit (S5) through an analog to digital conversion circuit (S3) again, a host computer (E3) connects described FPGA unit through a serial port circuit (S6), and a charactron (S4) connects described FPGA unit (S5); Two proportional control objects (E5, E6) behind two sample circuits (S14, S15) and two pre-amplification circuits (S10, S11), connect described FPGA unit (S5) through another analog to digital conversion circuit (S7) respectively again; Two output signal lines of described FPGA unit are connected described two proportional control objects (E5, E6) through two circuit linearity insulating circuits (S8, S9) with two power amplification circuits (S12, S13) respectively.

2. the electrohydraulic proportional controller based on on-site programmable gate array FPGA according to claim 1, it is characterized in that: described electric current input modulate circuit (S2) is made up of U11, U12, U13 and some resistance, connected mode is: interface JP6 input current, through the circuit that resistance R 37 and R36, U11, U12, U13 form, the voltage of a U-IN-2 of output; Described voltage input modulate circuit (S1) is made up of U14 and U15, and connected mode is: interface JP7 input voltage, and U-IN and U-IN-2 insert U14, and U15 inserts U14; Described two analog to digital conversion circuits (S3, S7) are formed by U5, and connected mode is: the signal U-IN-1 of U14 inserts 2 pin of U5 through resistance R 6,16 terminations of U5+5V power supply, and the pin 8,9,10,11,12,13,14,15 of U5 inserts the I/O mouth of U1; Described FPGA unit (S5) is made up of U1, connected mode is: 9 of U1,30,116,138,80,101,43,65,45,54,63,119,127,136 end ground connection, 87 of U1,86,14 ends connect+the 3.3V level through resistance, 22 of U1,23,13,24 end resistance groundeds, 8 of U1,29,115,137,81,102,44,66 terminations+3.3V level, and through capacitor C 6 ground connection, 135 of U1,126,117,64,55,46 terminations+1.5V level, and through capacitor C 5 ground connection, 26 ends of U1 connect 5 pin of U2 through resistance, 81 of U1,59,90,95 termination socket JP2, the I/O mouth of U1 receives the input quantity of U5 and the signal of U7, receives host computer through U8; Described serial port circuit (S6) is made up of U8, connected mode is: 1 of U8,3 ends connect through capacitor C 21,4,5 ends connect through capacitor C 22,11 ends are through resistance R 41, diode DS2 connects+3.3V, and receive the I/O mouth of U1,12 ends are through resistance R 40, diode DS1 connects+3.3V, and receives the I/O mouth of U1, and 10 ends are through resistance R 42, diode DS3 connects+3.3V, and receive the I/O mouth of U1,9 ends are through resistance R 43, diode DS4 connection+3.3V, and connect the I/O mouth of U1,7 ends and 14 terminations are gone into JP3,13 ends and 5 terminations are gone into JP4, JP3, JP4 inserts 2 ends and 3 ends of JP5, and 2 ends are through capacitor C 24,6 ends are through capacitor C 25,15 end ground connection, 16 terminations+3.3V level; Described two circuit linearity insulating circuits (S8, S9) are all selected HCNR200 for use; Described two power amplification circuits (S12, S13) and two sample circuits (S14, S15) are formed by Q1, Q2 and some resistance, and connected mode is: I-1 holds input, socket JP8 external load, and the signal of I-f1 and I=f2 end inserts pre-amplification circuit; Described two pre-amplification circuits (S10, S11) are formed by U7 and some resistance, electric capacity, and connected mode is: I-f1 and the input of I-f2 end, and the I-f termination is gone into the Vin end of analog to digital conversion circuit; Described host computer (E3) is a PC; Described two proportional control objects (E5, E6) are power control type or Stroke Control type proportion electro-magnet.

3. the electrohydraulic proportional controller based on on-site programmable gate array FPGA according to claim 2, it is characterized in that: above-mentioned U1 is that model is the fpga chip of EP1C6T144C8, above-mentioned U2 is the active crystal oscillator of 40MHz, above-mentioned U3 is the LT1084 chip of fixed value, above-mentioned U4 is adjustable LT1084 chip, above-mentioned U5 is A/D conversion chip AD7819, above-mentioned U6 is the TLC431 chip, above-mentioned U7 is that model is the operational amplifier of LM358, above-mentioned U8 is serial ports level transferring chip MAX3232, above-mentioned U9 is switch voltage-stabilizing piece LM2575, above-mentioned U10 is DC/DC converter control circuit MC34063, above-mentioned U11, U12, U13 is that model is the operational amplifier of OP-07, and above-mentioned U14 is a jumper switch, above-mentioned U15 is photoelectrical coupler TLP521, above-mentioned Q1, Q2 is a Darlington transistor.

4. the electrohydraulic proportional controller based on on-site programmable gate array FPGA according to claim 2 is characterized in that: control module (S51), communication module (S52) and driver module (S52) are set in described fpga chip; Control module (S51), communication module (S52) and driver module (S52) interconnect.

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