CN200950636Y - Television set with digital-analog integrated tuner - Google Patents
Television set with digital-analog integrated tuner Download PDFInfo
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- CN200950636Y CN200950636Y CNU2006200104552U CN200620010455U CN200950636Y CN 200950636 Y CN200950636 Y CN 200950636Y CN U2006200104552 U CNU2006200104552 U CN U2006200104552U CN 200620010455 U CN200620010455 U CN 200620010455U CN 200950636 Y CN200950636 Y CN 200950636Y
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Abstract
The utility model discloses a television set with digit analog integration radio-frequency head, which is aimed at realizing a function of receiving and decoding processing with one radio-frequency head at the time to perform a digital and an analog television signal; the device includes a digit and an analog integration radio-frequency head module and a decoding processing circuit; the digit and the analog integration radio-frequency head module produces the received ATSC digital television signal and NTSC analog television signal into a digital MPEG-2 signal and an analog CVBS signal respectively after being processed by a digital processing circuit and an analog processing circuit inside; the digital MPEG-2 signal is output to the decoding processing circuit for digital VSB demodulation and MPEG-2 decoding through a digital intermediate frequency signal output terminal of the high-frequency module; the analog CVBS signal is output to the decoding processing circuit through a analog signal output terminal of the high-frequency module for analog signal decoding; the output terminal of the decoding processing circuit is connected with a scaling circuit to carry output display of alive television programs.
Description
Technical field
The utility model relates to a kind of improvement of TV set circuit, specifically, relates to a kind of ATSC digital signal that can send TV station by a tuner and NTSC analog signal and realizes the control circuit that receives simultaneously, handle.
Background technology
At present, the TV signal ATSC digital signal of north America region and NTSC analog signal are also deposited, corresponding some television set that exports to this area is subjected to the restriction of self design that two tuners need be set, one receives the ATSC digital signal that TV station sends, another receives the NTSC analog signal, cause the TV set circuit integrated level low, it is big to take the complete machine space, and the user uses comparatively problem such as trouble.If can only both can receive analog signal with a tuner, again can demodulated digital signal, then not only can improve the integrated level and the stability of TV set circuit, the while again can be user-friendly.Therefore, how designing a kind of so digital-analog integrated receiving processing circuit, is that present television set is made one of subject matter that industry needs to be resolved hurrily.
Summary of the invention
The utility model need use two tuners to receive respectively that the circuit level that is brought is low, big problem takes up room in order to solve in the prior art anolog TV signals and digital television signal, a kind of novel digital-analog integrated receiving processing circuit is provided, adopt digital-analog integrated tuner module to cooperate simple peripheral circuit, receive and processing capacity when having realized anolog TV signals and digital television signal, effectively simplify circuit structure, improved the integrated level of TV set circuit.
For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:
A kind of television set with digital-analog integrated tuner, comprise digital-analog integrated tuner module and decoding treatment circuit, described digital-analog integrated tuner module with the ATSC digital television signal that receives and NTSC anolog TV signals respectively after its inner digital processing circuit and analog processing circuit are handled, generate digital MPEG-2 signal and simulation CVBS signal, described digital MPEG-2 signal outputs to through the digital medium-frequency signal output of digital-analog integrated tuner module and carries out digital VSB in the described decoding processing circuit and separate and be in harmonious proportion the MPEG-2 decoding; Described simulation CVBS signal outputs to through the analog signal output of digital-analog integrated tuner module and carries out the analog signal decoding in the described decoding processing circuit; The output of described decoding processing circuit connects the convergent-divergent circuit of television set.
Wherein, the digital medium-frequency signal output of described digital-analog integrated tuner module has two, and the output differential intermediate frequency connects the middle frequency difference sub-signal input of described decoding processing circuit through filter circuit.
In order to make the I of digital-analog integrated tuner module
2The bus level of C bus level and decoding processing circuit is complementary, the I of described digital-analog integrated tuner module
2The C bus end connects the bus end of described decoding processing circuit through the bus level change-over circuit.Include two N-channel MOS pipes in described bus level change-over circuit, one is connected on the SDA bus, and another is connected on the SCL bus; Wherein, the source electrode of described metal-oxide-semiconductor connects the bus end of digital-to-analogue integral high frequency head module, and connects a potential value first DC power supply identical with the bus potential value of described digital-analog integrated tuner module through pull-up resistor; The drain electrode of metal-oxide-semiconductor connects the bus end of described decoding processing circuit, and connects a potential value second DC power supply identical with the bus potential value of described decoding processing circuit through pull-up resistor; The grid of metal-oxide-semiconductor connects described second DC power supply.In the utility model, the model of considering selected digital-analog integrated tuner module is FQD1236MK5, and the decoding processing circuit is to be that the decoding processing chip of X240H is realized by a model, so, select potential value be the DC power supply of 5V as first DC power supply, selecting potential value is that the DC power supply of 3.3V is as second DC power supply.
The simulation second accompanying sound intermediate frequency signal output of described digital-analog integrated tuner module connects the audio signal input of described decoding processing chip; The automatic gain control end connects the gain compensation signal input of described decoding processing chip.
In addition, being built-in with a voltage switch in described digital-analog integrated tuner module, is that digital signal or analog signal are switched between the digital processing circuit of portion and two passages of analog processing circuit automatically within it according to the TV signal that receives.
Compared with prior art, advantage of the present utility model and good effect are: the utility model is by being provided with digital-analog integrated tuner module and decoding processing main control chip in television set inside, receive the decode processing when adopting a tuner promptly to realize digital television signal and anolog TV signals, not only simplified line construction, dwindled the circuit volume, and the high-quality of effectively having guaranteed digital signal and analog signal is exported, greatly improved the stability of system's operation, provide assurance television set complete machine quality.
Description of drawings
Fig. 1 is the circuit catenation principle figure between digital-analog integrated tuner module and the decoding processing main control chip in the utility model.
Embodiment
The utility model is described in more detail below in conjunction with the drawings and specific embodiments.
The utility model employing model is that the digital-analog integrated tuner module U001 of FQD1236MK5 receives ATSC digital signal and the NTSC analog signal that TV station sends, after its inner digital processing circuit and analog processing circuit processing, generate digital MPEG-2 signal and output in the decoding processing circuit with simulation CVBS signal.It is the decoding processing main control chip realization of X240H that described decoding processing circuit adopts a model, and digital MPEG-2 signal of logarithmic mode integral high frequency head module U001 output carries out digital VSB and separates mediation MPEG-2 decoding; After the simulation CVBS signal of tuner module U001 output simulated the NTSC decoding, the output by the decoding processing main control chip was sent to and carries out convergent-divergent in the convergent-divergent circuit of back level and handle, and then realizes that the output of TV programme shows.
In described digital-analog integrated tuner module U001, be built-in with a voltage switch, according to the TV signal that receives is that ATSC digital signal or NTSC analog signal are switched between the digital processing circuit of portion and two passages of analog processing circuit automatically within it, realizes the processing respectively of digital signal and analog signal.Concrete annexation between described digital-analog integrated tuner module U001 and the decoding processing main control chip is referring to shown in Figure 1.
Among Fig. 1, described digital-analog integrated tuner module U001 has 14 pins, and 1,2 pin are unsettled during use; 3 pin are connected+the 5V DC power supply through the LC filter network respectively with 13 pin, are respectively the digital demodulation unit and the power supply of analog demodulator unit of tuner module U001 inside; 4,5 pin are respectively the total stitch of SCL, SDA, because the bus level of the bus level of tuner module U001 and decoding processing main control chip is inconsistent, therefore, at its I
2Be connected with a bus level change-over circuit on the C bus.In described bus level change-over circuit, include two BSN20 type N-channel MOS pipe V001, V002, be connected on the SDA bus and the SCL bus on.Wherein, the source electrode of described metal-oxide-semiconductor V001, V002 is respectively through resistance R 005, the R009 data bus terminal SDA and corresponding connection of clock bus end SCL with digital-analog integrated tuner module U001, and respectively through pull-up resistor R004, R008 connection+5V DC power supply; The drain electrode of metal-oxide-semiconductor V001, V002 connects SDA, the SCL bus end of described decoding processing main control chip respectively, and respectively through pull-up resistor R001, R007 connection+3.3V DC power supply; The grid of described metal-oxide-semiconductor V001, V002 connects described+3.3V DC power supply, has realized the mutual coupling of bus level between digital-analog integrated tuner module U001 and the decoding processing main control chip thus.6 pin of tuner module U001 are automatic gain control pin IF_AGC, by rc filter circuit C010, R011 to decoding processing main control chip output gain compensating signal; 7,8 pin are differential digital medium-frequency IF signal output pins, output to the gain compensation signal input of described decoding processing main control chip after filter circuit is handled; 9,10 pin are unsettled; 11 pin are simulation second accompanying sound intermediate frequency signal NTSC_SIF output pins, connect the audio signal input of described decoding processing main control chip; 12 pin are simulation CVBS signal output pins, connect the input end of analog signal of described decoding processing main control chip; 14 pin are unsettled.
The utility model has realized that by adopting above-mentioned simple circuit configuration digital radio signal and analog radio-frequency signal adopt a tuner can finish the function of reception, effectively simplified circuit structure, improve the integrated level of TV set circuit, saved the complete machine cost of tv product.
Claims (9)
1. television set with digital-analog integrated tuner, it is characterized in that: comprise digital-analog integrated tuner module and decoding treatment circuit, described digital-analog integrated tuner module with the ATSC digital television signal that receives and NTSC anolog TV signals respectively after its inner digital processing circuit and analog processing circuit are handled, generate digital MPEG-2 signal and simulation CVBS signal, described digital MPEG-2 signal outputs to through the digital medium-frequency signal output of digital-analog integrated tuner module and carries out digital VSB in the described decoding processing circuit and separate and be in harmonious proportion the MPEG-2 decoding; Described simulation CVBS signal outputs to through the analog signal output of digital-analog integrated tuner module and carries out the analog signal decoding in the described decoding processing circuit; The output of described decoding processing circuit connects the convergent-divergent circuit of television set.
2. the television set with digital-analog integrated tuner according to claim 1 is characterized in that: the I of described digital-analog integrated tuner module
2The C bus end connects the bus end of described decoding processing circuit through the bus level change-over circuit.
3. the television set with digital-analog integrated tuner according to claim 2 is characterized in that: include two N-channel MOS pipes in described bus level change-over circuit, one is connected on the SDA bus, and another is connected on the SCL bus; Wherein, the source electrode of described metal-oxide-semiconductor connects the bus end of digital-to-analogue integral high frequency head module, and connects a potential value first DC power supply identical with the bus potential value of described digital-analog integrated tuner module through pull-up resistor; The drain electrode of metal-oxide-semiconductor connects the bus end of described decoding processing circuit, and connects a potential value second DC power supply identical with the bus potential value of described decoding processing circuit through pull-up resistor; The grid of metal-oxide-semiconductor connects described second DC power supply.
4. the television set with digital-analog integrated tuner according to claim 3 is characterized in that: the potential value of described first DC power supply is 5V, and the potential value of second DC power supply is 3.3V.
5. the television set with digital-analog integrated tuner according to claim 1 and 2 is characterized in that: the simulation second accompanying sound intermediate frequency signal output of described digital-analog integrated tuner module connects the audio signal input of described decoding processing circuit.
6. the television set with digital-analog integrated tuner according to claim 5 is characterized in that: the automatic gain control end of described digital-analog integrated tuner module connects the gain compensation signal input of described decoding processing circuit.
7. the television set with digital-analog integrated tuner according to claim 1, it is characterized in that: the digital medium-frequency signal output of described digital-analog integrated tuner module has two, and the output differential intermediate frequency connects the middle frequency difference sub-signal input of described decoding processing circuit through filter circuit.
8. the television set with digital-analog integrated tuner according to claim 1, it is characterized in that: being built-in with a voltage switch in described digital-analog integrated tuner module, is that digital signal or analog signal are switched between the digital processing circuit of portion and two passages of analog processing circuit automatically within it according to the TV signal that receives.
9. the television set with digital-analog integrated tuner according to claim 7 is characterized in that: described decoding processing circuit is that a model is the decoding processing chip of X240H.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200104552U CN200950636Y (en) | 2006-09-26 | 2006-09-26 | Television set with digital-analog integrated tuner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200104552U CN200950636Y (en) | 2006-09-26 | 2006-09-26 | Television set with digital-analog integrated tuner |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200950636Y true CN200950636Y (en) | 2007-09-19 |
Family
ID=38893180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2006200104552U Expired - Fee Related CN200950636Y (en) | 2006-09-26 | 2006-09-26 | Television set with digital-analog integrated tuner |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN200950636Y (en) |
-
2006
- 2006-09-26 CN CNU2006200104552U patent/CN200950636Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070919 Termination date: 20100926 |