CN1983824A - Method and system for realizing the second intersection and random access memory - Google Patents
Method and system for realizing the second intersection and random access memory Download PDFInfo
- Publication number
- CN1983824A CN1983824A CN 200610066392 CN200610066392A CN1983824A CN 1983824 A CN1983824 A CN 1983824A CN 200610066392 CN200610066392 CN 200610066392 CN 200610066392 A CN200610066392 A CN 200610066392A CN 1983824 A CN1983824 A CN 1983824A
- Authority
- CN
- China
- Prior art keywords
- data
- bit
- ram
- datas
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
The invention is concerned with the method and system to achieve the second interfelting. The system includes: the writing controlling unit, the random access memory (RAM) and the reading controlling unit. The method is based on the RAM and shift register achievement, confirms the width of RAM according to the bit number of the continuous outputting effective data, the depth is the biggest data load carrying capacity of the physics channel divides the width; writes the un-processing data that is corresponding with the once writing operating processing object into the shift register; writes the shifted data into the smallest address of the current un-wrote data; reads the data in the RAM address once according to read mode from the smallest to the biggest in the RAM address, takes the effective bit data output based on the effective bit data number of the continuous output. The invention can have data input in each system period, and achieves the second interfelting when one wireless frame data exists compression.
Description
Technical field
The present invention relates to the network communications technology, particularly relate to a kind of realization interweaving method and system and a kind of random access memory (RAM) for the second time.
Background technology
In network service,, on down channel, can encode to data stream usually for the transmission service is provided on wireless transmission link.Wherein, a kind of channel coding schemes comparatively commonly used is for interweaving for the second time.
At present, interweave for the second time with intersecting and realize by the mutual module of arranging of ranks.Be input to the symbol data symbol that interweaves for the second time, as u
P1, u
P2, u
P3..., u
PU, be written to following R by row
2* C
2Orthogonal matrix in:
At above-mentioned R
2* C
2Orthogonal matrix in, columns C
2Be fixed as 30, column number from left to right is followed successively by 0,1,2 ..., 29; And line number R
2Be to satisfy inequality U≤R
2C
2Smallest positive integral, wherein, U is the bit number on the physical channel in a radio frames.
In the prior art, realize that the process that interweaves for the second time comprises: for the above-mentioned R that receives
2* C
2Data in the orthogonal matrix are at first carried out column permutation to it; According to the rule of writing by row, calculate R then
2* C
2When the OPADD of previous Bit data, and, this Bit data is write among the RAM in the orthogonal matrix, repeat, until with R according to the OPADD that is calculated
2* C
2All Bit datas in the orthogonal matrix all write among the RAM; When needs read data among the RAM, from RAM, call over the data that write, and output.
By above description as can be seen, in the prior art, be the process object that is a write operation with a Bit data, i.e. write-once operation only writes the data of a bit among the RAM.But at present, the bit wide of RAM is not 1 usually in the chip, and its minimum bit wide is generally 4.Therefore, each the execution Bit data is write among the RAM in the particular address, prior art must at first read out existing data in this particular address among the RAM, the data that the data of being read and current need are write among the RAM are pieced together the position then, could write particular address among the RAM with piecing together data behind the position at last.This shows that when the data with any one bit write among the RAM, prior art all must be carried out read data, be pieced together position and three operations of write data, takies a plurality of system cycles and carry out these three action needs.In addition, in the prior art, data are write among the RAM at every turn, all need to calculate the address that writes among the RAM, therefore, further increased the shared system cycle of write data process.Like this, if at each system cycle the data input is arranged all, so, prior art then can't realize the process that interweave with the second time at all.
In addition, because at above-mentioned R
2* C
2Orthogonal matrix in, columns is fixed as 30, like this, if there is the situation of compression in wireless frame data of input, promptly Shu Ru data volume is not 30 multiple, so, at above-mentioned R
2* C
2Orthogonal matrix in, data can't be write full last column, piece together the position and will write process among the RAM thereby can't carry out follow-up column permutation and data, promptly can't realize the process that interweaves for the second time.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of realization interweaving method and system for the second time, another object of the present invention is to provide a kind of RAM, so that import under the continuous situation of data, realizes interleaving process for the second time.
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of realization is interweaving method for the second time, this method realizes based on a kind of RAM and a kind of shift register, wherein, the width of RAM requires continuously the bit number of the valid data of output to determine that its degree of depth is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; The bit wide of shift register is the number of bits corresponding to a write operation process object, and this method also comprises:
A, with R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix;
B, the data corresponding to a write operation process object in the shift register are interweaved;
C, the data corresponding to a write operation process object after will interweaving write among the RAM in the current lowest address that does not write data;
D, repeated execution of steps A be to step C, until with R
2* C
2All data all write among the RAM in the orthogonal matrix;
E, the mode that from the minimum to the maximum, reads successively according to address among the RAM, once read the data in address of RAM, require the number of the significant bit data of output continuously according to the back that interweaves for the second time, from all data that once read, take out the output of significant bit data, repeat this step, all data in output RAM.
Requiring continuously the bit number of the valid data of output after interweaving the described second time is 4;
The width of described RAM is 120 bits;
The bit wide of described shift register is 120 bits;
Described untreated data corresponding to a write operation process object are: current untreated preceding two line data in R2 * C2 orthogonal matrix.
Described step B comprises: according to displacement patterns between row, preceding 30 symbol datas and back 30 symbol datas interweave respectively in the shift register to described 120 bit bit wides;
In step C, the data corresponding to a write operation process object after described will interweaving write that the step in the current lowest address that does not write data comprises among the RAM: first symbol data after first symbol data after at first described preceding 30 symbol datas being interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, then, second symbol data after second symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, the rest may be inferred, and last symbol data after last symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively.
Requiring continuously the bit number of the valid data of output after interweaving the described second time is 2;
The width of described RAM is 60 bits;
The bit wide of described shift register is 60 bits;
Described untreated data corresponding to a write operation process object are: current untreated first line data in R2 * C2 orthogonal matrix.
The number of described shift register is 2;
In steps A, described shift register is the shift register that was not written into last time corresponding to write operation process object data.
In steps A, before execution writes data in the shift register, further comprise: described shift register is initialized as invalid 2 Bit datas.
Requiring continuously the bit number of the valid data of output after interweaving the described second time is 4;
In step e, described step of taking out data and output from all data that once read comprises:
E11, from all data that once read, take out preceding 4 Bit datas;
E12, judge in 4 Bit datas being got whether do not comprise invalid 2 Bit datas, if do not comprise, execution in step E13 then, if comprise two invalid 2 Bit datas, execution in step E14 then is if only comprise invalid 2 Bit data, then an execution in step E15;
E13, directly export this 4 Bit datas, finish current flow process;
E14, directly abandon this 4 Bit datas, finish current flow process;
E15, in 4 Bit datas that read, abandon one of them invalid 2 Bit data;
E16, judge 2 bit valid data of buffer memory before current whether the existence, if exist, then will before the valid data of 2 bits in 2 bit valid data and current 4 Bit datas that read of buffer memory piece together and export after becoming one 4 bit valid data, if there is no, then buffer memory reads 2 bit valid data in 4 Bit datas.
Requiring continuously the bit number of the valid data of output after interweaving the described second time is 2;
In step e, described step of taking out data and output from all data that once read comprises:
E21, from all data that once read, take out preceding 2 Bit datas;
E22, judge whether 2 Bit datas being got are invalid 2 Bit datas, if, execution in step E23 then, otherwise, execution in step E24;
E23, directly abandon the data of being taken out, finish current flow process;
The data that E24, direct output are taken out.
A kind of system that realizes that interweave with the second time, this system comprises: write control unit, RAM and read control unit, write and comprise the shift register subelement in the control unit and write the processing subelement, comprise at least one shift register in the shift register subelement, wherein, the width of RAM requires continuously the bit number of the valid data of output to determine that its degree of depth is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; The bit wide of shift register is the number of bits corresponding to a write operation process object, and,
Write the processing subelement, be used for R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix, and to after interweaving corresponding to the data of a write operation process object in the shift register, write among the RAM in the current lowest address that does not write data;
Any one shift register is used to receive the data corresponding to a write operation process object;
RAM is used for storing writing and handles the data that each address write of subelement at self;
Read control unit, be used for the mode that from the minimum to the maximum, reads successively according to the RAM address, once read all data in address of RAM, and require the bit number of output continuously, in all data that read, take out data according to the back that interweaves for the second time.
Comprise two shift registers in the described shift register subelement; These two shift registers are carried out the data that receive corresponding to a write operation process object in turn.
The described processing unit of writing is further used for the shift register in the shift register subelement is initialized as invalid 2 Bit datas.
This system further comprises: the dateout processing unit, be used to receive and read the data that control unit takes out, and abandon invalid 2 Bit datas in the received data, and requires the continuous valid data bit number of exporting according to the back that interweaves for the second time, export received data.
Describedly read control unit takes out preceding 4 bits in all data that read data;
Described dateout processing unit, be used for determining whether 4 received Bit datas do not comprise invalid 2 Bit datas, if do not comprise invalid 2 Bit datas, then directly export this 4 Bit datas, if comprise two invalid 2 Bit datas, then directly abandon this 4 Bit datas, if only comprise invalid 2 Bit datas, then in 4 Bit datas that read, abandon one of them invalid 2 Bit data and judge the current 2 bit valid data of buffer memory before that whether exist, if exist, then will before the valid data of 2 bits in 2 bit valid data and current 4 Bit datas that read of buffer memory piece together and export after becoming one 4 bit valid data, if there is no, then buffer memory reads 2 bit valid data in 4 Bit datas.
Describedly read control unit takes out preceding 2 bits in all data that read data;
Described dateout processing unit is used for determining whether 2 received Bit datas are invalid 2 Bit datas, if, then directly abandon this 2 Bit datas, otherwise, this 2 Bit datas directly exported.
A kind of RAM, this RAM is used for storing writing and handles the data that each address write of subelement at self, and, the width of this RAM requires continuously the bit number of the valid data of output to determine that the degree of depth of this RAM is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time.
This shows that the present invention is with R
2* C
2In the orthogonal matrix at least delegation promptly the data of 60 bits as the process object of a write operation, like this, when address that data is write among the RAM, then need not to carry out sense data in the prior art, piece together the position and write three operations of data, and only need carry out write operation, therefore, the shared time can be greater than a system cycle.In addition, in the present invention, data are write among the RAM, only need write according to the mode from the lowest address to the maximum address and get final product at every turn, and need not to write the calculating of address ram, therefore, have further reduced the shared system cycle of write data process.Like this, when each system cycle all had the data input, the present invention can realize interleaving process for the second time.
In addition, in the present invention, promptly in advance shift register is initialized as the practice of invalid 2 Bit datas, makes when there is the situation of compression in a wireless frame data, also can realize column permutation and write the process of RAM by filling invalid 2 Bit datas.Therefore, the present invention exists a wireless frame data and also can realize interleaving process for the second time under the compression situation.
Description of drawings
Fig. 1 is the basic structure schematic diagram of system of the present invention.
Figure 1A is the basic structure schematic diagram of system of the present invention when interweaving the continuous output of back requirement 4 bit valid data for the second time.
Figure 1B is the basic structure schematic diagram of system of the present invention when interweaving the continuous output in back 2 bit valid data for the second time.
Fig. 2 is the schematic diagram of optimizing structure of system of the present invention.
Fig. 3 is a flow chart of realizing write data in the interleaving process second time in embodiments of the present invention.
Fig. 4 is preceding 30 symbol datas and back 30 schematic diagrames that symbol data interweaves respectively in the shift register to 120 bit bit wides in embodiments of the present invention.
Fig. 5 is a flow chart of realizing read data in the interleaving process second time in embodiments of the present invention.
Fig. 6 is a flow chart of realizing exporting continuously 4 significant bit data in embodiments of the present invention.
Embodiment
The present invention proposes a kind of realization interweaving method for the second time, its core concept is: set in advance RAM, the width of this RAM requires continuously the bit number of the valid data of output to determine that its degree of depth then is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; Set in advance shift register, the bit wide of this shift register is the number of bits corresponding to a write operation process object; With R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix; Data corresponding to a write operation process object in the shift register are interweaved; The data corresponding to a write operation process object after will interweaving write among the RAM in the current lowest address that does not write data, repeat, until with R
2* C
2All data all write among the RAM in the orthogonal matrix; According to the mode that read from the minimum to the maximum successively address among the RAM, once read the data in address of RAM, get the back that wherein interweaves for the second time and require the Bit data of output continuously to export.
Wherein,, data are write before the shift register at every turn, all shift register is initialized as 60 invalid 2 Bit datas in order under the data compression situation, also to realize interleaving process for the second time.
The invention allows for a kind of system that realizes that interweave with the second time.Fig. 1 is the basic structure schematic diagram of system of the present invention.Referring to Fig. 1, system of the present invention mainly comprises: write control unit, RAM and read control unit, write and comprise the shift register subelement in the control unit and write the processing subelement, comprise at least one shift register in the shift register subelement, wherein, the width of RAM requires continuously the bit number of the valid data of output to determine that its degree of depth is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; The bit wide of shift register is the number of bits corresponding to a write operation process object, and,
Write the processing subelement, be used for R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix, and to after interweaving corresponding to the data of a write operation process object in the shift register, write among the RAM in the current lowest address that does not write data;
Any one shift register is used to receive the data corresponding to a write operation process object;
RAM is used for storing writing and handles the data that each address write of subelement at self;
Read control unit, be used for the mode that from the minimum to the maximum, reads successively according to the RAM address, once read all data in address of RAM, and require the bit number of output continuously according to the back that interweaves for the second time, data and the output in all data is read in taking-up.
In system of the present invention, in order also can to realize interleaving process for the second time under the data compression situation, the described processing unit of writing is further used for the shift register in the shift register subelement is initialized as invalid 2 Bit datas.
Fig. 2 is the schematic diagram of optimizing structure of system of the present invention.Referring to Fig. 2, in system of the present invention, may further include the dateout processing unit, be used to receive and read the data of being taken out when control unit reads at every turn, and delete invalid 2 Bit datas in the received data, require the valid data bit number of output continuously according to the back that interweaves for the second time, export received data.
Shown in Figure 1A, in the present invention, if consider the requirement of code rate, the back that promptly interweaves for the second time requires output 4 bit valid data continuously, so, is R corresponding to the data of a write operation process object
2* C
2The data of two row, 120 bits in the orthogonal matrix at this moment, comprise the shift register of two 120 bit bit wides in the shift register subelement, and the width of described RAM is 120 bits, and the degree of depth is physical channel maximum data bearing capacity/120.Accordingly, the dateout processing unit shown in Fig. 2 need be to reading the relevant treatment that 4 Bit datas that control unit reads are deleted invalid 2 Bit datas and pieced together position 4 bit valid data, thereby guarantee output 4 bit valid data continuously.
Shown in Figure 1B, in the present invention,, can export 2 bit valid data continuously after promptly interweaving for the second time if do not consider the requirement of code rate, so, be R corresponding to the data of a write operation process object
2* C
2The data of current untreated first row, 60 bits in the orthogonal matrix at this moment, comprise the shift register of two 60 bit bit wides in the shift register subelement, and the width of described RAM is 60 bits, and the degree of depth is physical channel maximum data bearing capacity/60.Accordingly, the dateout processing unit shown in Fig. 2 only needs to delete invalid 2 Bit datas and handle reading 2 Bit datas that control unit reads, thereby guarantees output 2 bit valid data continuously.
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with drawings and the specific embodiments.
Fig. 3 is a flow chart of realizing write data in the interleaving process second time in embodiments of the present invention.Referring to Fig. 3, utilize system of the present invention, the process that during the inventive method is implemented in and interweaves for the second time data is write RAM may further comprise the steps:
Step 301: set in advance a RAM.
Here, the width of set RAM requires continuously the bit number of the valid data of output to determine according to the back that interweaves for the second time; The degree of depth of set RAM then is the width of physical channel maximum data bearing capacity divided by this RAM.
Shown in Figure 1A, if consider the code rate requirement that interweave with the second time, the back that promptly interweaves for the second time requires to export continuously 2 symbol data symbol, and 1 symbol is 3 value sequences, is represented by 2 bits, and 2 symbol then are 4 bits.So, the R that interweaves for the second time according to above-mentioned realization
2* C
2Orthogonal matrix as can be seen since data symbol by by row from R
2* C
2Orthogonal matrix in read, therefore, if satisfy the code rate requirement that interweaves for the second time, the continuous data of promptly once reading 4 bits from RAM that is to say, once reads R from RAM
2* C
2Orthogonal matrix in 2 data symbol of same column in continuous two row, so, in the present invention, should be with R
2* C
2The data of continuous two row, 120 bits that is to say as the process object of a write operation in the orthogonal matrix, should write R in the address of set RAM
2* C
2Orthogonal matrix in continuous two the row data, promptly 60 symbol are 120 bits.Like this, in the present invention, the width of set RAM is 120 bits.And, the related spreading factor that interweaves for the second time is that the Data-carrying ability of 4 physical channel is 38400 bits, that is to say, the data that should store 38400 bits among the set RAM of the present invention, because determine that the width of RAM is 120 bits, so, its degree of depth then is the Data-carrying ability/width=38400/120=320 of physical channel, that is to say among the set RAM of the present invention 320 addresses are arranged.Therefore, can obtain: if consider the code rate requirement that interweave with the second time, set in this step RAM is 320 * 120 bits.
Shown in Figure 1B,, can export 1 symbol continuously after interweaving for the second time, i.e. 2 Bit datas if do not consider the code rate requirement that interweave with the second time.So, the R that interweaves for the second time according to above-mentioned realization
2* C
2Orthogonal matrix as can be seen since data symbol by by row from R
2* C
2Orthogonal matrix in read, therefore, if once from RAM, read the continuous data of 2 bits, so, can be with R
2* C
2The data of delegation's 60 bits that is to say as the process object of a write operation in the orthogonal matrix, can write R in the address of set RAM
2* C
2Orthogonal matrix in the data of delegation, promptly 30 symbol are 60 bits.Like this, in the present invention, the width of set RAM is 60 bits.And, the related spreading factor that interweaves for the second time is that the Data-carrying ability of 4 physical channel is 38400 bits, that is to say, the data that should store 38400 bits among the set RAM of the present invention, because determine that the width of RAM is 60 bits, so, its degree of depth then is the Data-carrying ability/width=38400/60=640 of physical channel, that is to say among the set RAM of the present invention 640 addresses are arranged.Therefore, can obtain: if do not consider the code rate requirement that interweave with the second time, set in this step RAM can be 640 * 60 bits.
Step 302: in writing control unit, the shift register subelement is set in advance, comprises two shift registers in this shift register subelement.
Here, the bit wide of set shift register is the number of bits corresponding to a write operation process object.Just,
Shown in Figure 1A, if the back that interweaves for the second time requires output 4 bit valid data continuously, promptly the number of bits corresponding to a write operation process object is R
2* C
2The data of current untreated preceding two row, 120 bits in the orthogonal matrix, so, in this step, in the shift register subelement, the bit wide of two shift registers is 120 bits;
Shown in Figure 1B, if can export 2 bit valid data continuously after interweaving for the second time, promptly the number of bits corresponding to a write operation process object is R
2* C
2The data of current untreated first row, 60 bits in the orthogonal matrix, so, in this step, in the shift register subelement, the bit wide of two shift registers is 60 bits.
Step 303: in writing control unit, write and handle subelement the shift register of current use in the shift register subelement is initialized as invalid 2 Bit datas.
Here, described invalid 2 Bit datas are " 01 " sequence.
Step 304: in writing control unit, write and handle subelement with R
2* C
2Data corresponding to a write operation process object in the orthogonal matrix write in the set shift register.
Need to prove, in the present invention, two shift registers are used in turn, that is to say, if shift register of this use receives the data corresponding to a write operation processing, so, next then use another shift register to receive the data of handling corresponding to write operation.
Step 305: in writing control unit, write the processing subelement and the data corresponding to a write operation process object in the shift register of current use are carried out interleaving treatment according to displacement patterns between existing row.
In above-mentioned steps 304 and step 305, permutation table can be referring to as shown in table 1 below between described existing row,
| Columns C 2 | Displacement patterns between row |
| 30 | {0，20，10，5，15，25，3，13，23，8，18，28，1，11，21，6，16，26，4， 14，24，19，9，29，12，2，7，22，27，17} |
Table 1
Referring to Figure 1A and Fig. 4, the back requires output 4 bit valid data continuously if interweave for the second time, so, the specific implementation process of this step comprises: according to displacement patterns between row, the data of the data of preceding 30 symbol and back 30 symbol interweave respectively in the shift register to described 120 bit bit wides.
Step 306: in writing control unit, write the data of handling after subelement will interweave and write the current lowest address that does not write data among the set RAM corresponding to a write operation process object.
Here, shown in Figure 1A, the back requires output 4 bit valid data continuously if interweave for the second time, so, the specific implementation process of this step comprises: write and handle will the interweave data of back 120 bits of subelement and write the current lowest address that does not write data among the set RAM, be specially, at first, first symbol data after first symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, then, second symbol data after second symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, the rest may be inferred, and last symbol data after last symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively.
Shown in Figure 1B, if can export 2 bit valid data continuously after interweaving for the second time, so, the specific implementation process of this step comprises: write and handle will the interweave data of back 60 bits of subelement and write the current lowest address that does not write data among the set RAM.
Step 307:, write control unit and carry out shift register reception R successively according to the principle of above-mentioned steps 303 to the described process of step 306
2* C
2Corresponding to the untreatment data of a write operation process object, and after interweaving, write among the set RAM in the current lowest address that does not write data in the orthogonal matrix.
Need to prove that owing to have the compression situation in data, during such as punching compression or high-rise specified compression, the data flow of input may not be 30 integral multiple.That is, at R
2* C
2Orthogonal matrix in, 60 situations that Bit data is not enough in last column may appear; Perhaps, R
2* C
2Orthogonal matrix in, though there are 60 Bit datas in last column, line number is an odd number.At this moment, in order to realize interweaving for the second time, then not enough data should be added according to invalid bit " 01 ".In concrete realization, can realize that not enough data add according to invalid bit " 01 " by the process of carrying out above-mentioned steps 303.This be because, carry out the process of above-mentioned steps 303, after set shift register is initialized as invalid 2 Bit datas respectively, to two shift register input data the time, the input Data Update the data of its shared position, not enough data then are made up of the invalid bit that writes in advance " 01 ", thereby have realized the purpose that not enough data are added according to invalid bit " 01 ", have avoided prior art can't realize the shortcoming that interweaves for the second time when there is the compression situation in data.
Fig. 5 is a flow chart of realizing read data in the interleaving process second time in embodiments of the present invention.Referring to Fig. 5, utilize system of the present invention, during the inventive method is implemented in and interweaves for the second time from RAM the process of sense data may further comprise the steps:
Step 501: the currency of reading the control unit cyclic variable is set to 1.
Step 502: read the mode that control unit reads from the minimum to the maximum successively according to address among the set RAM, once read the data in address of RAM.
Step 503: read control unit whenever reading the data in the address, get the back that interweaves for the second time and require the Bit data of output continuously.
Here, shown in Figure 1A,, so, in this step, be to get preceding 4 Bit datas in 120 Bit datas in the address that read if the back that interweaves for the second time requires output 4 bit valid data continuously.
Shown in Figure 1B,, so, in this step, be to get preceding 2 Bit datas in 60 Bit datas in the address that read if can export 2 bit valid data continuously after interweaving for the second time.
Step 504: in this address cycle, after the data in having read RAM in last address, read control unit the currency of cyclic variable is added 1.
Step 505: whether read currency that control unit judges cyclic variable greater than 30, if, then finish current flow process, otherwise, step 502 returned.
So far, to process shown in Figure 5, the present invention has then realized the process that interweave with the whole second time by above-mentioned Fig. 3.
Need to prove, in above-mentioned process shown in Figure 5, if do not consider the requirement of code rate, the continuous 2 bit valid data of back output promptly guarantee to interweave for the second time, and in the data of being taken out, comprise invalid 2 Bit datas probably, so, referring to Fig. 2, in above-mentioned steps 503, may further include: the dateout processing unit receives reads 2 Bit datas that control unit takes out, judge whether this 2 Bit data is invalid 2 Bit datas " 01 ", if then delete these invalid 2 Bit datas, promptly do not export, if not, so, then directly export this 2 Bit data that is read.
Fig. 6 is a flow chart of realizing exporting continuously 4 significant bit data in embodiments of the present invention.Referring to Fig. 6, in the present invention, if consider the requirement of code rate, continuous 4 the significant bit data of output are realized in the back that guarantees to interweave for the second time, and so, referring to Fig. 2, the present invention may further include following steps in above-mentioned steps 503:
Step 601: the dateout processing unit receives reads 4 Bit datas that control unit takes out, judge in these 4 Bit datas and whether do not comprise invalid 2 Bit datas, if do not comprise, then execution in step 602, if comprise two invalid 2 Bit datas, then execution in step 603, if only comprise invalid 2 Bit datas, then execution in step 604.
Step 602: the dateout processing unit is directly exported 4 Bit datas that read, and finishes current flow process.
Step 603: the dateout processing unit directly abandons 4 Bit datas that read, and finishes current flow process.
Step 604: the dateout processing unit abandons one of them invalid 2 Bit data in 4 Bit datas that read.
Step 605: the dateout processing unit is judged the current 2 bit valid data of buffer memory before that whether exist, if then execution in step 606, otherwise, execution in step 607.
Step 606: the dateout processing unit will before the valid data of 2 bits in 2 bit valid data and current 4 Bit datas that read of buffer memory piece together the position and become one 4 bit valid data, and export, finish current flow process.
Step 607: dateout processing unit buffer memory reads 2 bit valid data in 4 Bit datas.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1, a kind of realization interweaving method second time, it is characterized in that, this method realizes based on a kind of random access memory RAM and a kind of shift register, wherein, the width of RAM requires continuously the bit number of the valid data of output to determine that its degree of depth is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; The bit wide of shift register is the number of bits corresponding to a write operation process object, and this method also comprises:
A, with R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix;
B, the data corresponding to a write operation process object in the shift register are interweaved;
C, the data corresponding to a write operation process object after will interweaving write among the RAM in the current lowest address that does not write data;
D, repeated execution of steps A be to step C, until with R
2* C
2All data all write among the RAM in the orthogonal matrix;
E, the mode that from the minimum to the maximum, reads successively according to address among the RAM, once read the data in address of RAM, require the number of the significant bit data of output continuously according to the back that interweaves for the second time, from all data that once read, take out the output of significant bit data, repeat this step, all data in output RAM.
2, method according to claim 1 is characterized in that, it is 4 that the back that interweaves the described second time requires the bit number of the valid data of continuous output;
The width of described RAM is 120 bits;
The bit wide of described shift register is 120 bits;
Described untreated data corresponding to a write operation process object are: R
2* C
2Current untreated preceding two line data in the orthogonal matrix.
3, method according to claim 2 is characterized in that, described step B comprises: according to displacement patterns between row, preceding 30 symbol datas and back 30 symbol datas interweave respectively in the shift register to described 120 bit bit wides;
In step C, the data corresponding to a write operation process object after described will interweaving write that the step in the current lowest address that does not write data comprises among the RAM: first symbol data after first symbol data after at first described preceding 30 symbol datas being interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, then, second symbol data after second symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively, the rest may be inferred, and last symbol data after last symbol data after described preceding 30 symbol datas are interweaved and described back 30 symbol datas interweave writes among the RAM in the current lowest address that does not write data successively.
4, method according to claim 1 is characterized in that, it is 2 that the back that interweaves the described second time requires the bit number of the valid data of continuous output;
The width of described RAM is 60 bits;
The bit wide of described shift register is 60 bits;
Described untreated data corresponding to a write operation process object are: R
2* C
2Current untreated first line data in the orthogonal matrix.
5, according to any described method in the claim 1 to 4, it is characterized in that the number of described shift register is 2;
In steps A, described shift register is the shift register that was not written into last time corresponding to write operation process object data.
6, method according to claim 1 is characterized in that, in steps A, before execution writes data in the shift register, further comprises: described shift register is initialized as invalid 2 Bit datas.
7, method according to claim 6 is characterized in that, it is 4 that the back that interweaves the described second time requires the bit number of the valid data of continuous output;
In step e, described step of taking out data and output from all data that once read comprises:
E11, from all data that once read, take out preceding 4 Bit datas;
E12, judge in 4 Bit datas being got whether do not comprise invalid 2 Bit datas, if do not comprise, execution in step E13 then, if comprise two invalid 2 Bit datas, execution in step E14 then is if only comprise invalid 2 Bit data, then an execution in step E15;
E13, directly export this 4 Bit datas, finish current flow process;
E14, directly abandon this 4 Bit datas, finish current flow process;
E15, in 4 Bit datas that read, abandon one of them invalid 2 Bit data;
E16, judge 2 bit valid data of buffer memory before current whether the existence, if exist, then will before the valid data of 2 bits in 2 bit valid data and current 4 Bit datas that read of buffer memory piece together and export after becoming one 4 bit valid data, if there is no, then buffer memory reads 2 bit valid data in 4 Bit datas.
8, method according to claim 6 is characterized in that, it is 2 that the back that interweaves the described second time requires the bit number of the valid data of continuous output;
In step e, described step of taking out data and output from all data that once read comprises:
E21, from all data that once read, take out preceding 2 Bit datas;
E22, judge whether 2 Bit datas being got are invalid 2 Bit datas, if, execution in step E23 then, otherwise, execution in step E24;
E23, directly abandon the data of being taken out, finish current flow process;
The data that E24, direct output are taken out.
9, a kind of system that realizes that interweave with the second time, it is characterized in that, this system comprises: write control unit, RAM and read control unit, write and comprise the shift register subelement in the control unit and write the processing subelement, comprise at least one shift register in the shift register subelement, wherein, the width of RAM requires continuously the bit number of the valid data of output to determine that its degree of depth is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time; The bit wide of shift register is the number of bits corresponding to a write operation process object, and,
Write the processing subelement, be used for R
2* C
2Untreated data corresponding to a write operation process object write in the shift register in the orthogonal matrix, and to after interweaving corresponding to the data of a write operation process object in the shift register, write among the RAM in the current lowest address that does not write data;
Any one shift register is used to receive the data corresponding to a write operation process object;
RAM is used for storing writing and handles the data that each address write of subelement at self;
Read control unit, be used for the mode that from the minimum to the maximum, reads successively according to the RAM address, once read all data in address of RAM, and require the bit number of output continuously, in all data that read, take out data according to the back that interweaves for the second time.
10, system according to claim 9 is characterized in that, comprises two shift registers in the described shift register subelement; These two shift registers are carried out the data that receive corresponding to a write operation process object in turn.
11, system according to claim 9 is characterized in that, the described processing unit of writing is further used for the shift register in the shift register subelement is initialized as invalid 2 Bit datas.
12, system according to claim 11, it is characterized in that, this system further comprises: the dateout processing unit, be used to receive and read the data that control unit takes out, and abandon invalid 2 Bit datas in the received data, require the valid data bit number of output continuously according to the back that interweaves for the second time, export received data.
13, system according to claim 12 is characterized in that, describedly reads control unit takes out preceding 4 bits in all data that read data;
Described dateout processing unit, be used for determining whether 4 received Bit datas do not comprise invalid 2 Bit datas, if do not comprise invalid 2 Bit datas, then directly export this 4 Bit datas, if comprise two invalid 2 Bit datas, then directly abandon this 4 Bit datas, if only comprise invalid 2 Bit datas, then in 4 Bit datas that read, abandon one of them invalid 2 Bit data and judge the current 2 bit valid data of buffer memory before that whether exist, if exist, then will before the valid data of 2 bits in 2 bit valid data and current 4 Bit datas that read of buffer memory piece together and export after becoming one 4 bit valid data, if there is no, then buffer memory reads 2 bit valid data in 4 Bit datas.
14, system according to claim 12 is characterized in that, describedly reads control unit takes out preceding 2 bits in all data that read data;
Described dateout processing unit is used for determining whether 2 received Bit datas are invalid 2 Bit datas, if, then directly abandon this 2 Bit datas, otherwise, this 2 Bit datas directly exported.
15, a kind of RAM, it is characterized in that, this RAM is used for storing writing and handles the data that each address write of subelement at self, and, the width of this RAM requires continuously the bit number of the valid data of output to determine that the degree of depth of this RAM is the width of physical channel maximum data bearing capacity divided by this RAM according to the back that interweaves for the second time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100663927A CN100488058C (en) | 2006-04-05 | 2006-04-05 | Method and system for realizing the second intersection and random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100663927A CN100488058C (en) | 2006-04-05 | 2006-04-05 | Method and system for realizing the second intersection and random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1983824A true CN1983824A (en) | 2007-06-20 |
| CN100488058C CN100488058C (en) | 2009-05-13 |
Family
ID=38166116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100663927A Expired - Fee Related CN100488058C (en) | 2006-04-05 | 2006-04-05 | Method and system for realizing the second intersection and random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100488058C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009152770A1 (en) * | 2008-06-17 | 2009-12-23 | 中兴通讯股份有限公司 | Method and apparatus for implementing interleaving and de-interleaving at second time |
| CN101420233B (en) * | 2008-12-17 | 2011-07-20 | 航天恒星科技有限公司 | Bit interleaver and interleaving method |
| CN101188429B (en) * | 2007-12-24 | 2011-11-16 | 北京创毅视讯科技有限公司 | A bit interleaver and method for bit interleaving |
| CN110704018A (en) * | 2019-08-26 | 2020-01-17 | 深圳芯英科技有限公司 | Data buffer and data processing method |
| CN112416260A (en) * | 2020-12-03 | 2021-02-26 | 海光信息技术股份有限公司 | Data processing method and data processing device |
-
2006
- 2006-04-05 CN CNB2006100663927A patent/CN100488058C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188429B (en) * | 2007-12-24 | 2011-11-16 | 北京创毅视讯科技有限公司 | A bit interleaver and method for bit interleaving |
| WO2009152770A1 (en) * | 2008-06-17 | 2009-12-23 | 中兴通讯股份有限公司 | Method and apparatus for implementing interleaving and de-interleaving at second time |
| US8364916B2 (en) | 2008-06-17 | 2013-01-29 | Zte Corporation | Method and apparatus for implementing interleaving and de-interleaving at second time |
| CN101420233B (en) * | 2008-12-17 | 2011-07-20 | 航天恒星科技有限公司 | Bit interleaver and interleaving method |
| CN110704018A (en) * | 2019-08-26 | 2020-01-17 | 深圳芯英科技有限公司 | Data buffer and data processing method |
| CN112416260A (en) * | 2020-12-03 | 2021-02-26 | 海光信息技术股份有限公司 | Data processing method and data processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100488058C (en) | 2009-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100488058C (en) | Method and system for realizing the second intersection and random access memory | |
| US5001753A (en) | Crytographic system and process and its application | |
| CN100568745C (en) | Interleaver in the communication system and deinterleaving method | |
| CN101510781B (en) | Method and device for filling dummy argument for interlace and de-interlace process as well as processing system | |
| EP1330040B1 (en) | Interleaving apparatus and method for a communication system | |
| CN102833040B (en) | Decoding processing method, device and coding/decoding system | |
| CN101079641B (en) | 2-dimensional interleaving apparatus and method | |
| CN101540654A (en) | Method for interlacing rate matching and de-interlacing off-rate matching | |
| CN101547064B (en) | Interleaving and rate matching and de-interleaving and rate de-matching methods | |
| CN109889205B (en) | Coding method and system, decoding method and system, coding and decoding method and system | |
| CN101986584A (en) | Rate de-matching device and method in 3GPP LTE | |
| CN101556560A (en) | Storage device, controller and data access method thereof | |
| CN101777921A (en) | Structured LDPC code decoding method and device for system on explicit memory chip | |
| CN101667843A (en) | Methods and devices for compressing and uncompressing data of embedded system | |
| KR19990033431A (en) | Channel Coder Design Method Using Parallel Convolutional Coder | |
| CN102077470B (en) | Method and device for encoding by linear block code, and method and device for generating linear block code | |
| CN100508405C (en) | Parallel decoding method and device for raising Turbo decoding speed | |
| CN101515839A (en) | Method, device and system for outputting codes | |
| MXPA03002200A (en) | Third generation fdd modem interleaver. | |
| CN102201817B (en) | Low-power-consumption LDPC decoder based on optimization of memory folding architecture | |
| CN100493000C (en) | Method and device for realizing multiple logic path counting | |
| WO2022089429A1 (en) | Decoding method and apparatus | |
| CN102118219B (en) | Serial processing method and serial processing device for rate matching | |
| CN111817724B (en) | Data compression circuit | |
| CN111900999B (en) | High-performance polarization coding method and coder for satellite discontinuous communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090513 Termination date: 20150405 |
|
| EXPY | Termination of patent right or utility model |