CN1983552A - 双镶嵌工艺 - Google Patents
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Abstract
本发明提供了一种应用三层阻抗的部分接触孔优先(partial－via－first)的双镶嵌工艺。首先形成第一接触孔，该第一接触孔穿过介电层的部分厚度，然后在介电层上形成三层阻抗结构，其中三层阻抗的底层填满第一接触孔。进行干式显影工艺去除顶层，使顶层的开口转移至中间层及底层，同时移除第一接触孔的底层以露出第一接触孔。之后进行干式蚀刻工艺以在第一接触孔下形成第二接触孔，并在第二接触孔上形成沟槽。最后进行湿式剥除工艺去除残留的光刻胶层。
Description
技术领域
本发明涉及一种双镶嵌结构工艺，特别是涉及一种应用三层阻抗的部分接触孔优先的双镶嵌结构工艺。
背景技术
双镶嵌内连线可提供平坦化的结构，特别是多层内连线结构，这可增加元件的密度及层数。半导体业界应用低介电常数(low-k)材料是一股趋势，特别是当铜导线结合低介电常数材料后可有效降低电阻电容(RC)延迟的现象。但某些孔洞状的低介电常数材料在蚀刻过程中，特别是在双镶嵌结构的工艺难以控制。
双镶嵌工艺包括“接触孔优先”(via-first)或“沟槽优先”(trench-first)。前者为先图案化绝缘层，形成的接触孔穿过绝缘层所有的厚度后，再图案化绝缘层上半部以形成沟槽。后者为先图案化绝缘层上半部以形成沟槽，之后再形成穿过绝缘层的接触孔。在微影工艺中需要将光刻胶曝光以界定双镶嵌结构的沟槽及接触孔。然而在全接触孔(full-via-fist)优先工艺中，前一步蚀刻产生的胺类化合物将污染光刻胶并产生光刻胶毒化问题。以三层阻抗(tri-layer resists)可排除光刻胶毒化的问题，但仍有光刻胶灰化损伤、涂布微负载效应(coating micro-loading)以及接触孔内的湿式剥除能力等问题。在沟槽优先工艺中，可应用金属掩模来避免剥除光刻胶时的等离子体损伤。但此种作法将造成接触孔偏移以及金属化聚合物难以移除等缺点。
如上所述，双镶嵌结构需要新的工艺来克服上述问题，在不增加工艺及成本的情况下，结合三层阻抗及掩模使接触孔的湿式剥除窗步骤具有较宽裕的操作容忍度。
发明内容
本发明的目的是提供一种应用三层阻抗的双镶嵌工艺，其可避免灰化损伤，并改善接触孔及沟槽的关键尺寸，且在不增加工艺及成本的情况下可使接触孔的湿式剥除步骤具有较宽裕的操作容忍度。
为实现上述目的，本发明提供了一种双镶嵌工艺，包括在半导体基板上形成介电层；形成第一接触孔，穿过介电层的部分厚度；在介电层上形成三层阻抗结构，其中三层阻抗结构包括覆盖介电层并填满接触孔的底层、覆盖底层的中间层以及覆盖中间层并具有一开口的顶层；进行干式显影工艺去除顶层，并使开口转移至中间层及底层，同时移除第一接触孔的底层以露出第一接触孔；进行干式蚀刻工艺去除中间层及部分的介电层，在第一接触孔下形成第二接触孔，并在第二接触孔上形成沟槽；以及进行湿式剥除工艺去除底层。
为实现上述目的，本发明还提供了另一种双镶嵌工艺，包括：提供半导体基板，其具有导电区域；在半导体基板上形成蚀刻停止层；在蚀刻停止层上形成介电层，其中介电层具有第一接触孔，第一接触孔的厚度小于介电层的厚度的一半；在介电层上形成底光刻胶层，其中底光刻胶层填满第一接触孔形成插塞；在底光刻胶层上形成抗反射涂布层；在抗反射涂布层上形成顶光刻胶层，其中顶光刻胶层具有在第一接触孔上的开口；进行干式显影工艺去除顶光刻胶层，使开口转移至抗反射层及底光刻胶层，并移除插塞的底光刻胶层以露出第一接触孔；进行干式蚀刻工艺移除抗反射层及部分的介电层，在第一接触孔下形成第二接触孔，并在第二接触孔上形成沟槽，其中第二接触孔露出部分的导电区域；以及进行湿式剥除工艺去除残余的底光刻胶层。
本发明具有下列优点：首先，应用三层阻抗的部分接触孔优先的工艺可控制沟槽的关键尺寸与深度负载，并减少光刻胶涂布的微负载效应，这将有助于缩小接触孔及沟槽的关键尺寸。其次，利用三层阻抗结构界定沟槽的关键尺寸、清除插塞以及移除顶层光刻胶的显影工艺可得到非毒化的接触孔、湿式剥除窗步骤具有较宽裕的操作容忍度以及减少清洁步骤间平均时间内的风险(mean-time-between-clean，MTBC)。此外，在干式显影中去除光刻胶可避免光刻胶灰化的损伤。第三，干蚀刻工艺原位界定的接触孔及沟槽，可使沟槽具有实质上平滑垂直的侧壁，并使边角自然圆化。第四，与公知全接触孔优先的双镶嵌工艺与金属掩模工艺相比较，本发明的部分接触孔优先的双镶嵌工艺较简单，不需额外的工艺或成本。
附图说明
图1-图5分别为本发明实施例的剖面图，用以说明本发明的应用三层阻抗的部分接触孔优先的双镶嵌工艺。
其中，附图标记说明如下：
10～基板 12～导电区 14～蚀刻停止层
16～层间介电层 18～盖层 20～初始接触孔
20a～最终接触孔 21～插塞 22～底层
24～中间层 26～顶层 27～开口
28～沟槽 29～侧壁
具体实施方式
本发明提供了一种双镶嵌工艺，其可克服公知技术在应用三层阻抗及金属掩模等工艺时存在的问题。特别是本发明应用了三层阻抗的部分接触孔优先的双镶嵌工艺，可避免灰化损伤及改善沟槽及接触孔的关键尺寸，且在不增加工艺及成本的情况下可使接触孔的湿式剥除步骤具有较宽裕的操作容忍度。与公知的“全接触孔优先”工艺相较，“部分接触孔优先”指的是一开始形成的接触孔只穿过介电层的部分厚度，之后才在介电层下半部形成接触孔，及在介电层上半部形成沟槽。
下述说明中，尽量使用同样的符号描述同样的部位。为清楚起见，图中元件构造的形状比例可能用夸张方式表现。下述说明将着重于形成元件的步骤，以及本发明完成的装置。此外，当某一层于另一层上或下时，指的可能是某一层紧邻另一层，或两层之间具有其它层。
如图1所示，制造内连线所用的基板上已形成集成电路，x这些集成电路可形成于该基板上和/或该基板中。半导体基板可包括基体硅、半导体晶片、绝缘层上硅基板或硅锗基板。集成电路的电路元件包括晶体管、二极管、电阻、电容、电感或其它有源或无源元件。基板10包含导电区域12，若需要可由化学机械研磨(以下简称CMP)使导电区域12暴露的上表面平坦化。适合作为导电区域12的材料包括但不限定于：铜、铝、铜为主的合金或其它导电材料。
首先，在基板10上沉积约10-1000埃的蚀刻停止层14。蚀刻停止层的材料可为氧化硅、氮化硅、碳化硅、氮氧化硅或上述的组合。沉积方法较佳为低压化学气相沉积(以下简称LPCVD)、常压化学气相沉积(以下简称APCVD)、等离子体辅助化学气相沉积(以下简称PECVD)、物理气相沉积(以下简称PVD)、溅镀或其它未来发展的沉积方法。
在蚀刻停止层14上形成厚度约500到30000埃的层间介电层16。形成方法可包括旋转涂布法、化学气相沉积(以下简称CVD)或其它未来发展的沉积方法。层间介电层16可为单层结构或多层结构，其材料为介电常数低于3.9的低介电常数材料，例如介电常数为3.5或3.0，甚至可以更低。本发明应用的低介电常数材料可为：旋转涂布的无机介电材料、旋转涂布的有机介电材料、孔洞介电材料、有机聚合物、有机硅玻璃、氟硅玻璃、类钻碳、氢化倍半硅氧烷(HSQ)及其衍生物、甲基倍半硅氧烷(MSQ)及其衍生物、孔洞有机系列材料、聚亚酰胺、聚倍半硅氧烷、聚芳醚、Dow Corning公司所售的SiLK、Allied Signal公司所售的FLARE或其它低介电常数材料。
之后可视情况在层间介电层16上沉积一层厚度约为50到2000埃的盖层18，此盖层18可释放层间介电层16的应力。盖层18可为四乙氧基硅烷(TEOS)为主的氧化物、无机氧化物、氮化硅、氮氧化硅或碳化硅。沉积方法包括LPCVD、APCVD、PECVD、PVD、溅镀或其它未来发展的沉积方法。
如图1所示，以一般的微影与非等向性蚀刻工艺，形成至少一初始接触孔20，使其穿过盖层18及层间介电层16的部分厚度。接着以湿式剥除工艺去除微影工艺所用的光刻胶，并可增加湿式清洗工艺以确保无任何光刻胶残留在盖层18及/或层间介电层16上。初始接触孔的深度小于层间介电层一半厚度，较佳的深度介于该层间介电层厚度的1/4至1/2之间，且不露出蚀刻停止层14及导电区域12。虽然图1的初始接触孔不只一个，但本发明的工艺也可应用于单一初始接触孔的双镶嵌工艺。
如图2所示，在基板10上形成三层阻抗的复合式阻抗层。三层阻抗结构包括：一底层22，覆盖层间介电层16并填满初始接触孔20而形成插塞21；一中间层24，覆盖在底层22上；以及具有开口27的顶层26，覆盖在中间层24上。
底层22为厚度介于50到20000埃的薄膜，可用旋转涂布后烘烤形成。底层22包含极性成分如具有羟基或酚基的聚合物，可与位于其下的介电材料扩散出来的胺类化合物或含氮化合物键结或相吸。在一实施例中，底层22为I线光刻胶如酚醛型环氧树脂(Novolac resin)，其形成方式为将甲酚(cresol)、二甲酚(xylenol)或其它取代的酚类，与甲醛反应得到。I线光刻胶可有效防止当其上的光刻胶图案化时，底下的胺类化合物(如氨)往上扩散造成毒化。此外，底层22可为深紫外线光刻胶，通常是具有羟基苯乙烯基团的聚合物。底层22可为正光刻胶或负光刻胶，可使用生产线已有的材料以避免提高成本。
中间层24的厚度约为300埃到1000埃，同样可用旋转涂布后烘烤形成。中间层24包括一抗反射薄膜，中间层24的作用为抗反射层，避免其上的光刻胶在进行微影工艺的曝光时，光线影响其下的光刻胶。中间层24的材料选择有几个条件：不溶于后续旋转涂布工艺所用的有机溶剂，并可减少光反射以避免影响其上光刻胶的曝光工艺。举例来说，中间层24包括负型有机抗反射层、负型染料阻抗层、深紫外线抗反射层或193纳米的抗反射层。
顶层26的材料选择要视沟槽尺寸而定。当沟槽尺寸介于130纳米至250纳米时，顶层较佳为深紫外线光刻胶。当沟槽尺寸介于100纳米至130纳米时，顶层较佳为193纳米的光刻胶。较佳的顶层26厚度约介于2000埃到8000埃，也取决于沟槽的尺寸。顶层26可为正光刻胶或负光刻胶，曝光后可溶于碱性显影液以形成开口27。开口27的位置及方向对应于初始接触孔20。
如图3所示，进行干式显影工艺使开口27转移至中间层24及底层22，同时移除初始接触孔20的底层22以露出初始接触孔20。由于此步骤可同时移除顶层26并省略光刻胶灰化工艺，因此可避免公知技术的干式灰化损伤。
接着如图4所示，在同一腔室中以四氟化碳、氩气以及氧气进行干式蚀刻工艺，去除初始接触孔20下的层间介电层16及蚀刻停止层14，形成最终接触孔20a并露出导电区域12。同时原位横向蚀刻初始接触孔20周围的盖层18及层间介电层16，以在最终接触孔20a上形成沟槽28。一般在干式蚀刻盖层18及层间介电层16时，会消耗部分的中间层24及底层22，甚至完全去除中间层24。如此一来，就在层间介电层16的上半部形成沟槽28，并在层间介电层16的下半部形成接触孔20a，两者构成了双镶嵌结构。特别的是，沟槽28具有平滑垂直的侧壁29。最后图5所示，以湿式剥除工艺去除残留在盖层18上的底层22，使用的溶液例如是硫酸与双氧水的混合液，或硫酸与硝酸的混合液。再次强调虽然附图中有多个最终接触孔，但本发明也可应用于单一接触孔的双镶嵌工艺。
如上所述，本发明具有下列优点。首先，应用三层阻抗的部分接触孔优先的工艺可控制沟槽的关键尺寸与深度负载，并减少光刻胶涂布的微负载效应，这将有助于缩小接触孔及沟槽的关键尺寸。其次，利用三层阻抗结构界定沟槽的关键尺寸、清除插塞以及移除顶层光刻胶的显影工艺可得到非毒化的接触孔、湿式剥除窗步骤具有较宽裕的操作容忍度以及减少清洁步骤间平均时间内的风险(mean-time-between-clean，MTBC)。此外，在干式显影中去除光刻胶可避免光刻胶灰化的损伤。第三，干蚀刻工艺原位界定的接触孔及沟槽，可使沟槽具有实质上平滑垂直的侧壁，并使边角自然圆化。第四，与公知全接触孔优先的双镶嵌工艺与金属掩模工艺相比较，本发明的部分接触孔优先的双镶嵌工艺较简单，不需额外的工艺或成本。
Claims (14)
1.一种双镶嵌工艺，包括：
在一半导体基板上形成一介电层；
形成一第一接触孔，该第一接触孔穿过该介电层的部分厚度；
在该介电层上形成三层阻抗结构，该三层阻抗结构包括覆盖该介电层并填满该第一接触孔的一底层、覆盖该底层的一中间层以及覆盖该中间层并具有一开口的一顶层；
进行一干式显影工艺去除该顶层，并使该开口转移至该中间层及该底层，同时去除该第一接触孔的该底层以露出该第一接触孔；
进行一干式蚀刻工艺去除该中间层及部分的该介电层，在该第一接触孔下形成一第二接触孔，并在该第二接触孔上形成一沟槽；以及
进行一湿式剥除工艺去除该底层。
2.如权利要求1所述的双镶嵌工艺，其中该第一接触孔的深度小于该介电层的厚度的一半。
3.如权利要求1所述的双镶嵌工艺，其中该底层包括一I-线光刻胶。
4.如权利要求1所述的双镶嵌工艺，其中该中间层包括一抗反射薄膜。
5.如权利要求1所述的双镶嵌工艺，其中该顶层包括一光刻胶。
6.如权利要求1所述的双镶嵌工艺，其中该干式蚀刻工艺去除该第一接触孔底部的该介电层以形成该第二接触孔，以及去除该开口与该第一接触孔间的该介电层以形成该沟槽。
7.如权利要求1所述的双镶嵌工艺，其中该介电层的介电常数小于3.9。
8.如权利要求1所述的双镶嵌工艺，其中该双镶嵌工艺还包括在该半导体基板与该介电层之间形成一蚀刻停止层，其中该第二接触孔穿过该介电层及该蚀刻停止层。
9.如权利要求8所述的双镶嵌工艺，其中该蚀刻停止层包括氮化硅、氮氧化硅、碳化硅、或氮化硅、氮氧化硅、碳化硅的组合。
10.如权利要求1所述的双镶嵌工艺，该双镶嵌工艺还包括在形成该第一接触孔前，在该介电层上形成一盖层，其中该第一接触孔穿过该盖层及部分的该介电层。
11.如权利要求10所述的双镶嵌工艺，其中该盖层包括以四乙氧基硅烷为主的氧化物。
12.如权利要求1所述的双镶嵌工艺，其中该半导体基板包括一导电区域，且该第二接触孔露出部分的该导电区域。
13.如权利要求12所述的双镶嵌工艺，其中该导电区域包括铜或以铜为主的合金。
14.如权利要求1所述的双镶嵌工艺，其中该干式蚀刻工艺形成的该沟槽具有实质上垂直的侧壁。
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| US11/301,917 | 2005-12-13 |
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| CN101587854B (zh) * | 2008-05-20 | 2011-02-02 | 中芯国际集成电路制造(上海)有限公司 | 过孔和金属沟槽的制作方法 |
| CN101587852B (zh) * | 2008-05-20 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 一种优化金属沟槽制作的方法 |
| CN101740475B (zh) * | 2008-11-11 | 2012-04-18 | 中芯国际集成电路制造(北京)有限公司 | 具有双镶嵌结构的半导体器件及其形成方法 |
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| CN101958275B (zh) * | 2009-07-16 | 2012-11-14 | 中芯国际集成电路制造(上海)有限公司 | 接触孔形成方法 |
| CN110707061A (zh) * | 2019-09-06 | 2020-01-17 | 上海集成电路研发中心有限公司 | 一种红外探测器接触孔结构及其制作方法 |
| CN110707061B (zh) * | 2019-09-06 | 2021-09-14 | 上海集成电路研发中心有限公司 | 一种红外探测器接触孔结构及其制作方法 |
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| Publication number | Publication date |
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| US20070134917A1 (en) | 2007-06-14 |
| TWI305028B (en) | 2009-01-01 |
| CN100419995C (zh) | 2008-09-17 |
| TW200723447A (en) | 2007-06-16 |
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