CN1956216A - Semiconductor structure and method of forming the same - Google Patents
Semiconductor structure and method of forming the same Download PDFInfo
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- CN1956216A CN1956216A CNA2006100735022A CN200610073502A CN1956216A CN 1956216 A CN1956216 A CN 1956216A CN A2006100735022 A CNA2006100735022 A CN A2006100735022A CN 200610073502 A CN200610073502 A CN 200610073502A CN 1956216 A CN1956216 A CN 1956216A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
Abstract
A semiconductor structure includes a semiconductor substrate having a first device area and a second device area. A gate layer is formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer running across the first device area is doped with impurities of a type different from that of a second portion of the gate layer running across the second device area. A cap layer is formed on the gate layer for protecting the same covered thereunder from forming a silicide structure, having at least one opening at a junction of the first and second portions of the gate layer. A silicide layer is formed on the gate layer that is exposed by the opening for reducing resistance at the junction between the first and second portions.
Description
Technical field
The present invention is relevant for a kind of integrated circuit (IC) design, particularly relevant for a kind of when the self-aligned metal silicide contact zone that is applicable to static random access memory (sram) cell is provided, in order to reduce the semiconductor framework of resistance.
Background technology
When semiconductor technology progress during to the deep-sub-micrometer field, integrated circuit (integrated circuit, IC) semiconductor framework in the chip become more crowded.For example, (staticrandom access memory, SRAM) unit is more and more intensive, so that form the difficulty more that all necessary circuit become in sram chip owing to static RAM.Interior frame linking structure from a metal internal connecting line layer to another metal internal connecting line layer, and to metal-oxide semiconductor (MOS) (metal-oxide semiconductor, MOS) transistorized source/drain, grid and main body all need vertical conduction interlayer hole (via).In dual damascene (dual damascene) metallization (metallization), etching interlayer hole and groove are filled up with metal (being generally copper), the part of protruding is by for example cmp (chemical-mechanical-polish, CMP) technology and grind and remove.The interlayer hole that fills up metal provides vertical connection, and the groove that fills up metal provides horizontal joint sheet and lead.
Interlayer hole is normally carried out the minimal characteristic (feature) of development and the required resolution of etching.The interlayer hole that fills up metal that extends downward the contact zone of effective semiconductor substrate from the first metal layer must be enough little, just is unlikely to make any other substrate, polysilicon (polycrystalline silicon) lead, grid or other interlayer hole to cause electrical short circuit.
Usually use two kinds of frameworks to form the interlayer hole that extends downward the contact zone.First kind of framework is the metal silicide layer (silicide) that is formed at the polysilicon gate top, in order to the ohmic contact between polysilicon gate and the interlayer hole (Ohm contact) to be provided.Second kind of framework is self-aligned contact zone (self-alignment contact).Herein, coating layer (cap layer) is formed at the upper surface of polysilicon gate.Coating layer combines with the clearance wall that is arranged at the polysilicon gate side and each side of polysilicon gate can be isolated fully.Metal level is formed at the source/drain regions of semiconductor substrate.With semiconductor substrate heating to form metal silicide layer in metal level and as the interface of the source/drain regions of self-aligned contact zone.Because the cause of coating layer can be avoided forming metal silicide during the Technology for Heating Processing on polysilicon gate.
Above-mentioned two kinds of frameworks are mutual exclusion.When using the self-aligned contact zone, the coating layer that is arranged at the polysilicon gate top is formed on the polysilicon gate in order to avoid metal silicide.Therefore, for suitable circuit running, the resistance value of polysilicon gate can be too high.
Summary of the invention
In view of this, the invention provides a kind of semiconductor framework.Semiconductor framework comprises the semiconductor-based end with the first device district and second device district.Be across the grid layer in the suprabasil first device district of semiconductor and the second device district, carry out with impurity across first one of the grid layer in the first device district and to mix with first kenel, and be across second one of grid layer of the second device district with the impurity execution doping with second kenel.The coating layer that is arranged at grid layer top is in order to avoiding forming metal suicide structure in the grid layer top that is covered by coating layer, and has at least one opening in first face that connects place with second one of grid layer.Be arranged at the metal silicified layer of grid layer top, expose metal silicified layer, to reduce the resistance of the face that connects between first one and second one between grid layer by opening.
According to described semiconductor framework, wherein above-mentioned coating layer also comprises: by at least one sublevel that different materials constituted; Wherein above-mentioned coating layer comprises and is selected from material: silicon oxynitride, tantalum oxide, aluminium oxide, hafnium oxide, silica, silicon nitride, polyethylene glycol oxide, tetraethoxysilane, nitrogen-containing oxide, nitrogen oxide, contain hafnium oxide, contain tantalum pentoxide or contain at least a in the aluminum oxide; Wherein above-mentioned metal silicified layer comprises and is selected from material: at least a in refractory metal, metal nitride, titanium, titanium disilicide, cobalt, cobalt disilicide, nickel, nickle silicide, titanium nitride, titanium tungsten or the tantalum nitride.
According to described semiconductor framework, wherein above-mentioned is substantially by first sublevel that silica constituted by at least one sublevel that different materials constituted, and substantially by second sublevel that silicon nitride constituted.
According to described semiconductor framework, also comprise being arranged at suprabasil at least one isolated area of above-mentioned semiconductor, in order to define the above-mentioned first device district and the second device district.
According to described semiconductor framework, also comprise the first group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned first device district, and the second group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned second device district.
According to described semiconductor framework, also comprise at least one self-aligned metal silicide contact zone, be arranged at the top of above-mentioned first group of source/drain doping region and above-mentioned second group of source/drain doping region.
According to described semiconductor framework, also comprise being arranged at above-mentioned grid layer and the gate dielectric at the above-mentioned semiconductor-based end, in order to the above-mentioned grid layer and the above-mentioned semiconductor-based end are isolated.
According to described semiconductor framework, also comprise at least one clearance wall, be arranged at the sidewall of above-mentioned grid layer.
The present invention also provides a kind of semiconductor framework formation method, is applicable to semiconductor framework, comprising: the semiconductor-based end with the first device district and second device district is provided; Formation is across the grid layer in the suprabasil above-mentioned first device district of above-mentioned semiconductor and the second device district, wherein install the impurity of first first kenel of mixing of the grid layer of distinguishing, install the impurity of second doping second kenel of the grid layer of distinguishing across above-mentioned second across above-mentioned first; Form coating layer in above-mentioned grid layer top; First of above-mentioned grid layer face that connects with second one forms at least one opening in above-mentioned coating layer; And in the above-mentioned opening of above-mentioned grid layer, form metal silicified layer.
According to described semiconductor framework formation method, wherein form above-mentioned batch of step of cladding in above-mentioned grid layer top and also comprise: the top in above-mentioned grid layer forms first sublevel with first material; And second sublevel that has second material in the formation of the top of above-mentioned first sublevel.
According to described semiconductor framework formation method, above-mentioned coating layer comprises and is selected from material: silicon oxynitride, tantalum oxide, aluminium oxide, hafnium oxide, silica, silicon nitride, polyethylene glycol oxide, tetraethoxysilane, nitrogen-containing oxide, nitrogen oxide, contain hafnium oxide, contain at least a in the tantalum pentoxide or have dielectric constant K greater than 5 high dielectric constant materials.
According to described semiconductor framework formation method, also comprise being arranged at suprabasil at least one isolated area of above-mentioned semiconductor, in order to define the above-mentioned first device district and the second device district.
According to described semiconductor framework formation method, also comprise the first group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned first device district, and the second group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned second device district.
According to described semiconductor framework formation method, the step that wherein in the above-mentioned opening of above-mentioned grid layer, forms above-mentioned metal silicified layer also comprise form be arranged at above-mentioned first group of source/drain doping region and above-mentioned second group of source/drain doping region above at least one self-aligned metal silicide contact zone.
Description of drawings
Fig. 1 shows the circuit diagram of traditional sram cell.
Fig. 2 and Fig. 3 show the IC layout according to the described SRAM memory cell of the embodiment of the invention.
Fig. 4 to Fig. 6 shows the profile according to described Fig. 2 of different embodiments of the invention and SRAM memory cell shown in Figure 3.
Wherein, description of reference numerals is as follows:
100～circuit Figure 102,104～reverser
106,108～memory node 110,112～conduction transistor
114,118～pull-up transistor 116,120～pulldown transistors
200,300～IC layout 202,204,206,208～lines
210～window 212,214,216,218,232,234～contact zone
236,238,240,242,244,246,250,254,258,262,406,506～contact zone
220,226,256,260,410,510～polysilicon gate
264,266～traverse 400,500,600～profile
302,304,306,308,310,312,314,316,318,320～joint sheet
402,502～metal level 404,504,606～interlayer hole
408,516～gate dielectric 412,512,602～coating layer
414,514,604～clearance wall, 416～source/drain region
612～opening, 613～isolated area
Vdd～voltage source WL～word line
BL～bit line BLB～antiposition line
Vss～complementary voltage source
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Embodiment:
Next will be provided at the detailed description that produces the framework of self-aligned metal silicide and self-aligned contact zone in the integrated artistic.
Circuit Figure 100 of Fig. 1 shows the standard sram cell with two cross-coupled (cross-coupled) reverser 102 and 104.Reverser 102 (reverser 1) comprises pull-up transistor 114 (PU-1) and pulldown transistors 116 (PD-1).Reverser 104 (reverser 2) comprises pull-up transistor 118 (PU-2) and pulldown transistors 120 (PD-2).The memory node 106 of reverser 102 is electrically connected to two transistorized grids of reverser 104.The memory node 108 of reverser 104 is electrically connected to two transistorized grids of reverser 102.Be coupled to the reading and writing of memory node 106 of the conduction transistor 110 may command reversers 102 of bit line BL by control.Be coupled to the reading and writing of memory node 108 of the conduction transistor 112 may command reversers 104 of antiposition line BLB (bit linebar) by control.Conduction transistor 110 and 112 is subjected to the control of common word line WL.The present invention elaborates by this sram cell.
The IC layout 200 of Fig. 2 shows the framework according to the sram cell of the described preparation deposition of embodiment of the invention the first metal layer.The part of being got up by lines 202,204,206 and 208 frames is defined as sram cell.Contact zone 212 and 218 is formed at the top of polysilicon gate 220, in order to control pull-up transistor 118 (PU-2) and pulldown transistors 120 (PD-2), the part coating layer (label in Fig. 4 and Fig. 5 is 412 and 512) that wherein is formed at polysilicon gate 220 tops is removed. Contact zone 214 and 216 is formed at the top of polysilicon gate 226, and in order to control pull-up transistor 114 (PU-1) and pulldown transistors 116 (PD-1), the part coating layer that wherein is formed at polysilicon gate 226 tops is removed.In window 210 inside, have the wellblock of the second polarity kenel and first part of polysilicon gate 220 and 226 and mix with impurity with first polarity kenel.In window 210 outsides, another wellblock, polysilicon gate 256 and 260 with first polarity kenel, and the second portion of polysilicon gate 220 and 226 mixes with the impurity with second polarity kenel, and wherein the second polarity kenel is different from the first polarity kenel.
With reference to Fig. 1 and Fig. 2, transistor 114 is P passage MOS transistor (being called PMOS again), has the source contact area 232 that is coupled to voltage source V CC, is coupled to the drain contact region 234 of memory node 106.Transistor 118 is the PMOS transistor, has the source contact area 236 that is coupled to VCC, is coupled to the drain contact region 238 of memory node 108.Transistor 116 is a nmos pass transistor, has the source contact area 240 that is coupled to complementary voltage source V SS, is coupled to the drain contact region 242 of memory node 106.The transistor 114 and 116 of reverser 1 has common polysilicon gate 226.Transistor 120 is a nmos pass transistor, has the source contact area 244 that is coupled to VSS, is coupled to the drain contact region 246 of memory node 108.The transistor 118 and 120 of reverser 2 has common polysilicon gate 220.
Logical grid (pass gate) transistors 110 (PG-1) are nmos pass transistor, has the source contact area 250 that is coupled to bit line BL (not icon), be coupled to the drain contact region 242 of memory node 106, drain contact region 242 is identical with the drain contact region of transistor 116.Pass transistor 112 (PG-2) is a nmos pass transistor, has the source contact area 254 that is coupled to antiposition line BLB (not icon), is coupled to the drain contact region 246 of memory node 108, and drain contact region 246 is identical with the drain contact region of transistor 120.
Polysilicon gate 256 in order to oxide-semiconductor control transistors 110 has the contact zone 258 that is coupled to word line WL (not icon).In ensuing paragraph, can the coating layer of 258 outsides, contact zone that are formed at polysilicon gate 256 tops be illustrated with reference to the diagram of Fig. 4 and Fig. 5.Polysilicon gate 260 in order to oxide-semiconductor control transistors 112 has the contact zone 262 that is coupled to word line WL (not icon).In ensuing paragraph, can the coating layer of 262 outsides, contact zone that are formed at polysilicon gate 260 tops be illustrated with reference to the diagram of Fig. 4 and Fig. 5.Traverse (cross section line) 264 passes through transistor 120 and 112.Traverse 266 passes through polysilicon gate 220.The explanation of ensuing paragraph is along the profile of the observed sram cell of lines 264.
The profile 400 of Fig. 4 shows according to the self-aligned metal silicide contact zone (silicide contact) on the described source/drain region that is formed at MOS transistor of the embodiment of the invention.The first metal layer 402 is coupled to self-aligned metal silicide contact zone 406 by interlayer hole 404.Gate dielectric 408 is covered by polysilicon gate 410.Coating layer 412 is formed at the top of polysilicon gate 410.Side wall spacer 414 is formed at the sidewall of polysilicon gate 410 and coating layer 412.By coating layer 412 and clearance wall 414 polysilicon gate 410 is isolated, to avoid during the formation of self-aligned metal silicide contact zone 406 source/drain region 416 formation the metal silicides above polysilicon gate 410.In addition, because the suitable alignment of interlayer hole 404, therefore the necessary technology " interlayer hole etching " during interlayer hole 404 forms can't make any one part of polysilicon gate 410 be damaged.
Coating layer 412 comprises and is selected from material: silicon oxynitride (SiON), tantalum oxide (Ta
2O
5), aluminium oxide (Al
2O
3), hafnium oxide (HfO), silica, silicon nitride, polyethylene glycol oxide (poly-ethyloxazoline, PEOX), tetraethoxysilane (tetra-ethylorthosilicate, TEOS), nitrogen-containing oxide, nitrogen oxide, contain hafnium (hafnium) oxide, contain tantalum (tantalum) oxide or contain at least a in the aluminum oxide.Coating layer 412 comprises by made at least one sublevel (sub-layer) of different materials.For example, coating layer 412 can comprise cardinal principle by the first made sublevel of silica, and substantially by the second made sublevel of silicon nitride.Self-aligned metal silicide contact zone 406 comprises and is selected from material: refractory metal (refractory metal), metal nitride, titanium (Ti), titanium disilicide (TiSi
2), cobalt (Co), cobalt disilicide (CoSi
2), at least a in nickel (Ni), nickle silicide (NiSi), titanium nitride (TiN), titanium tungsten (TiW) or the tantalum nitride (TaN).Gate dielectric 408 comprises with clearance wall 414 and is selected from material: silicon oxynitride, tantalum oxide, aluminium oxide, hafnium oxide, silica, silicon nitride, polyethylene glycol oxide, tetraethoxysilane, nitrogen-containing oxide, nitrogen oxide, contain hafnium oxide, contain tantalum pentoxide or contain at least a in the aluminum oxide.
The profile 500 of Fig. 5 shows according to the described self-aligned metal silicide contact zone that is arranged at the source/top, drain region of MOS transistor of the embodiment of the invention.The first metal layer 502 is coupled to self-aligned metal silicide contact zone 506 by interlayer hole 504.Gate dielectric 516 is covered by polysilicon gate 510.Coating layer 512 is formed at the top of polysilicon gate 510.Side wall spacer 514 is formed at the sidewall of polysilicon gate 510 and coating layer 512.By coating layer 512 and clearance wall 514 polysilicon gate 510 is isolated, to avoid during the formation of self-aligned metal silicide contact zone 506, above polysilicon gate 510, forming metal silicide.In addition, because interlayer hole 504 does not have suitable alignment, so interlayer hole etching meeting makes coating layer 512 and side wall spacer 514 cause damage.Yet, the destruction that etching caused be not very obviously.Enough coating layers 512 can avoid polysilicon gate 510 generations significantly etch-damaged with side wall spacer 514.
Fig. 6 shows according to the described profile 600 along the observed sram cell of lines 266 (being shown in Fig. 2) of the embodiment of the invention.With reference to Fig. 2, Fig. 3 and Fig. 6, at least one isolated area 613 is arranged at at semiconductor-based the end, to define many device districts.Coating layer 602 is formed at the top of polysilicon gate 220, and side wall spacer 604 is arranged at the edge of polysilicon gate 220.Electrically interconnect structure must penetrate interlayer hole 606 and metal silicide contact zone 212 downwards between the polysilicon gate 220 between the first metal layer joint sheet 302.Contact zone 212 is formed at the opening of coating layer 602.Same, first one of polysilicon gate 220 who is arranged at window 210 inside must be electrically coupled to second one that is arranged at window 210 outsides.First one carry out to be mixed with the impurity with opposed polarity with second one.Opening 612 is arranged at coating layer 602, therefore allows metal silicide contact zone 218 to be formed at opening 612 tops.Metal silicide contact zone 218 provides necessary electric connection between between polysilicon gate 220 first one and second one.Yet contact zone 218 does not have any interlayer hole, therefore can't any electrical contact be arranged with the first metal layer.Polysilicon gate 220 by its high-resistance relatively first one, low-resistance metal silicide contact zone 218 with and high-resistance relatively second one and with low-resistance contact zone 212 electrically continuously.
The invention provides and a kind ofly form the method and the framework of metal silicide contact zone with second one the face that connects in first one of polysilicon gate, wherein first one is mixed with the impurity with opposed polarity with second one, therefore can reduce the resistance between first one and second one.In addition, the invention provides a kind of integration method, make to be arranged in the metal silicide contact zone that meets the face place and the self-aligned contact zone that is arranged at source/drain region can be realized in the integrating semiconductor framework.
A kind of method in order to the semiconductor framework that forms above-mentioned proposition is described as follows.Semiconductor framework has the first device district and the second device district.On the semiconductor-based end, form at least one isolated area, in order to define the first device district and the second device district.Formation is across being arranged at the silicon gate layer of the suprabasil first device district of semiconductor with the second device district.First one of silicon gate layer is passed the first device district, and mixes with the impurity with first kenel, and second one of silicon gate layer is passed the second device district, and mix with the impurity with second kenel.Coating layer is formed at the top of silicon gate layer, and in order to avoid forming metal suicide structure in the silicon gate layer place, coating layer has at least one opening, be arranged at first one of silicon gate layer with second one the face that connects.The metal silicide layer that is formed at silicon gate layer top comes out by opening, is positioned at first of the silicon gate layer resistance with second one the face that connects in order to reduction.First group of source/drain doping region is formed at the both sides of silicon gate layer in the first device district, and second group of source/drain doping region is formed at the both sides of silicon gate layer in the second device district.In the step that forms metal silicified layer, at least one self-aligned metal silicide contact zone is formed at first and second group source/drain doping region top simultaneously.
More than introduce according to preferred embodiment of the present invention.Mandatory declaration be, the invention provides many applicable inventive concepts, disclosed specific embodiment only is that explanation realizes and uses ad hoc fashion of the present invention, and is unavailable to limit the scope of the invention.
Though the present invention with preferred embodiment openly as above; so it is not in order to limit the scope of the invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (14)
1. semiconductor framework comprises:
The semiconductor-based end, have the first device district and the second device district;
Grid layer, be across the suprabasil above-mentioned first device district of above-mentioned semiconductor and the second device district, wherein install the impurity of first doping first kenel of the above-mentioned grid layer of distinguishing, install the impurity of second doping second kenel of the above-mentioned grid layer of distinguishing and be across above-mentioned second across above-mentioned first;
Coating layer is arranged at above-mentioned grid layer top, forms metal suicide structure in order to the grid layer of avoiding being covered by above-mentioned coating layer, and wherein above-mentioned coating layer has at least one opening in first face that connects place with second one of above-mentioned grid layer; And
Metal silicified layer is arranged in the above-mentioned opening of top of above-mentioned grid layer.
2. semiconductor framework as claimed in claim 1, wherein above-mentioned coating layer also comprises:
By at least one sublevel that different materials constituted;
Wherein above-mentioned coating layer comprises and is selected from material: silicon oxynitride, tantalum oxide, aluminium oxide, hafnium oxide, silica, silicon nitride, polyethylene glycol oxide, tetraethoxysilane, nitrogen-containing oxide, nitrogen oxide, contain hafnium oxide, contain tantalum pentoxide or contain at least a in the aluminum oxide;
Wherein above-mentioned metal silicified layer comprises and is selected from material: at least a in refractory metal, metal nitride, titanium, titanium disilicide, cobalt, cobalt disilicide, nickel, nickle silicide, titanium nitride, titanium tungsten or the tantalum nitride.
3. semiconductor framework as claimed in claim 2, wherein above-mentioned is substantially by first sublevel that silica constituted by at least one sublevel that different materials constituted, and substantially by second sublevel that silicon nitride constituted.
4. semiconductor framework as claimed in claim 1 also comprises being arranged at suprabasil at least one isolated area of above-mentioned semiconductor, in order to define the above-mentioned first device district and the second device district.
5. semiconductor framework as claimed in claim 4, also comprise the first group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned first device district, and the second group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned second device district.
6. semiconductor framework as claimed in claim 5 also comprises at least one self-aligned metal silicide contact zone, is arranged at the top of above-mentioned first group of source/drain doping region and above-mentioned second group of source/drain doping region.
7. semiconductor framework as claimed in claim 6 also comprises being arranged at above-mentioned grid layer and the gate dielectric at the above-mentioned semiconductor-based end, in order to the above-mentioned grid layer and the above-mentioned semiconductor-based end are isolated.
8. semiconductor framework as claimed in claim 7 also comprises at least one clearance wall, is arranged at the sidewall of above-mentioned grid layer.
9. a semiconductor framework formation method is applicable to semiconductor framework, comprising:
The semiconductor-based end with the first device district and second device district, be provided;
Formation is across the grid layer in the suprabasil above-mentioned first device district of above-mentioned semiconductor and the second device district, wherein install the impurity of first first kenel of mixing of the grid layer of distinguishing, install the impurity of second doping second kenel of the grid layer of distinguishing across above-mentioned second across above-mentioned first;
Form coating layer in above-mentioned grid layer top;
First of above-mentioned grid layer face that connects with second one forms at least one opening in above-mentioned coating layer; And
In the above-mentioned opening of above-mentioned grid layer, form metal silicified layer.
10. semiconductor framework formation method as claimed in claim 9 wherein forms above-mentioned batch of step of cladding in above-mentioned grid layer top and also comprises:
Top in above-mentioned grid layer forms first sublevel with first material; And
Top in above-mentioned first sublevel forms second sublevel with second material.
11. comprising, semiconductor framework formation method as claimed in claim 9, above-mentioned coating layer be selected from material: silicon oxynitride, tantalum oxide, aluminium oxide, hafnium oxide, silica, silicon nitride, polyethylene glycol oxide, tetraethoxysilane, nitrogen-containing oxide, nitrogen oxide, contain hafnium oxide, contain at least a in the tantalum pentoxide or have dielectric constant K greater than 5 high dielectric constant material.
12. semiconductor framework formation method as claimed in claim 9 also comprises being arranged at suprabasil at least one isolated area of above-mentioned semiconductor, in order to define the above-mentioned first device district and the second device district.
13. semiconductor framework formation method as claimed in claim 12, also comprise the first group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned first device district, and the second group of source/drain doping region that is arranged at the both sides of above-mentioned grid layer in the above-mentioned second device district.
14. semiconductor framework formation method as claimed in claim 13, the step that wherein in the above-mentioned opening of above-mentioned grid layer, forms above-mentioned metal silicified layer also comprise form be arranged at above-mentioned first group of source/drain doping region and above-mentioned second group of source/drain doping region above at least one self-aligned metal silicide contact zone.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/257,572 | 2005-10-25 | ||
| US11/257,572 US7485934B2 (en) | 2005-10-25 | 2005-10-25 | Integrated semiconductor structure for SRAM cells |
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| Publication Number | Publication Date |
|---|---|
| CN1956216A true CN1956216A (en) | 2007-05-02 |
| CN100470833C CN100470833C (en) | 2009-03-18 |
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| CNB2006100735022A Active CN100470833C (en) | 2005-10-25 | 2006-04-12 | Semiconductor structure and method of forming the same |
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| US (1) | US7485934B2 (en) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106935510A (en) * | 2015-12-30 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
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| US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
| US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| KR100842472B1 (en) * | 2006-12-27 | 2008-07-01 | 동부일렉트로닉스 주식회사 | Structure of a semiconductor device for decreasing chip area and manufacturing method thereof |
| US7869262B2 (en) * | 2007-01-29 | 2011-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device with an asymmetric layout structure |
| US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
| US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US8188550B2 (en) * | 2007-12-27 | 2012-05-29 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit structure with electrical strap and its method of forming |
| US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| KR101749351B1 (en) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
| US8315084B2 (en) * | 2010-03-10 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully balanced dual-port memory cell |
| US8675397B2 (en) | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
| US8212295B2 (en) | 2010-06-30 | 2012-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | ROM cell circuit for FinFET devices |
| US8942030B2 (en) | 2010-06-25 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM cell circuit |
| US8399931B2 (en) | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
| US8947912B2 (en) * | 2010-07-20 | 2015-02-03 | University Of Virginia Licensing & Ventures Group | Memory cell including unidirectional gate conductors and contacts |
| US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
| US8735972B2 (en) * | 2011-09-08 | 2014-05-27 | International Business Machines Corporation | SRAM cell having recessed storage node connections and method of fabricating same |
| US9911727B2 (en) | 2015-03-16 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strapping structure of memory circuit |
| US10804148B2 (en) * | 2017-08-25 | 2020-10-13 | International Business Machines Corporation | Buried contact to provide reduced VFET feature-to-feature tolerance requirements |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758773B2 (en) * | 1989-07-14 | 1995-06-21 | 三菱電機株式会社 | Method of manufacturing semiconductor device and semiconductor device |
| JP2001044294A (en) * | 1999-08-02 | 2001-02-16 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US6583518B2 (en) * | 2001-08-31 | 2003-06-24 | Micron Technology, Inc. | Cross-diffusion resistant dual-polycide semiconductor structure and method |
| US6700163B2 (en) * | 2001-12-07 | 2004-03-02 | International Business Machines Corporation | Selective silicide blocking |
| JP3914114B2 (en) * | 2002-08-12 | 2007-05-16 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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| CN106935510A (en) * | 2015-12-30 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
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| CN100470833C (en) | 2009-03-18 |
| US7485934B2 (en) | 2009-02-03 |
| TWI321829B (en) | 2010-03-11 |
| US20070090428A1 (en) | 2007-04-26 |
| TW200717716A (en) | 2007-05-01 |
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