CN1948981A - High speed Acceptable testing process for wafer - Google Patents

High speed Acceptable testing process for wafer Download PDF

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Publication number
CN1948981A
CN1948981A CN 200510030551 CN200510030551A CN1948981A CN 1948981 A CN1948981 A CN 1948981A CN 200510030551 CN200510030551 CN 200510030551 CN 200510030551 A CN200510030551 A CN 200510030551A CN 1948981 A CN1948981 A CN 1948981A
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test
smu
testing
editing
devices
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CN 200510030551
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Chinese (zh)
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胡晓明
徐向明
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上海华虹Nec电子有限公司
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Abstract

The invention discloses high speed crystal circle acceptable testing method. It includes the following steps: keeping device combination independent each other in domain designing; using parallel processing with same device and testing items in editing testing algorithm; connecting together the ends with same testing condition in editing testing program and using SMU to finish grounding or adding offset current or voltage; connecting the given end to the different SMU; once finishing testing, once reporting the result and each SMU enjoys testing precision. The invention uses SMU parallel processing and modifies Common PAD connecting method to effectively increase testing speed.

Description

一种高速晶圆允收测试方法 A high-speed wafer acceptance testing methods

技术领域 FIELD

本发明涉及一种适用于半导体参数测试仪器的应用方法,尤其涉及一种高速晶圆允收测试方法。 The present invention relates to a method suitable for use in a semiconductor parameter measuring instruments, particularly to a high speed wafer acceptance testing methods.

背景技术 Background technique

目前在晶圆允收测试(Wafer acceptance test,WAT)过程中,通常存在许多相同类型的Device(器件)和相同的测试项目。 Currently acceptance test wafer (Wafer acceptance test, WAT) process, usually many of the same types of Device (device) and the same test items. 例如需要分别测试长沟道、标准和窄沟道晶体管的阈值电压,沟道饱和电流,晶体管沟道的漏电和晶体管击穿特性等。 Such as the need to test a long channel, respectively, and the threshold voltage of a standard narrow-channel transistor, the channel saturation current of the transistor channel transistor breakdown and leakage characteristics. 如果对上述器件采用逐个项目测试需要花费一定的测试时间,所以如何寻找一种快速而不损失测试精度的方法在此时显得尤为重要。 If a project by project to test the above device takes some time to test, so how to find a quick way without loss of precision is particularly important at this time.

发明内容 SUMMARY

本发明要解决的技术问题是提供一种高速晶圆允收测试方法,可以提高测试速度,减少测试时间。 The present invention is to solve the technical problem of providing a high speed wafer acceptance testing method, the test speed can be increased, reducing testing time.

为解决上述技术问题,本发明提出了一种高速晶圆允收测试方法,其中的版图设计中器件的组合相互独立;编辑测试算法时采用相同类型器件、相同测试项目的并行处理的方法;编辑测试程序时,将各个器件在测试过程中具有相同测试条件端子连接在一起并使用一个SMU(Source/monitor unit)来完成接地或Bias(加偏置电压、电流)的动作,然后指定各个器件中需要测量的端子分别连接到不同的SMU上;测试时,一次完成所有器件的测试工作且每个所述SMU分享测试精度的设定,并一次报告所有器件测试结果。 To solve the above problems, the present invention provides a high speed wafer acceptance testing methods, wherein the composition layout of the device independent; editing device using the same type of test algorithms, parallel processing method of the same test items; Edit when the test program, the operation of each device has the same test conditions and terminals are connected together using a SMU (Source / monitor unit) to complete the ground or bias (plus the bias voltage, current) during the test, then each of the specified device the need to measure the terminals connected to different SMU; test, a complete testing of all devices and each of said shared SMU setting precision, and to report on the test results for all devices.

本发明方法由于在测试中采取SMU并行处理及改进了Common PAD(衬垫,用于测试时压探针或芯片封装时连线用的导电衬垫)的连接方法,有效的提高了测试速度。 The method of the present invention, since a parallel processing SMU taken in the test and improved Common PAD (pad, when the pressure probe for testing when used to connect the chip package or conductive pads) connection method to effectively improve the test speed.

附图说明 BRIEF DESCRIPTION

图1是本发明方法的流程图;图2是本发明方法具体实施例测试算法中,SMU并行处理的示意图。 1 is a flowchart of a method according to the present invention; FIG. 2 is a specific embodiment of the method of the present invention test algorithm, a schematic diagram of the SMU parallel processing.

具体实施方式 Detailed ways

下面结合附图及具体实施例对本发明作进一步详细的说明。 Specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and.

如图1所示,是本发明方法的流程图,即首先在版图中设计相互之间独立的器件的组合;然后编辑适用的测试算法,尽量考虑相同类型器件、相同测试项目的并行处理;在测试程序编辑时,将相同测试项目的器件的Ground端子连接在一起并使用一个SMU来完成接地或加Bias的动作,指定各个需要测量的端子分别连接到不同的SMU上;最后在测试的时候:必须1)一次完成这些器件的测试工作,2)每个SMU分享了测试精度的设定,3)一次将所有的测试结果报告出来。 1 is a flowchart of a method of the present invention, i.e. the first device is designed independently combined with each other in the layout; then edit the applicable test algorithms, try to consider the same type of device, the parallel processing of the same test items; in when editing, the test program ground connection terminals of the device and the same test items together using a ground or finalization action SMU to add Bias, specifying each terminal to be measured are respectively connected to different SMU; last time in the test: must be 1) a complete testing of these devices, 2) each SMU a shared set of test accuracy, 3) once all the test results reported out.

本发明方法具体实施中采用了HP4070仪器。 The method of the present invention employed in a particular embodiment HP4070 instrument. 通常情况下,因为HP4070仪器的SMU对于每一次测试,都会有一个延迟(Internal Delay),该延迟包括测试的等待(Wait)时间、SMU Force(印加Bias)的等待时间、程序的运行时间、调用测试算法的时间、数据的存储时间,仪器的A/D转换时间等等。 Under normal circumstances, because HP4070 instrument SMU For each test, there will be a delay (Internal Delay), the delay includes test wait (Wait) time, run time SMU Force (Inca Bias) waiting time, the program, call time of the test algorithm, data storage time, the instrument a / D conversion time and the like. 当测试项目庞大时候,这些延迟时间的总和是不容忽视的。 When the test when a huge project, the sum of the delay time can not be ignored. 但利用本发明方法,可以最大限度利用HP4070的8个SMU来同时完成对8个Device的测试。 However, using the method of the present invention, it is possible to maximize the use of eight HP4070 SMU to simultaneously complete the test of the eight Device. 具体而言:首先在版图Layout设计中,考虑使用Common ground PAD,并使每个Device的相对独立的方法来设计版图来满足测试要求;然后在测试算法Algorithm里,选用SMU并行的处理方法,具体可见图2所示;在测试程序中,调用上述类型的算法,进行并行测试。 Specifically: firstly in the design layout Layout, consider Common ground PAD, and relatively independent of each process to the design layout Device to meet the test requirements; Algorithm Then a test algorithm, the selected SMU parallel processing method, in particular Figure 2 seen; in the test program, calls for these types of algorithms, parallel testing.

为进一步说明,以采用HP4070仪器进行晶体管的IOFF(沟道漏电)测试为例:在版图设计的时候,将所有晶体管的栅(Gate)、源(Source)、衬底(Substrate)使用Common Gate、common Source、common Substrate的方法分别引出一个PAD,而漏(Drain)端子每个器件各占用一个PAD。 For further explanation, to employ HP4070 instrument IOFF transistor (drain channel) Test Example: When the layout design, all of the transistor gate (Gate), the source (the Source), the substrate (Substrate,) using Common Gate, common Source, common Substrate extraction methods are a PAD, and drain (drain) terminals of each of the devices each occupying a PAD.

在测试程序中,将晶体管的Common Gate、common Source、commonSubstrate三个端子连接在一起,用一个SMU来接地。 In the test procedure, the transistors Common Gate, common Source, commonSubstrate three terminals are connected together to a ground SMU. 将各个器件的Drain端子分别连接到SMU上,并且逐个有序的加上相应的Bias电压。 Drain terminals of the respective devices are connected to the SMU, and individually ordered with the corresponding voltage Bias. Wait一定的时间使SMU处在稳定的工作状态。 Wait some time for the SMU job in a stable state.

最后使用并行测量Drain端口电流的方法,一次将所有Drain端子测试完毕,并且将数据报告Report出来。 Finally, using the method of measuring the parallel port Drain current Drain terminals all at once the test is completed, and the data reporting Report out.

通过实验与分析,选用5786个Device电阻测试,并且在同一Wafer上测试70个有效Die。 Experiments and analysis, selection 5786 Device resistance test, and the test 70 at the same effective Die Wafer. 采用本发明方法进行测试的时间为3.2小时/wafer,而采用原先单个测试的时间为15小时/wafer。 The method of the present invention using the testing time of 3.2 hours / wafer, and the use of a single original test time was 15 hours / wafer.

综上所述,本发明由于在测试中采取SMU并行的方法及改进了CommonPAD的连接方法,有效的提高了晶圆允收测试测试速度。 In summary, the method of the present invention As a result of tests in parallel SMU and improved methods for connecting CommonPAD effectively improve the acceptance test wafer test speed.

Claims (3)

  1. 1.一种高速晶圆允收测试方法,包括版图设计、编辑测试算法、编辑测试程序及测试步骤,其特征是,所述版图设计中器件的组合相互独立;所述编辑测试算法时采用相同类型器件、相同测试项目的并行处理的原则;所述编辑测试程序时,将各个器件在测试过程中具有相同测试条件端子连接在一起,并使用一个SMU来完成接地或加偏置电压、电流的动作,然后将各个器件中需要分别测试的端子,各自分别连接到不同的SMU上;所述测试步骤中,一次完成所有器件的测试工作且每个所述SMU分享测试精度的设定,并一次报告所有器件测试结果。 1. A high speed wafer acceptance testing methods, including layout, editing test algorithm, test procedures and test editing step, characterized in that, in the combination of the layout of the device independent of each other; when the editing using the same test algorithm type devices, the same principle of parallel processing of the test item; when editing the test procedure, each of the devices with the same test conditions during the test terminals are connected together, and used to complete a ground SMU or biasing voltage, current operation, then each device requires testing terminals are each connected to a different SMU; said test step, a complete testing of all devices and each of said shared SMU precision setting, and once report all test results devices.
  2. 2.根据权利要求1所述高速晶圆允收测试方法,其特征是,所述版图设计中,将所测试的一组MOS晶体管的栅、源、衬底使用Common Gate、common Source、common Substrate的设计方法分别引出一个PAD,而漏端子每个测试器件各占用一个PAD;所述编辑测试算法、编辑测试程序中,将所测试晶体管的Common Gate、common Source、common Substrate三个端子连接在一起且用一个SMU来接地,将所述测试器件的漏端子分别连接到所述SMU上,并且逐个加上相应的偏置电压并使所述SMU处在稳定工作态;所述测试步骤中,使用改为并行测试的方法的命令,将所有漏端子一次测试完毕,并且一次报告所有器件测试数据。 The high speed wafer acceptance testing method according to claim 1, characterized in that, the layout, the gate of the MOS transistor group tested, the source, the substrate using the Common Gate, common Source, common Substrate a design method of the PAD are drawn, and the drain terminal of each of the test devices each occupy a the PAD; editing of the test algorithm, edit the test procedure, the test transistors are connected together Common Gate, common Source, common Substrate three terminals and treated with a SMU to ground, are connected to the drain terminal of the device under test to the SMU, and individually with the corresponding bias voltage and is in a stable operational state of the SMU; the test step, command to the method tested in parallel, the drain terminal of all a test is completed, and once all devices report test data.
  3. 3.根据权利要求2所述高速晶圆允收测试方法,其特征是,所述一组MOS晶体管为0.13um以上的晶体管。 3. The high speed of the wafer acceptance testing method according to claim 2, characterized in that the set of MOS transistor 0.13um or more transistors.
CN 200510030551 2005-10-14 2005-10-14 High speed Acceptable testing process for wafer CN1948981A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101311737B (en) 2007-05-23 2010-11-10 中芯国际集成电路制造(上海)有限公司 Wafer quality control methods
CN103163435A (en) * 2013-03-15 2013-06-19 上海华力微电子有限公司 Wafer acceptance test (WAT) breakdown voltage test device and method
CN103308840A (en) * 2013-05-23 2013-09-18 上海华力微电子有限公司 Wafer acceptance test method
CN103645428A (en) * 2013-11-22 2014-03-19 上海华力微电子有限公司 A system and a method for raising the efficiency of a WAT test
CN104049197A (en) * 2014-06-24 2014-09-17 上海集成电路研发中心有限公司 Wafer acceptance test system and method
CN104133172A (en) * 2014-08-08 2014-11-05 上海华力微电子有限公司 Novel test development method for improving simultaneous test number
CN105388353A (en) * 2015-11-26 2016-03-09 中国工程物理研究院电子工程研究所 Anti-noise SOI transistor light current test system design
CN106601645A (en) * 2016-12-13 2017-04-26 武汉新芯集成电路制造有限公司 Test structure and layout method thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101311737B (en) 2007-05-23 2010-11-10 中芯国际集成电路制造(上海)有限公司 Wafer quality control methods
CN103163435A (en) * 2013-03-15 2013-06-19 上海华力微电子有限公司 Wafer acceptance test (WAT) breakdown voltage test device and method
CN103163435B (en) * 2013-03-15 2015-11-25 上海华力微电子有限公司 Breakdown voltage testing device and method for testing the acceptability of the wafer
CN103308840A (en) * 2013-05-23 2013-09-18 上海华力微电子有限公司 Wafer acceptance test method
CN103645428A (en) * 2013-11-22 2014-03-19 上海华力微电子有限公司 A system and a method for raising the efficiency of a WAT test
CN104049197A (en) * 2014-06-24 2014-09-17 上海集成电路研发中心有限公司 Wafer acceptance test system and method
CN104049197B (en) * 2014-06-24 2017-12-15 上海集成电路研发中心有限公司 Wafer acceptance testing and system acceptance testing methods
CN104133172A (en) * 2014-08-08 2014-11-05 上海华力微电子有限公司 Novel test development method for improving simultaneous test number
CN104133172B (en) * 2014-08-08 2017-09-29 上海华力微电子有限公司 A new test method developed to improve the number of parallel test
CN105388353A (en) * 2015-11-26 2016-03-09 中国工程物理研究院电子工程研究所 Anti-noise SOI transistor light current test system design
CN105388353B (en) * 2015-11-26 2018-03-30 中国工程物理研究院电子工程研究所 An anti-noise transistor soi photocurrent Test System
CN106601645A (en) * 2016-12-13 2017-04-26 武汉新芯集成电路制造有限公司 Test structure and layout method thereof

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