CN1930692A - 具有包含二元氧化物的混合物的沟道的半导体器件 - Google Patents
具有包含二元氧化物的混合物的沟道的半导体器件 Download PDFInfo
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- CN1930692A CN1930692A CNA2005800079775A CN200580007977A CN1930692A CN 1930692 A CN1930692 A CN 1930692A CN A2005800079775 A CNA2005800079775 A CN A2005800079775A CN 200580007977 A CN200580007977 A CN 200580007977A CN 1930692 A CN1930692 A CN 1930692A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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Abstract
一种半导体器件，可以包括包含第一二元氧化物和第二二元氧化物的沟道，其中第二二元氧化物选自CdO、SrO、CaO或MgO。
Description
介绍
半导体器件使用于各种电子装置中。例如，薄膜晶体管技术可以用于液晶显示(LCD)屏。一些类型的薄膜晶体管由于低的载流子迁移率而具有相对低的切换速度。在一些应用中，例如在LCD屏的应用中，使用具有相对低切换速度的薄膜晶体管使得很难准确地运动。
附图简述
图1A-1F示出了诸如薄膜晶体管这样的半导体器件的各个实施例。
图2示出了薄膜晶体管的一个实施例的剖面示图。
图3示出了制造薄膜晶体管的一个实施例的方法实施例。
图4示出了有源矩阵显示区的实施例。
详述
本发明公开的示例性实施例包括诸如晶体管这样的包含多成分氧化物半导体的半导体器件。此外，本公开的示例性实施例说明了诸如晶体管这样的包含多成分氧化物半导体的半导体器件所具有的性质，例如光学透明度、化学稳定性、机械性质以及电学性能。示例性实施例包括具有沟道的半导体器件，其中沟道包括MgO和CdO至少其中之一。示例性实施例包括具有多成分氧化物半导体的薄膜晶体管，该多成分氧化物半导体包含至少选自第一组、第二组和第三组二元金属氧化物其中之一的第二二元氧化物和第一二元氧化物，所述第一组、第二组和第三组二元金属氧化物具有第一金属(A)∶第二金属(B)比率为(A∶B)的原子组成，其中A和B互不相同，且都处于大约0.05到大约0.95范围，从而形成等价半导体。一些示例性实施例中，等价半导体包括非晶形式、单相结晶形式或混合相结晶形式。
除非特别指出，说明书和权利要求书中使用的表示组分数量、反应条件等的所有数字在所有实例中都理解成被术语“大约”修饰。因此，除非相反指明，下面的说明书和所附权利要求书中提出的数字参数是近似值，根据本公开所需要获得的性质，该近似值可以改变。丝毫不限制权利要求范围的等效原则的应用，应至少根据所述有效位的数目和通过应用普通舍入技术理解每个数字参数。
应当理解，各个半导体器件可以与本公开说明的各个实施例，即，包括薄膜晶体管的场效应晶体管、有源矩阵显示器、逻辑反相器和放大器相结合使用。图1A-1F示出了示例性薄膜晶体管实施例。该薄膜晶体管可以是任何类型，包括但不限制于水平、垂直、共面电极、交错电极、顶栅、底栅、单栅以及双栅等类型。
这里，共面电极结构意欲表示一种晶体管结构，其中源电极和漏电极与栅电极位于沟道相同的一侧。交错电极结构意欲表示一种晶体管结构，其中源电极和漏电极与栅电极位于沟道的相反侧。
图1A和1B示出了底栅晶体管的实施例，图1C和1D示出了顶栅晶体管的实施例，且图1E和1F示出了双栅晶体管的实施例。图1A-1D每幅图中，晶体管包括衬底102、栅电极104、栅电介质106、沟道108、源电极110以及漏电极112。图1A到1D每幅图中，栅电介质106位于栅电极104与源电极和漏电极110、112之间，所以栅电介质106将栅电极104与源和漏电极110、112物理上分离。此外，图1A到1D每幅图中，源和漏电极110、112分离放置，由此形成源和漏电极110、112之间的一个区域，用于插入沟道108。这样，图1A到1D每幅图中，栅电介质106与沟道108相邻，并使得栅电极104与源和漏电极110、112物理上分离。此外，图1A到1D每幅图中，沟道108与栅电介质106相邻，并与源和漏电极110、112接触。
各个实施例中，例如图1E和1F中所示的双栅实施例中，阐述了两个栅电极104-1、104-2和两个栅电介质106-1、106-2。这种实施例中，栅电介质106-1、106-2相对于沟道108以及源和漏电极110、112的定位，以及栅电极104-1、104-2相对于栅电介质106-1、106-2的定位遵循上述相同的定位关系惯例，上述定位关系中示出了一个栅电介质和一个栅电极。即，栅电介质106-1、106-2位于栅电极104-1、104-2与源和漏电极110、112之间，使得栅电介质106-1、106-2将栅电极104-1、104-2与源和漏电极110、112物理上分离。
图1A-1F每幅图中，源和漏电极110、112之间插入的沟道108提供源和漏电极110、112之间的可控电学路径，使得当对栅电极104施加电压时，电荷可以通过沟道108在源和漏电极110、112之间流动。栅电极104处施加的电压可以改变沟道108传导电荷的能力，这样，通过在栅电极104处应用电压，可以至少部分地控制沟道108的电学性质。
图2中示出了薄膜晶体管实施例的更为详细的描述。图2示出了示例性底栅薄膜晶体管200的剖面图。应当理解，图2中描述的薄膜晶体管的不同部分、它们组成的材料以及它们形成的方法，同样可以应用于这里描述的任何晶体管实施例，包括结合图1A-1F描述的这些
实施例。
而且，各个实施例中，薄膜晶体管200可以包含在包括有源矩阵显示屏装置、逻辑反相器和放大器的大量装置中。薄膜晶体管200还可以包括在红外装置中，该红外装置中还使用透明部件。
如图2所示，薄膜晶体管200可以包括衬底202、与衬底202相邻放置的栅电极204、与栅电极204相邻放置的栅电介质206以及与栅电介质206、源电极210和漏电极212接触的沟道208。各个实施例中，沟道208可以位于源电极210和漏电极212之间并在它们之间电学耦合。
图2所示的实施例中，衬底202包括玻璃。然而，衬底202可以包括用于执行各个实施例的任何合适的衬底材料或组分。
图2中所示的衬底202包括ITO(即氧化铟锡)覆盖涂层以形成栅电极204。然而，任何数目的材料可以用于栅电极204。这种材料可以包括诸如n型掺杂的In2O3、SnO2或ZnO这样的透明材料等等。其它适用的材料包括诸如In、Sn、Ga、Zn、Al、Ti、Ag、Cu这样的金属等。图2所示的实施例中，栅电极204的厚度大约200nm。栅电极的厚度可以根据使用的材料、器件类型或其它因素改变。
图2所示的栅电介质206也可以具有覆盖涂层。尽管图2中示出的栅电极204和栅电介质206是有覆盖涂覆、未图形化的层，但它们可以被图形化。各个实施例中，栅电介质206可以包括各种具有代表栅电介质绝缘性质的材料。这些材料可以包括五氧化二钽(Ta2O5)、钛酸锶(ST)、锶钛酸钡(BST)、锆钛酸铅(PZT)、铋钛酸锶(SBT)和锆钛酸铋(BZT)、二氧化硅(SiO2)、氮化硅(Si3N4)、氧化镁(MgO)、氧化铝(Al2O3)、氧化铪(IV)(HfO2)、氧化锆(IV)(ZrO2)、各种有机电介质材料等。
各个实施例中，源电极210和漏电极212分离地与栅电介质206相邻放置。图2所示的实施例中，源和漏电极210和212可以由与栅电极204相同的材料形成。图2中，源和漏电极210和212的厚度大约为200nm。然而，可以根据使用的材料组成、将使用材料的应用和其它因素改变该厚度。源和漏电极材料的选择可以根据使用它们的应用、器件、系统等而改变。整体器件性能可以根据源和漏材料而改变。例如，在需要基本透明薄膜晶体管的器件中，可以为所需要的效果选择源、漏和栅电极材料。
各个实施例中，沟道208可以由多成分氧化物半导体形成，该多成分氧化物半导体至少包括选自这里都将讨论的第一组、第二组和第三组其中之一的第二二元氧化物和第一二元氧化物，以形成等价半导体。各个实施例中，第一和第二二元氧化物包括第一金属(A)∶第二金属(B)的比率为(A∶B)的原子组成，其中A和B互不相同且都处于大约0.05到大约0.95的范围。
各个实施例中，根据组成、处理条件和其它因素，这些材料可以包括各种形态。该各种形态可以包括非晶态和多晶形式。多晶形式可以包括单相结晶形式或混合相结晶形式。此外，各个实施例中，源电极、漏电极和栅电极可以包括基本透明的材料。通过使用基本透明的材料用作源电极、漏电极和栅电极，薄膜晶体管区域可能对人眼可见的部分电磁波谱是透明的。这种晶体管技术中，一般技术人员应当理解，通过允许更多的光透过显示器，诸如有源矩阵液晶显示器这样的具有与薄膜晶体管(TFT)(具有用于选择或寻址将被打开或关闭的像素的基本透明材料)耦合的显示元件(像素)的装置，将有益于显示特性。
参考图2，沟道208作为等价半导体形成，沟道厚度约50nm，然而，各个实施例中，可以根据各种因素(包括沟道材料是非晶还是多晶，以及将包括沟道的器件)而改变沟道厚度。
本实施例中，沟道208与栅电介质206相邻并位于源和漏电极210、212之间，以与电极210和212接触并电学耦合。在栅电极204处施加的电压可以促进沟道208中的电子积聚。此外，施加的电压可以提高从源电极210到沟道208的电子注入以及通过漏电极212从中提取电子。在本公开的实施例中，使用施加到栅电极204的电压，通过控制漏电极212和源电极210之间的电流，沟道208可以允许开/关操作。
这里，“等价半导体”可以包括从多成分氧化物半导体形成的薄膜，该多成分氧化物半导体至少具有第一二元氧化物和第二二元氧化物。此外，这里使用的“等价半导体”包括：相当数量的阳离子(例如99％或更多)在等价半导体中共享相似的氧化态。应当理解，等价半导体中的阳离子的氧化态并不都是相同的值。这样，在具有一种或多种氧化状变形的等价半导体中，存在可探测的阳离子成分。
一个实施例中，第一二元氧化物和第二二元氧化物选自第一组CdO、SrO、CaO和MgO等价化合物、第二组In2O3和Ga2O3等价化合物以及第三组SnO2、GeO2、PbO2和TiO2等价化合物的其中之一。此外，第一二元氧化物和第二二元氧化物可以选自包括ZnO的第一组的其中之一(即，第一组包括ZnO、CdO、SrO、CaO和MgO等价化合物)。另一个实施例中，当所选的第一二元氧化物是SrO或CaO时，第二二元氧化物可以从CdO、ZnO和MgO等价化合物中选择，从而形成等价半导体。
另一实施例中，第一二元氧化物和第二二元氧化物可以包括第一金属(A)∶第二金属(B)的比率为(A∶B)的原子组成，其中A和B互不相同且都在大约0.05到大约0.95的范围内。另一个实施例中，A和B都处于大约0.10到大约0.90的范围。这些原子组成不考虑氧和其它元素的可选存在。它们仅代表第一和第二金属的相对比率。
这里描述的等价半导体显示出了令人满意的电学性能(取决于组成材料选择、处理条件等)，特别是在沟道迁移率方面。等价半导体可以呈现令人惊奇的沟道迁移率的增加。本领域技术人员应当理解，迁移率是能够帮助确定薄膜晶体管性能的特征，因为最大操作频率、速度和驱动电流随沟道迁移率成正比地增加。此外，等价半导体可能在可见和红外光谱都是透明的，允许整个薄膜晶体管对于电磁波谱的可见区域是光学透明的。
本公开的实施例中所述的等价半导体的使用有利于集成电路结构中各种薄膜的应用。例如，这些应用包括晶体管，如这里讨论的，例如水平、垂直、共面电极、交错电极、顶栅、底栅、单栅、双栅等薄膜晶体管。各个实施例中，本公开的晶体管(例如，薄膜晶体管)可以作为开关或放大器提供，其中施加到晶体管栅电极的电压可以影响流经沟道的等价半导体的电子流。技术人员应当理解，晶体管可以以各种方式操作。例如，当晶体管用作开关时，晶体管可以操作在饱和区，且当晶体管用作放大器时，晶体管可以操作在线性区。此外，下面结合图4示出和描述了在集成电路中结合等价半导体沟道的晶体管以及结合诸如可视显示面板(例如有源矩阵LCD显示器)的集成电路的结构的使用。在显示应用和其它应用中，通常希望将薄膜晶体管的一个或多个剩余部分例如源、漏和栅电极，至少制造成部分透明。
图2中，源电极210和漏电极212包括厚度约为200nm的ITO。然而，各个实施例中，根据各种因素，包括材料种类、应用和其它因素，可以改变该厚度。各个实施例中，电极210和212可以包括透明导体，例如n型掺杂的宽带半导体。实例包括但不限于n型掺杂的In2O3、SnO2、氧化铟锡(ITO)或ZnO等。电极110和112还可以包括诸如In、Sn、Ga、Zn、Al、Ti、Ag、Cu、Au、Pt、W或Ni这样的金属等。本公开的各个实施例中，所有电极104、110和112可以包括透明材料，使得晶体管的各个实施例可以基本透明。
可以使用各种技术形成这里所述的晶体管结构的各个部分。例如，栅电介质206可以通过使用Ta(OC2H5)5和O2，在大约430摄氏度通过低压CVD工艺沉积，并可以接着退火以减小漏电流特性。可以采用薄膜沉积技术，例如蒸发(例如热蒸发、电子束蒸发)、物理气相沉积(PVD)(例如，直流反应溅射、RF磁控溅射、离子束溅射)、化学气相沉积(CVD)、原子层沉积(ALD)，脉冲激光沉积(PLD)、分子束外延(MBE)等。此外，为了沉积本公开实施例的晶体管的各个部分，可以采用备选方法。这些备选方法可以包括金属薄膜的阳极电镀(电化学氧化)、以及液体前驱物的沉积，例如包括热喷墨和压电式按需即喷印刷的喷墨印刷和旋涂。薄膜图形化可以采用结合腐蚀或剥离工艺的光刻，或可以使用备选技术例如遮蔽掩模。一层或多层(例如图2所示的沟道)的掺杂还可以通过引入氧空位和/或等价元素的替代物而完成。
本公开说明的实施例还包括形成金属的方法，该金属包含衬底或衬底组件的表面上的薄膜，该衬底或衬底组件例如是在形成集成电路(特别是这里描述的薄膜晶体管)中使用的其上具有或没有层或结构的硅晶片。应当理解本公开的方法不局限于在硅晶片上进行沉积；而是也可以使用其它类型的晶片(例如砷化镓、玻璃等)。
而且，其它衬底也可以用于本公开的方法。例如这些衬底包括光纤、引线等。一般地，薄膜可以在衬底的最低表面上直接形成，或者，例如，它们可以在图形化晶片中的各个层(即表面)中的任意一个上形成。
一个实施例中，图3示出了制造半导体器件的方法。本公开的各个实施例中，在形成半导体器件中，可以提供衬底或衬底组件。这里，术语“衬底”指底部衬底材料层，例如，玻璃晶片中玻璃材料的最底层。术语“衬底组件”指其上具有形成的一个或多个层或结构的衬底。衬底类型的实例包括但不局限于玻璃、塑料和金属，并包括如下这些物理形式，例如薄层、薄膜和覆盖层，并且可以不透明或基本透明。
在方框310，可以提供漏电极和源电极。例如，可以在衬底组件的衬底上提供漏电极和源电极。
方框320中，可以沉积与漏电极和源电极接触并包括等价半导体的沟道。例如，沟道可以沉积在漏电极和源电极之间，从而与这两个电极电学耦合。各个实施例中，沉积与漏电极和源电极接触的沟道可以包括：提供包含一个或多个前驱物化合物的前驱物合成物，该前驱物化合物选自包括锌(Zn)、镉(Cd)、和镁(Mg)的第一组、包括铟(In)和镓(Ga)的第二组以及包括锡(Sn)、锗(Ge)、铅(Pb)和钛(Ti)的第三组的其中之一。这里描述的前驱物化合物的各组组合可以用于前驱物合成物。这样，这里，术语“前驱物合成物”指包括这里描述化学式的一种或多种化合物的固体或液体，可选地混合不同于这里描述化学式的一种或多种化合物。例如，可以在一个前驱物合成物或分离的合成物中提供第一组的锌前驱物化合物和镉前驱物化合物。备选地，一个前驱物化合物可以提供两种金属。这里“液体”指溶液或纯液体(室温下的液体，或室温下可以随温度升高而熔化的固体)。这里，“溶液”不要求固体的完全可溶性；而是，溶液可以具有一些不溶解材料，然而更希望是具有相当数量的能被有机溶剂带到用于化学气相沉积工艺的气相中的材料。这里描述的前驱物化合物还可以包括适用于化学气相沉积系统的一种或多种有机溶剂，以及其它添加物，例如辅助所需化合物蒸发的自由配体。
适于薄膜沉积技术的各种Zn、Cd、Mg、In、Ga、Sn、Ge、Pb和Ti的前驱物化合物可以用于本公开的实施例。前驱物化合物的实例包括但不局限于金属和金属氧化物，包括ZnO、ZnO2、CdO、SrO、SrO2、CaO、CaO2、MgO、MgO2、InO、In2O3、GaO、Ga2O、Ga2O3、SnO、SnO2、GeO、GeO2、PbO、PbO2、Pb2O3、Pb3O4、TiO、TiO2、Ti2O3和Ti3O5等价化合物。尽管这里示出了特定的化合物，但可以使用各种前驱物化合物，只要它们可以用在沉积工艺即可。本发明的各个实施例中，Zn、Cd、Mg、In、Ga、Sn、Ge、Pb和Ti前驱物化合物可以包括中性化合物，并且在室温下可以是液体或固体。如果它们是固体，它们在有机溶剂中充分可溶以允许蒸发，它们可以从固态蒸发或升华或烧蚀(例如，通过激光烧蚀或溅射)，或它们具有低于它们分解温度的熔化温度。这样，这里描述的很多前驱物化合物适用于蒸发沉积技术，例如化学气相沉积(CVD)技术(例如，闪蒸技术、气泡技术和/或微滴技术)。
这里描述的前驱物化合物可以用于喷墨沉积、溅射和气相沉积技术(例如，化学气相沉积(CVD)或原子层沉积(ALD))的前驱物合成物中。备选地，这里描述的某些化合物可以用在其它沉积技术(例如旋涂覆盖等)的前驱物合成物中。一般地，包含具有少量碳原子(例如每个R基具有1-4个碳原子)的有机R基的化合物适用于使用气相沉积技术。包含具有较大量碳原子(例如每个R基具有5-12个碳原子)的有机R基的那些化合物一般适用于旋涂或浸渍涂敷。
这里，术语“有机R基”表示烃基(具有不同于碳和氢的可选元素，例如氧、氮、硫和硅)，该烃基分类成脂族基、环状基(cyclicgroup)或脂肪和环状基的组合(例如烷芳和芳烷基)。本公开说明的上下文中，有机基是不干扰包含金属薄膜形成的那些基团。它们可以属于这样的种类和尺寸，即对于使用化学气相沉积技术形成包含金属的薄膜不产生干扰。术语“脂族基”表示饱和或不饱和线性或分岔的烃基。例如该术语用于包含烷基、烯基和炔基。术语“烷基”表示饱和线性或分岔的烃基，例如，包括甲基、乙基、异丙基、叔丁基、庚基、十二烷基、十八烷基、戊基、2-乙基已基等。术语“烯基”表示不饱和的、线性或分岔的具有一个或更多碳-碳双键的烃基，例如乙烯基。术语“炔基”表示不饱和的、线性或分岔的具有一个或更多碳-碳三键的烃基。术语“环状基”表示闭环烃基，该闭环烃基分类为脂环基、芳香基或杂环基。术语“脂环基”表示具有集合这些脂肪族基性质的环状烃基。术语“芳香基”或“芳基”表示单或多核芳香烃基。术语“杂环基”表示闭环烃基，其中环中的一个或多个原子是不同于碳的元素(例如，氮、氧、硫等)。
仍然参考图3，可以在衬底或衬底组件的一个表面上从前驱物化合物中沉积等价半导体的沟道。例如，前驱物合成物的等价半导体的沟道可以从前驱物化合物沉积，以与薄膜晶体管的漏电极和源电极接触，从而电学耦合漏和源电极。各个实施例中，沟道可以采用物理气相沉积技术，例如溅射涂膜，它可以包括蒸发前驱物合成物并将其引导到衬底或衬底组件。沉积沟道的其它方法可以包括一种或多种物理气相沉积技术，例如直流反应溅射、RF溅射、磁控溅射、离子束溅射或它们的组合。
各个实施例中，尽管这不是必须的，但包含在沟道中的等价半导体在它的整个厚度上具有均匀的成分。例如，首先可以沉积第一二元氧化物的前驱物化合物，然后可以沉积第一和第二二元氧化物的前驱物化合物的合成物，随着薄膜形成，所沉积的第二二元氧化物的前驱物化合物数量增加。应当理解，等价半导体的厚度将取决于它的应用。例如，该厚度的范围可以为大约1纳米到大约1000纳米。备选实施例中，厚度的范围可以为大约10纳米到大约200纳米。
本公开的实施例中，前驱物化合物可以包括用于第一二元金属半导体的一种或多种前驱物化合物以及用于第二二元金属半导体的一种或多种前驱物化合物。用于二元金属半导体的前驱物化合物一般是单核的(即，每个分子包含一种金属的单体)，尽管也可使用弱结合的二聚物(即包含通过氢或配价键微弱键合在一起的两个单体的二聚物)。本公开的其它实施例中，二元金属半导体的前驱物化合物可以包括适于气相沉积的有机金属化合物。这种有机金属化合物的实例包括但不限于乙酰丙酮锌[Zn(C5H7O2)2]和乙酰丙酮铟[In(C5H7O2)3]。
如这里所述，在本公开的实施例中，用于溅射工艺的等价半导体的第一二元金属半导体的前驱物化合物可以包括形成CdO的那些前驱物化合物，该CdO是n型半导体，具有极好的电子输运性质。第一组等价化合物的剩余两个二元金属半导体的其中之一MgO呈现相对于CdO相当大的带隙。这样，MgO一般认为是电介质，具有它本身的优点，不认为可以作为晶体管沟道。然而，MgO和CdO等价，在各个二元氧化物的性质之间引入调节各种材料性质(例如带隙、化学活性等)的可能性，由此允许对给定应用调节相关性质。
此外，选自这里列出的三个组其中之一的两个或更多组的二元金属氧化物，允许等价半导体具有金属与金属比率的谱(例如，第一金属(A)∶第二金属(B)的原子组成具有比率(A∶B)，其中A和B互不相同且都处于大约0.05到大约0.95的范围)。本实施例中，等价半导体中的二元氧化物的金属与金属比率排除任何“纯”金属氧化物半导体。如这里使用的，“纯”材料理解成包括一定程度的杂质“掺杂”；这样，本公开实施例中示出的第一和第二二元金属半导体的组成范围应该使次要成分的量足够大，使之不被理解成主要成分定义的薄膜中的“杂质”。
此外，因为等价化合物不必是同构的，因此很多情况下在跨越两个(或更多)二元金属氧化物之间的整个相空间中不能获得固体溶液。然而，即使在获得多相混合物的情况(例如，ZnO+ZnxCd1-xO[固体溶液]+CdO)，作为沟道的等价半导体的性能(例如迁移率)可能处于这些组成的二元金属氧化物性能的中间(尽管对于多相薄膜，有效带宽可能由存在相的禁带的最低值确定，而不是对于固体溶液采用一些中间值)。
当使用上述靶(例如，衬底或衬底组件)，通过溅射在薄膜中沉积沟道时，可能获得单相结晶形式以形成沟道。备选地，由于使用上述靶的溅射，等价半导体的实施例可以呈现混合相结晶形式。例如，混合相结晶形式可以包括但不局限于两相或更多相，可以包括，例如第一金属氧化物半导体、第二金属氧化物半导体和选自第一组ZnO、CdO、SrO、CaO和MgO等价化合物的第三二元氧化物。备选地，混合相结晶形式可以包括但不限于两相或更多的相，例如这些相可以包括选自第一组ZnO、CdO、SrO、CaO和MgO等价化合物或第三组SnO2、GeO2、PbO2和TiO2等价化合物的第四二元氧化物、第三二元氧化物、第二金属氧化物半导体和第一金属氧化物半导体。对于这些实例，第一金属∶第二金属∶第三金属的原子组成的比率为A∶B∶C，其中A、B和C各不相同，且都处于大约0.025到大约0.95的范围。此外，第一金属∶第二金属∶第三金属∶第四金属的原子组成的比率为A∶B∶C∶D，其中A、B、C和D各不相同，且都处于大约0.025到大约0.95的范围。备选地，A、B、C和D可以都处于大约0.017到大约0.95的范围，以及大约0.10到大约0.80的范围。
另一些实施例中，等价半导体可以具有基本非晶的形式。例如，等价半导体可以包括第一二元氧化物的第一金属(A)与第二二元氧化物的第二金属(B)的原子组成比，其中A和B各不相同且都处于大约0.05到大约0.95的范围。其它实施例中，A和B各不相同且都处于大约0.10到大约0.90的范围。
一个特定实例中，源自第一组等价化合物的CdO和MgO可以包括比这里讨论的范围大的第一金属(A)与第二金属(B)的原子组成比。例如因为CdO和MgO都是同构的，除了等价之外，固体溶液可以在大部分中间相空间稳定。因此，第一金属(A)与第二金属(B)的A和B值的比率(A∶B)可以都处于0.0到1.00的范围。换句话说，除了这两个化合物落在其中的比率，CdO和MgO的组成范围可以包括纯的CdO或MgO。
可以在惰性气体和/或反应气体氛围执行溅射或化学气相沉积工艺以形成相对纯的多成分氧化物半导体，用于至少包含第一二元氧化物和第二二元氧化物的等价半导体。惰性气体一般选自包括氮、氦、氩及其混合物的组。本公开的上下文中，惰性气体一般不与这里描述的前驱物化合物反应且不干扰等价半导体的形成。
反应气体可以选自与这里描述的化合物在沉积条件下至少在表面反应的各种气体。反应气体的实例包括氢气和诸如O2这样的氧化气体。载气和/或反应气体的各种组合可以用于本公开的实施例以形成等价半导体。
例如，等价半导体的溅射工艺中，可以通过使用氩气和氧气的混合气体作为溅射气体，在特定流速条件下应用RF功率执行该工艺，以获得溅射沉积腔中所需的沉积。然而，很明显，根据本公开，形成等价半导体的任何方式(对于其形成来讲)并不局限于任意特定工艺例如溅射。
方框330中，在形成本公开的薄膜晶体管的实施例中，可以提供栅电极和位于栅电极与沟道之间的栅电介质。
这里描述的实施例可以用于制造芯片、集成电路、单片装置、半导体装置以及微电子装置，例如显示装置。例如，图4示出了诸如有源矩阵液晶显示器(AMLCD)480这样的显示装置的实施例。图4中，AMLCD 480可以包括显示区460矩阵中的像素器件(即，液晶元件)440。矩阵中的像素器件440可以与同样位于显示区460中的薄膜晶体管400相耦合。薄膜晶体管400可以包括这里公开的薄膜晶体管的实施例。此外，AMLCD 480可以包括正交的控制线462和464，用于供给寻址信号电压到薄膜晶体管400，以影响薄膜晶体管导通和截止，并控制例如像素器件440，以提供AMLCD 480上的图像。
尽管这里阐述和描述了特定示例性实施例，但本领域技术人员应当理解，为获得相同技术而计算的布置可以代替所示的特定示例性实施例。本公开意欲覆盖本公开实施例的修改或变化。应当理解上述描述是以阐述方式而非限制方式进行。
对于本领域技术人员，回顾上述描述，上述示例性实施例和其它这里没有特别描述的实施例的组合是显而易见的。本发明的各个实施例的范围包括使用上述结构和方法的其它应用。因此，本发明各个实施例的范围应由所附权利要求以及这些权利要求的等效表述的全部范围确定。
上述详述中，为简化本公开说明，各种特征组合到单个示例性实施例中。本公开的所述方法不应理解成反映这样的意图：本发明的实施例必须具有每个权利要求明确表明的更多特征。而是，如下面权利要求反映的，发明的主题内容较少地依赖于单个公开示例性实施例的所有特征。这样，下面的权利要求由此与说明书相结合，每个权利要求保持其本身是一个独立的实施例。
Claims (10)
1.一种半导体器件100/200/400，包括：
漏电极112/212；
源电极110/210；
与漏电极112/212和源电极110/210接触的沟道108/208，其中沟道108/208包括选自第一组CdO、SrO、CaO和MgO的第二二元氧化物和第一二元氧化物；
栅电极104/204；和
位于栅电极和沟道之间的栅电介质106/206。
2.权利要求1的半导体器件100/200/400，其中当第一二元氧化物选自SrO和CaO时，第二二元氧化物选自CdO、ZnO和MgO。
3.权利要求2的半导体器件100/200/400，其中沟道108/208包括第一金属(A)∶第二金属(B)比率为(A∶B)的原子组成，其中A和B都在大约0.05到大约0.95的范围内。
4.权利要求1的半导体器件100/200/400，其中第一组包括ZnO，且沟道108/208包括选自第一组ZnO、CdO、SrO、CaO和MgO的第三二元氧化物，并具有第一金属∶第二金属∶第三金属比率为A∶B∶C的原子组成，其中A、B和C各不相同，且它们都处于大约0.025到大约0.95的范围。
5.权利要求4的半导体器件100/200/400，其中沟道108/208包括选自第一组ZnO、CdO、SrO、CaO和MgO的第四二元氧化物、第三二元氧化物、第二二元氧化物和第一二元氧化物，并具有第一金属∶第二金属∶第三金属∶第四金属比率为A∶B∶C∶D的原子组成，其中A、B、C和D各不相同，且它们都处于大约0.017到大约0.95的范围。
6.权利要求1的半导体器件100/200/400，其中沟道108/208包括选自第一组CdO、SrO、CaO和MgO和第二组In2O3和Ga2O3其中之一的第二二元氧化物和第一二元氧化物。
7.权利要求6的半导体器件100/200/400，其中沟道108/208包括选自第一组CdO、SrO、CaO和MgO、第二组In2O3和Ga2O3以及第三组SnO2、GeO2、PbO2和TiO2其中之一的第二二元氧化物和第一二元氧化物。
8.权利要求7的半导体器件100/200/400，其中沟道108/208包括选自第三组SnO2、GeO2、PbO2和TiO2的第三二元氧化物、第二二元氧化物和第一二元氧化物，并具有第一金属∶第二金属∶第三金属比率为A∶B∶C的原子组成，其中A、B和C各不相同，且它们都处于大约0.025到大约0.95的范围。
9.权利要求8的半导体器件100/200/400，其中沟道108/208包括选自第三组SnO2、GeO2、PbO2和TiO2的第四二元氧化物、第三二元氧化物、第二二元氧化物和第一二元氧化物，并具有第一金属∶第二金属∶第三金属∶第四金属比率为A∶B∶C∶D的原子组成，其中A、B、C和D各不相同，且它们都处于大约0.017到大约0.95的范围。
10.权利要求1的半导体器件100/200/400，其中漏电极112/212、源电极110/210、沟道108/208、栅电极104/204以及栅电介质106/206的至少其中之一基本透明。
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| EP1443130B1 (en) * | 2001-11-05 | 2011-09-28 | Japan Science and Technology Agency | Natural superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film |
| JP2003179233A (ja) | 2001-12-13 | 2003-06-27 | Fuji Xerox Co Ltd | 薄膜トランジスタ、及びそれを備えた表示素子 |
| TWI285515B (en) | 2002-02-22 | 2007-08-11 | Semiconductor Energy Lab | Light-emitting device and method of manufacturing the same, and method of operating manufacturing apparatus |
| US7339187B2 (en) | 2002-05-21 | 2008-03-04 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures |
| US7189992B2 (en) | 2002-05-21 | 2007-03-13 | State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University | Transistor structures having a transparent channel |
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- 2005-02-25 KR KR1020067018713A patent/KR101107794B1/ko active IP Right Grant
- 2005-02-25 JP JP2007502846A patent/JP2007529117A/ja active Pending
- 2005-02-25 CN CN200580007977A patent/CN100592535C/zh not_active Expired - Fee Related
- 2005-03-02 TW TW094106252A patent/TWI353623B/zh not_active IP Right Cessation
- 2005-10-25 US US11/257,935 patent/US7462862B2/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2005093847A1 (en) | 2005-10-06 |
| US7462862B2 (en) | 2008-12-09 |
| TW200534367A (en) | 2005-10-16 |
| KR101107794B1 (ko) | 2012-01-25 |
| US20050199879A1 (en) | 2005-09-15 |
| EP1733433A1 (en) | 2006-12-20 |
| US20060043377A1 (en) | 2006-03-02 |
| TWI353623B (en) | 2011-12-01 |
| JP2007529117A (ja) | 2007-10-18 |
| CN100592535C (zh) | 2010-02-24 |
| US7282782B2 (en) | 2007-10-16 |
| KR20070006770A (ko) | 2007-01-11 |
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