CN1914720A - 具有接触支撑层的半导体封装以及制造该封装的方法 - Google Patents
具有接触支撑层的半导体封装以及制造该封装的方法 Download PDFInfo
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Abstract
半导体封装(1)包括衬底(3),该衬底包括在其上表面上的多个导电迹线(6)和上接触区(7)和其底表面上的第二多个下导电迹线(8)和外部接触区(9),以及附着到外部接触区(9)的外部导电装置(11)。半导体封装(1)还包括半导体管芯(2),其包括具有多个管芯接触垫(4)的有源表面,通过导电装置(12)电连接到衬底(3)的接触区(7)。在管芯(2)的有源表面上的导电装置之间的支撑层(13)至少覆盖导电装置(12)的基底部分。
Description
技术领域
本发明涉及一种制造包括接触支撑层的半导体封装的方法。
背景技术
DE101 33 791 A1公开了一种用于将预形成的焊球设置和附着到半导体芯片上的方法。该方法复杂且不可靠。
发明内容
本发明的一个目的是制造一种更加可靠的半导体封装以及一种用于制造该封装的简单节省成本的方法。
本发明的该目的通过独立权利要求的主题来解决。进一步的改进从从属权利要求的主题中产生。
根据本发明组装包括接触支撑层的半导体封装的方法包括以下步骤。提供包括多个半导体管芯或芯片的半导体晶片。每个半导体管芯包括具有多个管芯接触区或垫的有源表面。在该工艺的下一步骤中,前驱导电装置或前驱凸起形成或沉积于管芯接触区上。前驱导电装置优选包括焊料基材料,如高铅、共晶焊料或无铅焊料。
包括管芯的有源表面的晶片的前表面以及至少前驱导电装置的基底涂覆有电绝缘或接触支撑层。支撑层的厚度优选是约0.1μm至约10μm。然后加热晶片以由前驱导电装置形成导电装置如焊料凸起或微观焊球。然后,由于残余物减少了,因此将带或带叠层优选为UV带附着到导电装置的上表面上和电绝缘层的上表面上,以提供导电装置的进一步保护。然后减薄晶片的背表面直到晶片具有希望的厚度和/或表面光洁度为止。在减薄工艺之前晶片通常具有约750μm的厚度,且在减薄工艺之后具有小于约250μm的厚度。然后,去除带并从晶片分离出各个管芯。
根据本发明的电绝缘或支撑层非常有利。在焊料回流工艺中加热前驱导电装置之前将其沉积在晶片的前表面上。因此防止了优选包括焊料装置的前驱导电装置横向扩展,且将其机械地限制到管芯接触区。这防止了在管芯的有源表面上的电路之间形成短路。
在焊料回流期间,由于表面张力的影响,导电装置的上部变成圆形。该圆形形状是所希望的且是有利的。此外,由于电绝缘层近接触导电装置的基底以及导电装置和管芯接触垫之间的界面,因此在晶片减薄或背面研磨工艺期间,电绝缘层有利地用作机械支撑或导电装置的套环(collar)。
电绝缘层进一步的益处在于,在带层叠阶段期间,该带很好地装配在导电装置上,且避免了导电装置基底处的滞留空气。这产生在减薄工艺期间用于导电装置的更加可靠的支撑,而且在减薄工艺期间接触不会被破坏。因此改善了使用本发明方法制造的封装的可靠性。
电绝缘层优选包括透明或半透明材料,并且具有使得在晶片上沉积涂层之后包括在晶片前侧中的各个管芯之间的锯齿迹(sawstreet)保持可见的厚度。由于接着可将锯齿迹用于从晶片更加精确地分离出各个管芯或芯片,因此这是有利的。
电绝缘层也用作在芯片的有源表面上的钝化层和底部填充材料之间的界面增强装置。芯片的更加有效且可靠的底部填充物使用根据本发明的方法来实现。封装的可靠性也改善了。
由于电绝缘层为导电装置提供了另外的机械支撑,因此在随后的处理以及制造工艺的测试阶段期间,包括电绝缘层的封装也较小可能被破坏。因此,废弃了较少的封装,改善了制造工艺的生产率。
有利地,前驱导电装置形成或沉积于晶片级的管芯接触区上,且更有利地借助电镀技术来实现。晶片级的前驱导电装置的形成更加有效和节省成本。由于在一个制造步骤中且基本上是同时形成所有的前驱导电装置,因此使用电镀技术是有效的。这降低了制造时间且简化了工艺。电镀也改善了在管芯接触垫上设置导电装置的精确性和导电装置的均匀性。
可替换地,通过有利地用于沉积晶片级的前驱导电装置的丝网印刷技术将前驱导电装置形成于管芯接触区上。降低了制造时间并简化了工艺。
通过电镀沉积的前驱导电装置通常具有伞状形状,其中凸起的顶部具有圆形形式且横向大于基本上为棒状的底部。绝缘支撑层有利地支撑前驱凸起的基底并改善接触的可靠性。
优选地,电绝缘层通过旋涂技术沉积于晶片的前表面上。这具有的益处在于可以简单且快速地沉积层,并且其厚度可根据需要来控制。具有均匀厚度和良好覆盖的涂层有利地使用旋涂技术来获得。
可替换地,电绝缘层通过浸涂技术来沉积。浸涂具有的益处在于可控制在导电凸起的表面上方的涂层的厚度。该涂层例如在基底处较厚且向着顶部变薄,如果需要的话。基本上分离的环氧树脂助熔剂(epoxy flux)的套环形成于每个导电凸起的基底部分周围。这具有的益处在于在凸起的基底处提供另外的机械支撑,且降低了用在工艺中的环氧树脂助熔剂材料的质量。可替换地,基本上连续的环氧树脂助熔剂层可形成于晶片的上表面上。
电绝缘层优选包括环氧树脂助熔剂或环氧树脂助熔剂底部填充材料。
晶片背侧的减薄或晶片的背面研磨通过机械研磨和抛光或化学蚀刻或现有技术中公知的方法来进行。
本发明的方法有利地用于倒装片或球栅阵列封装或芯片尺寸封装或超薄球栅阵列封装或晶片级芯片尺寸封装或过铸模倒装片封装。
在管芯从晶片分离之后,将其组装形成半导体封装。将管芯安装在衬底如再分配板上,以使管芯的有源表面面对再分配板的上表面,且导电装置提供芯片或管芯和再分配板之间的电连接。将外部接触或导电装置如焊球附着到再分配板的底表面上,以提供从封装到外部衬底如印刷电路板的电连接。
根据本发明组装的半导体封装包括衬底,例如再分配板,其包括在其上表面上的多个上导电迹线及上部接触区和在其底表面上的第二多个导电迹线和外部接触区。外部导电装置如焊球附着到衬底底部上的外部接触区。
半导体封装还包括半导体管芯或芯片,其包括具有多个管芯接触区或垫的有源表面。导电装置如微观焊球提供管芯接触区和衬底的上部接触区之间的电连接。管芯的有源表面和衬底的上表面之间的区域通过例如环氧树脂或环氧树脂助熔剂底部填充物来底部填充。本发明的半导体封装还包括管芯的有源表面上的导电装置之间的电绝缘或支撑层,其至少覆盖导电装置的基底部分。该电绝缘层包括例如环氧树脂助熔剂或环氧树脂助熔剂底部填充材料。借助于显微镜,电绝缘支撑层可在根据本发明的半导体封装的抛光的截面中看到。
在背面研磨凸起的晶片期间,根据本发明的接触支撑层对凸起提供改善程度的支撑。与使用蜡不同,沉积环氧树脂支撑层简单且灵活,并且不需要冗长的去除工艺。由于凸起的基底已经由环氧树脂支撑,因此可获得带和凸起之间的良好接触。这确保了UV带完全固化并降低了在凸起的圆周处的残余物形成。对比于使用抗蚀剂来支撑凸起,本发明的方法还非常简单和快捷。尤其是,抗蚀剂的剥离困难且耗时。
附图说明
现在将借助于实例参考附图描述本发明的实施例。
图1示出了根据本发明组装的球栅阵列半导体封装的截面图,
图2示出了包括多个半导体管芯的晶片,每一个包括根据本发明的方法中使用的多个电镀凸起,
图3示出了具有电绝缘层的图2的晶片的旋涂,
图4示出了图3的晶片的电镀凸起的回流,
图5示出了UV带至图4的晶片的附着,
图6示出了图5的晶片的背面研磨,
图7示出了半导体管芯从图6的晶片的去带(detaping)和单切(singulation),
图8示出了用于本发明的替换实施例的图3的方法步骤,其中通过浸涂沉积电绝缘涂层,
图9示出了用于图8的实施例的图4的方法步骤,和
图10示出了用于图8的替换实施例的图4的方法步骤。
具体实施方式
图1示出了包括半导体管芯2的半导体封装1的截面图,其通过倒装片技术安装至再分配板3。
半导体管芯2包括包含多个管芯接触垫4的有源表面和无源表面。再分配板3包括非导电核心材料5的片,并包括在其上表面上的多个上导电迹线6和上接触垫7以及在其底表面上的多个下导电迹线8和外部接触区9。再分配板3还包括多个基本上垂直的导电通孔10,其将上接触垫7与再分配板3的底表面上的接触区9电连接。焊球11附着到外部接触区9以提供从封装1至外部电路板(其在图中未示出)的电连接。
半导体管芯2安装有其与再分配板3的上表面面对的有源表面,并且其通过设置在管芯接触区4和再分配板3上表面上的上接触垫7之间的微观焊球12电连接至再分配板3。在此微观用于描述借助于显微镜看到的焊球。
环氧树脂的薄支撑层13涂覆微观焊球12之间的管芯2的有源表面。在薄支撑环氧树脂层13和再分配板3的上表面之间的区域用底部填充材料14来填充。可借助于显微镜,在抛光的截面中观察薄环氧树脂层13和底部填充材料14之间的界面。
图2示出了包括用在根据本发明的方法中的多个管芯2的半导体晶片15。每个管芯2包括在其有源表面上的多个管芯接触垫4。晶片15的前侧19包括管芯2的有源表面。在根据本发明的方法的第一步骤中,通过公知的电镀方法在管芯接触垫4上沉积多个前驱导电凸起16。前驱导电凸起16包括焊料。如此沉积的前驱凸起16具有蘑菇形状,其是该工艺的特征。凸起16的上部是圆形的,且横向上比具有基本上为棒形状的下部大。
图3示出了通过旋涂技术在晶片15的前侧19上薄电绝缘层的沉积或环氧树脂13的涂覆。环氧树脂层13具有使得附着到包括在晶片15的前表面19中的管芯接触垫4的电镀凸起16的下部涂覆有环氧树脂层13的厚度。环氧树脂层13的上表面在焊料凸起12之间基本上是凹形。环氧树脂层13是接触支撑层。
图4示出了工艺的下一阶段,其中图3的晶片15经受焊料回流工艺。在工艺的该步骤中,电镀前驱凸起16的上部在加热处理形成微观焊球12期间变成圆形。环氧树脂层13防止了前驱凸起16从管芯接触垫4向外横向扩展到相邻区域中。环氧树脂层13的上表面在焊球12之间具有基本上是凹形的形式。
图5示出了UV带叠层18至图4的晶片15的前侧19的附着。由于焊球13的基底部分借助环氧树脂层13来支撑,因此带叠层18紧密地装配在焊球12的在环氧树脂层13上暴露的表面和环氧树脂层13的设置在焊球12之间的上表面上方。
图6示出了图5的晶片15的背侧20的研磨和抛光,以降低晶片15的厚度。晶片15的厚度通常从约750μm降低到小于约250μm。图7示出了从晶片15的带18的去除和各个管芯2的单切。
图8示出了用环氧树脂支撑层17涂覆晶片15的前侧19的替换方法。在本发明的该实施例中,包括电镀前驱凸起16的晶片15的前侧19浸渍到包括环氧树脂助熔剂树脂的槽21中。电镀前驱凸起16和晶片15的前表面19涂覆有电绝缘支撑层17。
图9示出了根据本发明的方法的第二实施例在电镀凸起16的焊料回流凸起以形成微观焊球12之后的晶片15。用在浸涂工艺中的环氧树脂助熔剂的体积较小,以使环氧树脂助熔剂的套环22形成在每个焊球12的基底周围。环氧树脂套环22在每个焊球12周围形成基本上分离的支撑区。
图10示出了通过其中使用较大体积的环氧树脂助熔剂的浸涂方法形成的替换环氧树脂支撑层。在本发明的该实施例中,环氧树脂支撑层17形成了焊球12之间的基本上连续的层,并具有在焊球12之间基本上为凹形的起伏表面。每个焊球12的涂层厚度在附着到管芯接触垫4的焊球12的基底处比在顶部处大。
使用与前述相似的工艺减薄根据图9和10中示出的实施例的晶片15。然后将带18附着到环氧树脂支撑层17并研磨和抛光晶片15的背侧20。晶片15的厚度通常被从约750μm降低到小于约250μm。然后从晶片分离出各个管芯。
然后将管芯2安装在再分配板3上以形成半导体封装1,对其测试、封装并输送给用户。
参考数字
1半导体封装
2半导体管芯
3再分配板
4管芯接触区
5核心材料
6上导电迹线
7上接触垫
8下导电迹线
9外部接触区
10通孔
11外部焊球
12微观焊球
13环氧树脂电绝缘层
14底部填充物
15晶片
16电镀前驱凸起
17被浸渍的电绝缘层
18UV带叠层
19晶片的前表面
20晶片的背表面
21环氧树脂助熔剂槽
22环氧树脂助熔剂套环
Claims (7)
1.一种组装半导体封装(1)的方法,包括以下步骤:
-提供晶片(15),其包括多个半导体管芯(2),每个半导体管芯(2)包括具有多个管芯接触区(4)的有源表面,
-在管芯接触区(4)上形成前驱导电装置(16),
-用电绝缘层(13;17;22)涂覆晶片(15)的前表面(19)和至少前驱导电装置(16)的基底,
-加热晶片(15)以由前驱导电装置(16)形成导电装置(12),
-将带(18)附着至导电装置(12)的上表面以及电绝缘层(13,17)的上表面,
-减薄晶片(15)的背表面(20),
-去除该带(18),
-从晶片(15)分离出各个管芯(2)。
2.根据权利要求1的组装半导体封装(1)的方法,其特征在于,前驱导电装置(12)通过电镀技术形成。
3.根据权利要求1或权利要求2的组装半导体封装(1)的方法,其特征在于,前驱导电装置(12)通过丝网印刷技术来形成。
4.根据权利要求1至3中的一项的组装半导体封装(1)的方法,其特征在于,通过旋涂技术将电绝缘层(13)沉积在晶片(15)的前表面(19)上。
5.根据权利要求1至4中的一项的组装半导体封装(1)的方法,其特征在于,通过浸涂技术将电绝缘层(17;22)沉积于晶片(15)的前表面(19)上。
6.一种半导体封装(1),包括:
-衬底(3),包括在其上表面上的多个导电迹线(6)和上部接触区(7)和在其底表面上的第二多个下导电迹线(8)和外部接触区(9),以及附着到外部接触区(9)的外部导电装置(11),
-半导体管芯(2),包括具有多个管芯接触垫(4)的有源表面,通过导电装置(12)电连接到衬底(3)的接触区(7),和
-在管芯(2)的有源表面上的导电装置之间至少覆盖导电装置(12)的基底部分的支撑层(13;22)。
7.根据权利要求6的半导体封装(1),其特征在于,电绝缘层(13;22)包括环氧树脂助熔剂或环氧树脂底部填充材料。
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2004
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- 2004-02-11 CN CNB2004800415362A patent/CN100508148C/zh not_active Expired - Fee Related
- 2004-02-11 EP EP04710086A patent/EP1714316A1/en not_active Withdrawn
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2006
- 2006-08-10 US US11/501,913 patent/US7452747B2/en not_active Expired - Fee Related
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CN108538734A (zh) * | 2010-12-22 | 2018-09-14 | 英特尔公司 | 具有嵌入式层叠硅通孔管芯的衬底 |
CN108538734B (zh) * | 2010-12-22 | 2022-04-19 | 英特尔公司 | 具有嵌入式层叠硅通孔管芯的衬底 |
Also Published As
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US7452747B2 (en) | 2008-11-18 |
EP1714316A1 (en) | 2006-10-25 |
US20070037319A1 (en) | 2007-02-15 |
WO2005088696A1 (en) | 2005-09-22 |
CN100508148C (zh) | 2009-07-01 |
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