CN1855469A - Semiconductor device and method of manufacturing same - Google Patents
Semiconductor device and method of manufacturing same Download PDFInfo
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- CN1855469A CN1855469A CNA2006100747015A CN200610074701A CN1855469A CN 1855469 A CN1855469 A CN 1855469A CN A2006100747015 A CNA2006100747015 A CN A2006100747015A CN 200610074701 A CN200610074701 A CN 200610074701A CN 1855469 A CN1855469 A CN 1855469A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention discloses a semiconductor and preparing method, which is characterized by the following: forming insulating film (6a) on the surface of semiconductor chip (2); forming first distribution (5a) on the insulating film (6a); adhering glass base (3) on the surface of semiconductor chip (2); covering insulating film (16a) on the lateral and back of semiconductor chip (3); setting lateral connection with first distribution (5a) and second wiring (9a) on the extended back of semiconductor chip (2); forming conductive terminal (8) on the second distribution (9a); reducing cost of BGA (ball Grid Array) typed semiconductor device; improving reliability.
Description
The application is that application number is 03122991.3 (the applying date: the dividing an application of application of the same name on April 23rd, 2003).
Technical field
The present invention relates to a kind of semiconductor device with BGA (ball Grid Array) type of spherical conducting terminal.
Background technology
In recent years, as three-dimensional mounting technique, perhaps as new encapsulation technology, CSP (Chip SizePackage) is attracted attention.CSP is meant the compact package that has with the overall dimension of the overall dimension approximate same size of semiconductor chip.
In the prior art, a kind of as CSP has BGA N-type semiconductor N device.This BGA N-type semiconductor N device is meant be made of a plurality of configurations on an interarea of encapsulation of spherical conducting terminal metal materials such as scolding tin latticed, and is electrically connected the device that is constituted with the semiconductor chip that carries on the another side of encapsulation.
Then, when being assembled into this BGA N-type semiconductor N device in the e-machine,, semiconductor chip is electrically connected with the external circuit that carries on printed circuit board (PCB) by each conducting terminal being crimped on the wiring pattern on the printed circuit board (PCB).
Such BGA N-type semiconductor N device, wait the semiconductor device of other CSP type to compare with SOP that has the pin of protrusion at sidepiece (SmallOutline Package) and QFP (Quad Flat Package), have more conducting terminal can be set, and advantage that can miniaturization.This BGA N-type semiconductor N device, the image sensor chip that for example can be used as the digital camera of lift-launch in portable phone uses.
Figure 22 represents the summary pie graph of the BGA N-type semiconductor N device of prior art.Figure 22 (A) represents the stereogram of the face side of this BGA N-type semiconductor N device.In addition, Figure 22 (B) represents the stereogram of the rear side of this BGA N-type semiconductor N device.
This BGA N-type semiconductor N device 101 seals semiconductor chip 104 after passing through to get involved epoxy resin 105a, 105b between the 1st and the 2nd glass substrate 102,103.On an interarea of the 2nd glass substrate 103, promptly on the back side of BGA N-type semiconductor N device 101, be configured to a plurality of spherical terminals 106 latticed.
This conducting terminal 106 is connected with semiconductor chip 104 by the 1st wiring 107.In a plurality of the 1st wirings 107, draw end aluminium wiring by connecting respectively from the inside of semiconductor chip 104, each spherical terminal 106 and semiconductor chip 104 are electrically connected.
Cross section structure for this BGA N-type semiconductor N device 101 further describes with reference to Figure 21.Figure 21 represents to be divided into along line of cut the cutaway view of the BGA N-type semiconductor N device 101 behind the single chip.
Be configured in be provided with on the lip-deep dielectric film 108 of semiconductor chip 104 the 1st the wiring 107.This semiconductor chip 104 is bonding by resin 105 and the 1st glass substrate 102.In addition, the back side of this semiconductor chip 104 is bonding by resin 105 and the 2nd glass substrate 103.
Then, an end of the 1st wiring 107 is connected with the 2nd wiring 110.The 2nd wiring 110 is extended on the surface of the 2nd glass substrate 103 since an end of the 1st wiring 107.Then, in the 2nd wiring of extending on the 2nd glass substrate 103, form spherical conducting terminal 106.
The following manufacturing process that semiconductor device 101 is described successively with reference to Figure 17～Figure 21.
As shown in figure 17, prepare to have the semiconductor crystal wafer of a plurality of semiconductor chips 104, form by SiO in its surface
2The dielectric film 108 that such insulant forms.Then, on dielectric film 108,, form the 1st wiring 107 across for a plurality of semiconductor chips 104 being cut into border (line of cut) S of single chip.This border S is the border of a plurality of semiconductor chips 104.
Then, on the surface of the semiconductor chip 104 that has formed the 1st wiring 107, adopt transparent epoxy resin 105 bonding the 1st glass substrates 102 that are used to support semiconductor chip 104.
Then, semiconductor chip 104 is carried out the bottom milled processed, the skiving chip thickness carries out etching along border S to the back side and the dielectric film 108 of semiconductor chip 104 afterwards, and the 1st wiring 107 is exposed.
Then, as shown in figure 18, the exposed portions serve of the side of the semiconductor chip after the etching 104, dielectric film 108 and the 1st wiring 107 is covered with epoxy resin 105, and this resin 105 is as bonding agent, bonding the 2nd glass substrate 103 on the back side of semiconductor chip 104.
Then, as shown in figure 19, the 2nd glass substrate 103 sides are offered V font grooving along border S.This grooving can adopt cutting toolss such as blade to carry out cut.At this moment, the degree of depth of the V font groove that cutting forms is to arrive the 1st substrate 102.Like this, the 1st wiring 107 is cut into 2 sections, and expose its side.
Then, as shown in figure 20, form the cutting face that aluminium lamination covers the 2nd glass substrate 103 and cutting formation.Like this, the face that exposes of the 1st wiring 107 is connected with aluminium lamination.Then,, form given wiring pattern, form the 2nd wiring 110 the aluminium wiring patternization.
Then, as shown in figure 21, in the 2nd wiring 110, form diaphragms 111 such as scolding tin mask.Then, the peristome by diaphragm 111 forms the spherical conducting terminal 106 that is made of metals such as scolding tin in the 2nd wiring 110.Then, cut along border S.Like this, finish the BGA N-type semiconductor N device 101 of prior art shown in Figure 22.
Above-mentioned technology, for example on the books in following patent documentation.
[patent documentation]
The public table of patent 2002-512436 communique
But, in above-mentioned BGA N-type semiconductor N device and manufacturing engineering thereof, have following shortcoming.
The first, owing to adopt 2 substrates of the 1st glass substrate 102 and the 2nd glass substrate 103, there is the manufacturing process complexity in the manufacturing engineering of the BGA N-type semiconductor N device 101 of prior art, and the high problem of manufacturing cost.
The second, owing to bonding the 2nd glass substrate 103 on the back side of semiconductor chip 104,, need carry out the so-called special cut of grooving (notching) for cutting off the 1st wiring 107.For this reason, on the end of the 1st wiring 107, (for example, pollution etc. is sneaked into and produced to foreign matter) unusually can appear in the cutting cross section of implementing grooving processing.
The 3rd, because the length of the contact portion between the 1st wiring 107 side and the 2nd wiring 110 only is provided with the degree of 2 μ m～3 μ m, when being subjected to stress etc. from the outside, might cause broken string between the side of the 1st wiring 107 and the 2nd wiring 110.And the 1st wiring 107 side is because the cutting face that forms when being grooving, and the side of the 1st wiring 107 is more coarse, and the adhesive property between the 2nd wiring 110 is poor.
Summary of the invention
At the invention of above shortcoming, its purpose is to provide a kind of N-type semiconductor N of BGA cheaply device 101 just in the present invention.In addition, provide a kind of, realize the high BGA N-type semiconductor N device 101 of reliability by making the connection between the 1st wiring the 107 and the 2nd wiring 110 good.
Semiconductor device of the present invention forms dielectric film on the surface of semiconductor chip, form the 1st wiring on this dielectric film.Bonding supporting substrates on the surface of semiconductor chip is with the side and the back side of the 2nd dielectric film covering semiconductor chip.Then, the 2nd wiring that is connected with the 1st wiring, extend is set on semiconductor chip backside.Further, in the 2nd wiring, form conducting terminal such as bump pad.
In addition, the manufacture method of semiconductor device of the present invention is ready to have the semiconductor crystal wafer of a plurality of semiconductor chips, is forming the 1st wiring on the surface of semiconductor crystal wafer behind the 1st dielectric film.Then, bonding supporting substrates on the surface of semiconductor crystal wafer.Then, along the border of a plurality of semiconductor chips the back side of semiconductor crystal wafer is carried out etching, the part of above-mentioned the 1st wiring is exposed.Then, cover the side and the back side of semiconductor chip with the 2nd dielectric film.Then, etching is carried out in the 1st wiring, the 1st wiring is divided be broken into 2 sections.Then, form the 2nd wiring that is connected with the 1st wiring, behind the 2nd dielectric film, on semiconductor chip backside, extend.Then, in the 2nd wiring, form conducting terminal.Then, cut along the border of a plurality of semiconductor chips.
Description of drawings
Fig. 1 represents the relevant the of the present invention the 1st and the cutaway view of the semiconductor device of the 2nd embodiment.
Fig. 2 represents the cutaway view of the semiconductor device of relevant the 3rd embodiment of the present invention.
Fig. 3 represents the cutaway view of the semiconductor device of relevant the 4th embodiment of the present invention.
Fig. 4 represents the cutaway view about the manufacture method of the semiconductor device of the 1st embodiment of the present invention.
Fig. 5 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 1st embodiment.
Fig. 6 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 1st embodiment.
Fig. 7 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 1st embodiment.
Fig. 8 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 1st embodiment.
Fig. 9 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 2nd embodiment.
Figure 10 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 2nd embodiment.
Figure 11 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 3rd embodiment.
Figure 12 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 3rd embodiment.
Figure 13 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 3rd embodiment.
Figure 14 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention the 3rd and the 4th embodiment.
Figure 15 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 3rd embodiment.
Figure 16 represents the cutaway view of manufacture method of the semiconductor device of relevant the present invention's the 3rd embodiment.
Figure 17 represents the cutaway view of manufacture method of the semiconductor device of prior art.
Figure 18 represents the cutaway view of manufacture method of the semiconductor device of prior art.
Figure 19 represents the cutaway view of manufacture method of the semiconductor device of prior art.
Figure 20 represents the cutaway view of manufacture method of the semiconductor device of prior art.
Figure 21 represents the cutaway view of manufacture method of the semiconductor device of prior art.
Figure 22 represents the stereogram of the semiconductor device of prior art.
Embodiment
Following with reference to description of drawings embodiment of the present invention.
The cutaway view of the BGA N-type semiconductor N device 1a of relevant the present invention's the 1st embodiment of Fig. 1 (A) expression.
State after Fig. 1 (A) expression will be cut along border S at a plurality of semiconductor chips 2 of the BGA type that forms on the semiconductor crystal wafer.All are all identical for single BGA N-type semiconductor N device 1a after the incision.Below, the formation of single BGA N-type semiconductor N device 1a is described.
On the surface of semiconductor chip 2, form dielectric film 6a, on this dielectric film 6a, form the 1st wiring 5a.Then, on the surface of this semiconductor chip 2, adopt resin 4 adhering glass substrates 3 as bonding agent.Dielectric film 6a is for example by silicon oxide film (SiO
2), silicon nitride film (SiN), organic insulating film formation such as (epoxy resin etc.).
The 1st wiring 5a is the metal pad that is made of aluminium or aluminium alloy, is electrically connected with circuit element in the semiconductor chip 2.The 1st wiring 5a is also referred to as and extends pad (Extension Pad) owing to the border S that extends between a plurality of semiconductor chips 2.
Dielectric film 16a covers the side of semiconductor chip 2 and the dielectric film at the back side, for example by silicon oxide film (SiO
2), silicon nitride film (SiN), organic insulating film formation such as (epoxy resin etc.).
In addition, on the given position on the dielectric film 16a at the back side of semiconductor chip 2, form a plurality of buffer units 7.This buffer unit 7 is configured to overlap the below of conducting terminal 8 described later, relaxes the impact when forming conducting terminal 8 on the 2nd wiring 9a.In addition, buffer unit 7 also plays the effect that the height of conducting terminal 8 is improved to a certain extent some.
The 2nd wiring 9a forms on the surface of dielectric film 16a and buffer unit 7.Be the metal line that constitutes by aluminium or aluminium alloy, on the side of the 1st wiring 5a, connect the 2nd wiring 9a.
The length of the contact portion between the side of the 1st wiring 5a and the 2nd wiring 9a is about 2 μ m～3 μ m.The 1st wiring 5a observes in the plane, because broad formation, so the width of its contact portion also can broadening.
And, be formed with diaphragm 10a in the 2nd wiring on the 9a, by the peristome of diaphragm 10a, be formed with spherical conducting terminal 8 being separated with on the 2nd wiring 9a of the not shown coating that constitutes by Ni, Cu.
Followingly the 2nd embodiment is described with reference to Fig. 1 (B).The difference of this embodiment and the 1st embodiment is, the planform of the 2nd wiring and the 1st wiring end contact portion.That is, in the 1st embodiment, contact makes its electrical connection between side by the 1st wiring 5a and the 2nd wiring 9a, and in the present embodiment, makes between the part at the back side of the 1st wiring 5b and the 2nd wiring 9b to contact, and makes its electrical connection.The length of the contact portion between the part at the back side of the surface of this 2nd wiring 9b and the 1st wiring 5b is about 2 μ m～3 μ m.
In addition, dielectric film 6b, the 16b in the present embodiment, diaphragm 10b respectively with the 1st embodiment in dielectric film 6a, 16a, diaphragm 10a suitable.
According to the 1st and the 2nd embodiment,, therefore can realize the semiconductor device low, more slim than conventional example cost because the 2nd glass substrate 103 is not set.
Then, owing to cancelled the 2nd glass substrate 103, not the technology that adopts the such blade of prior art to cut, and can the 1st wiring 5a, 5b be cut apart by etch processes.Therefore, the side of the 1st wiring 5a, the 5b that contacts with the 2nd wiring 9a, 9b becomes slyness and clean state, even the length of contact portion also can improve both electrical connections and the reliability of mechanical connection about 2 μ m～3 μ m.
Followingly the 3rd embodiment of the present invention is described with reference to Fig. 2.In the figure, the inscape identical with Fig. 1 adopts identical symbol, and omits its explanation.
The present embodiment is compared with above-mentioned the 2nd embodiment, and the contact portion between the 1st wiring 5c and the 2nd wiring 9c enlarges and forms.For example, the length of its contact portion but also can further prolong about 4 μ m～6 μ m.That is, for enlarge on the back side of the 1st wiring 5c and the contact portion of the 2nd wiring between the 9c, the 1st wiring 5c has protuberance 20c, thereby its part is more protruded to the outside of semiconductor chip 2 than dielectric film 16c.
Then, the 2nd wiring 9c extends to protuberance 20c from the side of semiconductor chip 2, becomes the L font, enlarges the contact on protuberance 20c.At this, the 1st wiring back side of 5c and the length of the adhesive portion between the protuberance 20c, preferably the length than the side of the 1st wiring 5c is big.For this reason, can further improve the 1st wiring 5c and the 2nd wiring between the 9c electrical connection and the reliability of mechanical connection.In addition, dielectric film 6c, the 16c in the present embodiment, diaphragm 10c respectively with the 1st embodiment in dielectric film 6a, 16a, diaphragm 10a suitable.
Followingly the 4th embodiment of the present invention is described with reference to Fig. 3.In Fig. 3, the inscape identical with Fig. 1 adopts identical symbol, and omits its explanation.
In the present embodiment, by the protuberance 20d of the 1st wiring 5d is set, contact portion between the 1st wiring 5d and the 2nd wiring 9d is being enlarged on the basis that forms, form the side of the 1st wiring 5d and the part (hereinafter referred to as contact site S) that the 2nd wiring contacts between the 9d again, can further improve the electrical connection between the 1st wiring 5d and the 2nd wiring 9d and the reliability of mechanical connection.
That is, in the present embodiment, the length of the contact-making surface between the back side part of the 1st wiring 5d and the 2nd wiring 9d expands to about 4 μ m～6 μ m and forms, on this basis, make the 2nd wiring 9d also with the contacts side surfaces of the 1st wiring 5d.In addition, also can make the whole contacts side surfaces of the 2nd wiring 9d and the 1st wiring 5d.At this, the length of the back side of the 1st wiring 5d and the contact site of the 2nd wiring between the 9d is preferably big than the 1st the connect up length of side of 5d.
In addition, in the 1st and the 2nd embodiment, the 2nd wiring 9a, 9b also can contact with part or all of side of the 1st wiring 5a, 5b.
Below, the manufacture method of the semiconductor device of relevant the present invention's the 1st embodiment is described with reference to Fig. 4～Fig. 8.
At first, as shown in Figure 4, prepare to have the semiconductor crystal wafer of a plurality of semiconductor chips 2.This semiconductor chip 2 for example is a CCD image sensor chip etc.Then, by the lip-deep dielectric film 6a of semiconductor chip 2,, form the 1st wiring 5a across border (line of cut) S of a plurality of semiconductor chips 2.
Then, as shown in Figure 5, transparent epoxy resin 4 adhering glass substrates 3 are adopted on the dielectric film 6a surface on the semiconductor chip 2 that has formed the 1st wiring 5a.Glass substrate 3 is as the supporting substrates effect of semiconductor chip 2.Then, the bottom milled processed is carried out at the back side of semiconductor chip 2, the skiving chip thickness, simultaneously from the rear side of semiconductor chip 2 along border S, semiconductor chip 2 and dielectric film 6a are carried out etching, make the part at the back side of the 1st wiring 5a, preferably its middle body exposes.In addition, the bottom milled processed is not the processing that necessarily needs in the present embodiment.
In this such technology, because not as prior art, have glass substrate in the rear side of semiconductor chip 2, can reduce cost.In addition, can cut down the worker ordinal number, further can make semiconductor device self slimming.
Then, as shown in Figure 6, formation dielectric film 16a covers the side of the semiconductor chip 2 after the etching and the exposed portions serve of the 1st wiring 5a.This dielectric film 16a for example is to adopt CVD (ChemicalVapor Deposition: the silicon oxide film (SiO of Xing Chenging chemical vapour deposition technique)
2), silicon nitride film (SiN) or organic insulating film (epoxy resin etc.) etc., its thickness is about 2 μ m.
Then, shown in Fig. 7 (A), coating resist 11 exposes, development treatment on the surface of dielectric film 16a, as mask dielectric film 16a is carried out the anisotropy etching with resist 11.Being provided with on dielectric film 16a with border S is that the width at center is the peristome 12 of d1, and the middle body of the 1st wiring 5a is exposed.
Then, shown in Fig. 7 (B), as mask, carry out the anisotropy etching once more, the 1st wiring 5a is etched away fully, the 1st wiring 5a is divided into 2 sections with resist 11 and dielectric film 16a.Like this, the wiring of the 1st after segmentation 5a exposes the side.
At this, when 5a that dielectric film 16a and the 1st is connected up carries out etching,, be not limited thereto though carry out 2 etchings, also can adopt identical etching gas carry out etching continuously to dielectric film 16a and the 1st wiring 5a.
Then, remove resist 11 after, on the desired position on the dielectric film 16a of the rear side of semiconductor chip 2, form a plurality of buffer units 7, for convenience of explanation, in the drawings for 2 of 1 semiconductor chips, 1 buffer unit 7 that drawn.This buffer unit 7 is configured on the position that forms conducting terminal 8.
Then, shown in Fig. 8 (A), form the whole rear side that metal level that aluminium or aluminium alloy constitute covers semiconductor chip 2 with sputtering method etc.
Then, shown in Fig. 8 (B), on metal level, form resist (not drawing among the figure), to its expose, development treatment.Then, as mask, metal level is carried out etching, resin 4 is exposed with this resist, and the peristome 13 (width d2) that formation ratio open 12 (the width d1) of portion are narrow (d1＞d2).Like this, on the 1st wiring 5a, make the 2nd wiring 9a contact, both are electrically connected and mechanical connection.At this, the thickness of the 2nd wiring 9a forms about 2 μ m～3 μ m.The length of the contact portion of the 1st wiring 5a and the 2nd wiring 9a, as mentioned above, about 2 μ m～3 μ m.
Then, shown in Fig. 1 (A), on the 2nd wiring 9a, implement Ni, Cu plating back and form diaphragm 10a such as scolding tin mask, on diaphragm 10a, form peristome,, utilize coating scolding tin such as silk screen printing, on the 2nd wiring 9a, form conducting terminal 8 by this peristome.Then, cut along border S.Like this, finish the BGA N-type semiconductor N device 1a of relevant the present invention the 1st embodiment shown in Fig. 1 (A).
Below, the manufacture method of the semiconductor device of relevant the present invention's the 2nd embodiment is described with reference to Fig. 9 and Figure 10.In addition, corresponding to the technology of Fig. 4, Fig. 5, Fig. 6, because the manufacture method of the present embodiment is identical with it, in this explanation technology thereafter.
Shown in Fig. 9 (A), coating resist 19 exposes, development treatment on the back side of semiconductor chip 2, forms the peristome 20 with A/F d3.
Then, shown in Fig. 9 (B), as mask, the 1st wiring 5b is carried out etching, the 1st wiring 5b is divided into 2 sections, form the peristome 14 of A/F d3 simultaneously with resist 19.Remove resist 19 then.At this, the A/F d3 among Fig. 9 (B) is littler than the A/F d1 of Fig. 7 (A).
Then, as shown in figure 10, form on the given position on dielectric film 16b after the buffer unit 7, exposing of the back side part of the 5b that connects up on the surface, the 1st of dielectric film 16b and side, resin 4 forms the 2nd wiring 9b on face and the buffer unit 7.
Then, form resist (not drawing among the figure), to its expose, development treatment, carry out etching, form and the peristome of peristome 14 same widths d3.Like this, shown in Fig. 1 (B), the back side part of the 1st wiring 5b is contacted about 2 μ m～3 μ m with the length of the contact portion of the 2nd wiring 9b, both are electrically connected.At this, the thickness of the 2nd wiring 9b forms about 2 μ m～3 μ m.
Then, implement Ni, Cu plating back on the 9b in the 2nd wiring and form diaphragm 10b, on the desired position of this diaphragm 10b, form peristome, utilize silk screen printing etc. that scolding tin is coated on the peristome, on the 2nd wiring 9b, form conducting terminal 8.Then, the border S along a plurality of semiconductor chips 2 cuts.Like this, finish the BGA N-type semiconductor N device 1b of relevant the present invention the 1st embodiment shown in Fig. 1 (B).
In each manufacture method of above-mentioned the 1st, the 2nd embodiment, owing to be not to resemble to adopt blade to cut the prior art, the end surface of the 1st wiring 5a, 5b can be not coarse, can keep clean state.Therefore, can improve the 1st wiring 5a, 5b and the 2nd connection reliability that connects up between 9a, the 9b.
In addition, in the manufacture method of the 1st, the 2nd embodiment, adopt earlier and form the 2nd wiring 9a, 9b, then it is carried out etching, and be segmented into 2 sections method in the wide region sputter.Like this, even the part that the 1st wiring 5a, 5b contacts with the 2nd wiring 9a, 9b is about 2 μ m～3 μ m and conventional example is in equal extent, also can improve both electrical connections and the reliability of mechanical connection.
In addition, in each manufacture method of above-mentioned the 1st, the 2nd embodiment, though be after the 1st wiring 5a, 5b carried out etching and be divided into 2 sections, contact with the 2nd wiring 9a, 9b, also can be after 9a, 9b be connected with the 1st wiring 5a, 5b and the 2nd wiring, simultaneously connect up 9a, 9b of the 1st wiring 5a, 5b and the 2nd carried out the etching disjunction.
Below, the manufacture method of the 3rd embodiment of relevant semiconductor device of the present invention is described with reference to Figure 11～Figure 16.
Preparation has the semiconductor crystal wafer of a plurality of semiconductor chips 2, and by the lip-deep dielectric film 6c of this semiconductor chip 2, the border S of clamping semiconductor chip 2, the certain width d11 of being separated by separate formation the 1st wiring 5c, 5c.The 1st wiring 5c, 5c for example is the superiors' wiring of semiconductor chip 2.
Then, as shown in figure 12, after getting involved the 1st wiring 5c and dielectric film 6c, the resin 4 of the transparent epoxide resin material of coating etc. on semiconductor chip 2.Then, resin 4 uses as bonding agent, at the surface adhesion glass substrate 3 of semiconductor chip 2.
Then, semiconductor chip 2 is carried out the bottom milled processed, the skiving chip thickness, simultaneously from the rear side of semiconductor chip 2 along border S, semiconductor chip 2 and dielectric film 6c are carried out etching, the part of the 1st wiring 5c, 5c and the part of resin 4 are exposed.In addition, the bottom milled processed is not the processing that necessarily needs in the present embodiment.
Then, as shown in figure 13, on side, the 1st wiring 5c, the 5c of the side after the etching of the back side of semiconductor chip 2, semiconductor chip 2, dielectric film 6c and the resin 4 that exposes, adopt the CVD method to form dielectric film 16c.
Then, shown in Figure 14 (A), coating resist 12 exposes, development treatment on the surface of dielectric film 16c, as mask dielectric film 16c is carried out the anisotropy etching with resist 12.Peristome 15 is set on dielectric film 16c.At this, the face that exposes of the 1st wiring 5c, 5c in the peristome 15 is called protuberance 20c.The width of peristome 15 is d12, and width d12 is wideer than the interval d11 between the 1st wiring 5c, the 5c.In addition, border S is positioned at the substantial middle of peristome 15.
At this, Figure 14 (B) is illustrated in dielectric film 16c to Figure 14 (A) when carrying out etching, and the figure the when part of the resin 4 that exists between the 1st wiring 5c, the 5c that separates is etched will be explained below for this Figure 14 (B).
Then, remove resist 12 after, as shown in figure 15, on dielectric film 16c, form buffer unit 7.Then, on the surface of dielectric film 16c, the exposing the exposing on the face of face, resin 4 of the surface of buffer unit 7, the 1st wiring 5c, 5c, adopt sputtering method etc. to form the metal level that aluminium or aluminium alloy constitute.Then, coating resist 18 exposes, development treatment on metal level.
Then, as shown in figure 16, as mask, metal film is carried out etching, peristome 17 is set with resist 18.At this, the width of peristome 17 is d13, and width d13 is littler than Figure 14 (A) width d12 (B), and d11 is identical with width 13, interval.That is, make the end sides of protuberance 20c consistent with the end sides of the 2nd wiring 9c.
Then, through and the identical technology of manufacture method of the semiconductor device of relevant the 1st embodiment, finish the semiconductor device 1c of the present embodiment shown in Figure 2.
In the present embodiment, form peristome 15 with width d12 wideer than the interval width d11 of the 1st wiring 5c, 5c, the back side of protuberance 20c of the 1st wiring 5c, 5c of such formation is exposed.Then, have wide contact-making surface between the back side of protuberance 20c and the 2nd wiring 9c, for example have the length about 4 μ m～6 μ m.In addition, if above-mentioned contact-making surface more than 6 μ m, can further increase bonding strength.
Below, the manufacture method of the 4th embodiment of relevant semiconductor device of the present invention is described with reference to Figure 14 (B).
The present embodiment is done further to inquire into to the engraving method of Figure 14 (A) in above-mentioned the 3rd embodiment.
Figure 14 (B) expression as mask, is carried out the cutaway view of etched state with resist 12 to dielectric film 16d.In this etching, if carried out etching, the part of the resin 4 of the 1st wiring between 5d, the 5d that then will be in separation is also etched.Wet etching or dry ecthing are adopted in this etching, use not to the etched corrosive agent of the 1st wiring 5d, 5d.
Its result, make the 1st the wiring 5d, 5d the side part or all expose.Then, remove resist 12, implement the technology identical, finish shown in Figure 3 having and make the connect up semiconductor device 1d of structure of the back side of 5d, 5d and contacts side surfaces of the 2nd wiring 9d and the 1st with the 3rd embodiment.
In addition, in above-mentioned the 1st, the 2nd, the 3rd, the 4th embodiment, also can adopt plastics to constitute sheet material instead of glass substrate 3.But, if when semiconductor chip 2 is the CCD image sensor chip, need can printing opacity sheet material.In addition, the 1st wiring 5a, 5b, 5c, 5d and the 2nd wiring 9a, 9b, 9c, 9d also are not limited to aluminum or aluminum alloy and also can be made of copper (Cu).
In addition, can use thin-film material, silicon substrate, regeneration silicon substrate, oxide-film, transparent resin material to substitute glass substrate 3 as supporting substrates.Specify as follows.
Thin-film material is organic class thin-film material, through resin bonding on the 1st wiring 5a, 5b, 5c, 5d.It is lower and do not have an advantage of the glass breach in cutting process as glass substrate 3 than glass substrate 3 that thin-film material has a cost.The regeneration silicon substrate is so owing to be that to use as supporting substrates be not that pure silicon substrate is good.The regeneration silicon substrate has the low advantage of cost.Silicon substrate or regeneration silicon substrate through resin bonding on the 1st wiring 5a, 5b, 5c, 5d.In addition, oxide-film can be formed on the 1st wiring 5a, 5b, 5c, the 5d without resin by low temperature CVD method or ion CVD method.And, on the 1st wiring 5a, 5b, 5c, 5d,, form dielectric films such as for example transparent epoxy resin material of the above thickness of 100 μ m or clear polyimides material with the screen printing method as transparent resin.Thin-film material, silicon substrate, regeneration silicon substrate, oxide-film, and each thickness of transparent resin material all be formed the required film thickness that is enough to satisfy the supporting substrates effect.In addition, on the 1st wiring 5a, 5b, 5c, 5d, be formed with oxide-film or nitride film in advance as diaphragm.
According to the present invention, the supporting substrates of supporting semiconductor chip can low-costly obtain the few BGA N-type semiconductor N device of manufacturing process owing to only adopt 1.
In addition, can obtain good electrical connection at semiconductor chip with between the conducting terminal that forms on the supporting substrates.
Claims (40)
1, a kind of semiconductor device is characterized in that, comprising:
The 1st dielectric film that on the surface of semiconductor chip, forms,
The 1st wiring that on described the 1st dielectric film, forms,
Be bonded in described semiconductor chip lip-deep supporting mass,
Cover the side of described semiconductor chip and the back side the 2nd dielectric film,
Is connected with described the 1st wiring and across described the 2nd dielectric film on described semiconductor chip backside, extend the 2nd connect up and
Cover the diaphragm of described the 2nd wiring.
2, semiconductor device according to claim 1 is characterized in that, the side of described semiconductor chip has rake.
3, semiconductor device according to claim 2 is characterized in that, the setting of described rake makes the length of described semiconductor chip surface portion less than the length of back side portion.
4, semiconductor device according to claim 1 is characterized in that, has the conducting terminal that is electrically connected with described the 2nd wiring.
According to each described semiconductor device in the claim 1～4, it is characterized in that 5, described the 2nd wiring is connected with the side of described the 1st wiring.
According to each described semiconductor device in the claim 1～4, it is characterized in that 6, described the 2nd wiring is connected with the back side of described the 1st wiring.
According to each described semiconductor device in the claim 1～4, it is characterized in that 7, described the 2nd wiring is connected with the side and the back side of described the 1st wiring.
8, semiconductor device according to claim 5 is characterized in that, the length of the adhesive portion of the back side of described the 1st wiring and described the 2nd wiring is greater than the length of the described the 1st side of connecting up.
According to each described semiconductor device in the claim 1～4, it is characterized in that 9, described the 2nd dielectric film is formed by single film.
10, according to each described semiconductor device in the claim 1～4, it is characterized in that,
Be provided with buffer unit between described the 2nd wiring and described the 2nd dielectric film.
11, a kind of manufacture method of semiconductor device is characterized in that, comprising:
Be formed with the 1st the wiring semiconductor crystal wafer on bonding supporting mass operation,
Along the border of a plurality of semiconductor chips to the back side of described semiconductor crystal wafer carry out etched operation,
With the 2nd dielectric film cover the side of described semiconductor chip and the back side operation,
Form the 2nd operation that connects up that is connected with described the 1st wiring and on described semiconductor chip backside, extends across described the 2nd dielectric film,
Form to cover described the 2nd wiring diaphragm operation and
The operation of cutting along the border of described a plurality of semiconductor chips.
12, the manufacture method of semiconductor device according to claim 11 is characterized in that, has the operation that forms rake in the side of described semiconductor chip.
13, the manufacture method of semiconductor device according to claim 12 is characterized in that, forms described rake by etching, makes the length of described semiconductor chip surface portion less than the length of back side portion.
14, the manufacture method of semiconductor device according to claim 11 is characterized in that, has the operation that forms the conducting terminal that is electrically connected with described the 2nd wiring.
15, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that, described the 2nd wiring is connected with the side of described the 1st wiring.
16, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that, described the 2nd wiring is connected with the back side of described the 1st wiring.
17, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that, described the 2nd wiring is connected with the side and the back side of described the 1st wiring.
18, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that, form described the 2nd dielectric film by single film.
19, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that having the operation that between described the 2nd wiring and described the 2nd dielectric film, forms buffer unit.
20, according to the manufacture method of each described semiconductor device in the claim 11～14, it is characterized in that having the operation that behind described the 1st dielectric film of etching the described the 1st back side of connecting up is exposed.
21, a kind of semiconductor device is characterized in that, comprising:
The protruding pad of metal, it is connected with circuit element in the semiconductor chip, and is formed near the side surface part on this semiconductor chip;
By bonding supporting mass, its covering comprises the surface element of the described semiconductor chip of the protruding pad of described metal;
Dielectric film, it is formed on the side surface part and the back side portion of described semiconductor chip; And
Metal line, it is connected with the protruding pad of described metal, and extends to back side portion and join with described dielectric film from the side surface part of described semiconductor chip.
22, semiconductor device according to claim 21 is characterized in that, described metal line is connected the side or the back side of the protruding pad of described metal.
23, semiconductor device according to claim 21 is characterized in that, described metal line is connected the side and the back side of the protruding pad of described metal.
According to claim 22 or 23 described semiconductor devices, it is characterized in that 24, the back side of the protruding pad of described metal and the length of the connecting portion between the described metal line are greater than the length of the side of the protruding pad of described metal.
25, according to each described semiconductor device in the claim 21～24, it is characterized in that the side surface part of described semiconductor chip has rake, make this semiconductor chip backside portion less than surface element.
26,, it is characterized in that described dielectric film has thickness about equally according to each described semiconductor device in the claim 21～25.
27,, it is characterized in that described dielectric film is made of cvd film, organic membrane according to each described semiconductor device in the claim 21～26.
According to each described semiconductor device in the claim 21～27, it is characterized in that 28, described supporting mass is any in glass, plastics, sheet material, silicon substrate, regeneration silicon substrate, oxide-film, the transparent resin material.
According to each described semiconductor device in the claim 21～28, it is characterized in that 29, described semiconductor chip is the ccd image sensor chip.
30, according to each described semiconductor device in the claim 21～29, it is characterized in that on described metal line, having conducting terminal.
31, semiconductor device according to claim 30 is characterized in that, the described metal line below described conducting terminal has buffer unit.
32, a kind of manufacture method of semiconductor device may further comprise the steps:
Preparation has the semiconductor crystal wafer of a plurality of semiconductor chips, and at the bonding supporting mass of face side of the described semiconductor crystal wafer that is formed with the 1st wiring, the wherein said the 1st connects up is the border of crossing between the adjacent semiconductor chip;
Described boundary member to described semiconductor wafer back carries out etching;
On the side surface part and back side portion of the semiconductor chip that exposes by described etching, form dielectric film;
Etching is carried out in described the 1st wiring, made it from described boundary separation;
Form the 2nd wiring, and make it connect up and to be connected, and extend to back side portion and join with described dielectric film from the side surface part of described semiconductor chip with the described the 1st;
Become semiconductor device one by one along described boundary segmentation.
33, a kind of manufacture method of semiconductor device may further comprise the steps:
Preparation has the semiconductor crystal wafer of a plurality of semiconductor chips, at the bonding supporting mass of face side of described semiconductor crystal wafer that is formed with the 1st wiring, wherein said the 1st wiring be with adjacent semiconductor chip between the border separate;
Described boundary member to described semiconductor wafer back carries out etching;
On the side surface part and back side portion of the semiconductor chip that exposes by described etching, form dielectric film;
Form the 2nd wiring, and make it connect up and to be connected, and extend to back side portion and join with described dielectric film from the side surface part of described semiconductor chip with the described the 1st;
Become semiconductor device one by one along described boundary segmentation.
34, according to the manufacture method of claim 32 or 33 described semiconductor devices, it is characterized in that, form the step of described the 2nd wiring, the 2nd wiring is connected with the side or the back side of the 1st wiring of exposing from the side surface part of described semiconductor chip.
35, according to the manufacture method of claim 32 or 33 described semiconductor devices, it is characterized in that, form the step of described the 2nd wiring, the 2nd wiring is connected with the back side and the side of described the 1st wiring of exposing from the side surface part of described semiconductor chip.
According to the manufacture method of each described semiconductor device in the claim 32～35, it is characterized in that 36, described etching step forms rake in the side surface part of described semiconductor chip, make described semiconductor chip backside portion less than surface element.
37, according to the manufacture method of each described semiconductor device in the claim 32～36, it is characterized in that, form the step of described dielectric film, make the thickness of this dielectric film become about equally thickness.
38, according to the manufacture method of each described semiconductor device in the claim 32～37, it is characterized in that, form the step of described dielectric film, form the dielectric film that constitutes by cvd film, organic membrane.
39, according to the manufacture method of each described semiconductor device in the claim 32～38, it is characterized in that, the step of bonding described supporting mass, any in described semiconductor wafer surface side bonds glass, plastics, sheet material, silicon substrate, regeneration silicon substrate, oxide-film, transparent resin material.
40, according to the manufacture method of each described semiconductor device in the claim 32～39, it is characterized in that, also comprise: the step that in described the 2nd wiring, forms conducting terminal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002120369 | 2002-04-23 | ||
| JP2002120369 | 2002-04-23 | ||
| JP2002185749 | 2002-06-26 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031229913A Division CN1257550C (en) | 2002-04-23 | 2003-04-23 | Semiconductor device and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1855469A true CN1855469A (en) | 2006-11-01 |
| CN100470781C CN100470781C (en) | 2009-03-18 |
Family
ID=37195490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100747015A Expired - Lifetime CN100470781C (en) | 2002-04-23 | 2003-04-23 | Semiconductor device and method of manufacturing same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5238985B2 (en) |
| CN (1) | CN100470781C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355058B (en) * | 2007-07-27 | 2010-09-22 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| CN102339844A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | Implementation method for silicon-free through hole low-cost image sensor packaging structure |
| CN102339843A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL123207A0 (en) * | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
| WO1999048143A2 (en) * | 1998-03-16 | 1999-09-23 | Koninklijke Philips Electronics N.V. | Method of manufacturing semiconductor devices with 'chip size package' |
| JP3839271B2 (en) * | 2001-05-01 | 2006-11-01 | 富士写真フイルム株式会社 | Solid-state imaging device and manufacturing method thereof |
-
2003
- 2003-04-23 CN CNB2006100747015A patent/CN100470781C/en not_active Expired - Lifetime
-
2009
- 2009-09-03 JP JP2009203621A patent/JP5238985B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355058B (en) * | 2007-07-27 | 2010-09-22 | 三洋电机株式会社 | Semiconductor device and method of manufacturing the same |
| CN102339844A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | Implementation method for silicon-free through hole low-cost image sensor packaging structure |
| CN102339843A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5238985B2 (en) | 2013-07-17 |
| JP2010016395A (en) | 2010-01-21 |
| CN100470781C (en) | 2009-03-18 |
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