CN1808904B

CN1808904B - Novel anti-noise high-speed domino circuit

Info

Publication number: CN1808904B
Application number: CN 200510110460
Authority: CN
Inventors: 赖练章; 汤庭鳌; 林殷茵
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2006-03-10
Filing date: 2006-03-10
Publication date: 2010-05-05
Anticipated expiration: 2026-03-10
Also published as: CN1808904A

Abstract

This invention belongs to large scale digital integration circuit technique field and relates to one new anti-noise domino digital logic circuit, which Uses one thin impulse generator effective control dynamic points to make the output dynamic point keep original level in the noise situation to realize strong anti-noise property and Adopts pull network parallel structure to eliminate current compactor to work under high frequency.

Description

A kind of novel anti-noise high-speed domino circuit

Technical field

The invention belongs to the large-scale digital ic technical field, be specifically related to a kind of anti-noise high-speed domino circuit that can be applicable to dynamic logic circuit.

Background technology

The dynamic CMOS logic is a kind of logical form that is widely used, and it proposes for service speed that improves circuit and the PMOS pipe series connection number that reduces the complex gate circuit on the basis of complementary cmos logic.Be the 4 input OR circuit that realize with complementary cmos as shown in Figure 1, Fig. 2 is its correspondence " no pin transistor " dynamic CMOS gate circuit (footless).The operation of complementary cmos door is static fully, and the operation of dynamic CMOS is worked under the clock step is coordinated.When CLOCK was low level, circuit was in pre-charging stage, and dynamic point F is charged to high level, and it is invalid at this moment to import, and must all be set to 0 level; When CLOCK began to be drawn for high level, circuit was in evaluate phase, and incoming level is effective, and dynamic point F is according to incoming level combination or dragged down or keep original level.This is the groundwork process of dynamic CMOS.The not gate that dynamic point connects later is to be unlikely to produce misoperation, promptly so-called domino circuit for correct cascade.But must see, though domino circuit has increased speed greatly and has reduced chip area, a fatal weakness is but arranged, and this weakness along with becoming more and more serious, the increase of the fan-in number of gate and the raising of integrated level is exactly its very weak noise resisting ability.As seen from Figure 2, when input noise amplitude during greatly to the switching threshold of pull-down NMOS pipe, the electric charge of dynamic point F will be leaked, and the complementary cmos circuit is under the situation that suitably sets pipe sizing, and its switching threshold can reach VDD/2; In addition, for many fan-ins dynamically or door, under the more and more littler situation of process, because the ratio that subthreshold current accounts for operating current is in continuous increase, so the electric charge of dynamic point F also may be leaked away by the subthreshold current of pulldown network.

In order to solve the antinoise problem of dynamic logic circuit, international academic community has proposed a lot of solutions.Be the dynamic logic gate circuit structure of a kind of band KEEPER that is widely used as shown in Figure 3.It is to rely on KEEPER that the charge compensation of dynamic point F is increased noise resisting ability.This structure can provide good noise resisting ability [1] when realizing simple gate, but gate circuit for complexity, dynamic or door as 16 inputs, 32 inputs, when increasing the KEEPER size, this simple structure will cause serious electric current warfare, the speed of circuit is descended greatly, and power consumption sharply increases.People such as Atila Alvandpour has proposed a kind of circuit structure with intelligent KEEPER [2] for this reason, as shown in Figure 4, this structure has two KEEPER that vary in size, PK2 and PK1, in the starting stage of evaluation, PK2 is invalid, PK1 provides dynamic point at the certain noise resisting ability of conversion stage, after evaluation is finished, if dynamic point by drop-down, PK2 will keep off state; If not by drop-down, PK2 is with conducting, so that stronger noise resisting ability to be provided to dynamic point.This structure makes circuit can not increase time-delay greatly because of the size that increases KEEPER (PK2), has therefore improved the performance of circuit.Yet owing to still have KEEPER in the dynamic point level transitions stage, increasing its size will influence speed, will influence noise resisting ability and reduce size, and speed and antimierophonic compromise still exist.Up to the present also there be not a kind of circuit structure and technology of abandoning the KEEPER structure fully at the design of many inputs dynamic gate.

The present invention will propose a kind of circuit structure that does not have the many input dynamic gates of being applicable to of KEEPER fully.

Summary of the invention

The object of the present invention is to provide a kind of domino circuit that is used for high noise resisting ability of having of dynamic logic circuit and high service speed.

High antinoise provided by the invention and high-speed domino circuit, the dynamic point of its pulldown network be directly output not, but by the output stage output that adds.Structurally, output stage mainly comprises a narrow-pulse generator and output dynamic point, and the output dynamic point is driven by the burst pulse that narrow-pulse generator produces.The output dynamic point is owing to be to be driven by narrow-pulse generator fully, so external noise wants to influence it and just must pass through narrow-pulse generator.Yet narrow-pulse generator has the overanxious function of certain noise, and when signal was imported, narrow-pulse generator had the burst pulse of normal amplitude with generation, can normally drive the output dynamic point; When the noise of outside is imported, narrow-pulse generator will produce the very little burst pulse of amplitude, be difficult to drive the output dynamic point, and the output dynamic point is well protected, thereby has very strong noise resisting ability.Based on such reason, also the output dynamic point can be called the internal dynamic point.On service speed, owing to abandoned the structure of KEEPER, do not have the electric current warfare in the circuit, so speed improves greatly.

Fig. 5 is the theory diagram of above summary of the invention.Wherein 200 is narrow-pulse generators, and F is the output dynamic point, the 210th, and pulldown network, the 220th, the preliminary filling fulgurite, 230 and 240 is respectively the preliminary filling fulgurite and the discharge tube of output dynamic point, G1, G2....Gn are the dynamic points of each pulldown network branch correspondence.Their concrete annexations are: dynamic point F is driven by narrow-pulse generator 200, and narrow-pulse generator 200 is by dynamic point G1, the G2....Gn control of clock CLOCK and pulldown network 210 each branch's correspondence; And preliminary filling fulgurite 220 is used in pre-charging stage each branch of pulldown network being charged.Each branch of each pulldown network is a kind of relation in parallel, and drop-down branch and narrow-pulse generator 200 and output dynamic point F then are series relationship.They have formed basic structure of the present invention.

The present invention is inner except having introduced, the notion of external dynamic point and pulse generator, structurally also introduced the method that reduces the dynamic point parasitic capacitance, exactly a big pulldown network is divided into 2,4 even 8 s' parallel connection.Fig. 5 has clearly expressed this conception of species.There are a lot of branches in pulldown network, when the input of circuit is a lot, just selects the structure than the multiple-limb parallel connection, imports the structure of then in parallel with few branch even single branch.Because ingenious design on circuit, more than the structure of the how drop-down branch parallel connection analyzed be can freely to expand fully, additionally do not increase too many pipe.Branched structure reduces parasitic capacitance greatly, thereby circuit has higher speed; Simultaneously, because branched structure has also reduced the gap of the time-delay under the worst time-delay and the worst noise situations, its noise resisting ability is also further improved.

Description of drawings

Fig. 1 is 4 input complementary cmos logic sum gate circuit.

Fig. 2 is corresponding dynamic CMOS OR circuit.

Fig. 3 is many fan-ins dynamic circuit of common band KEEPER.

Fig. 4 is the many fan-ins dynamic circuit with intelligent KEEPER.

Fig. 5 is the circuit structure general diagram of the tape pulse generator output stage of proposition.

Fig. 6 is the circuit diagram (Fig. 5 special case) of the band burst pulse output stage of single pulldown network.

Fig. 7 is the circuit diagram (Fig. 5 special case) of the band burst pulse output stage of two pulldown network parallel connections.

Fig. 8 is the circuit diagram (Fig. 5 special case) of the band burst pulse output stage of four pulldown network parallel connections.

Fig. 9 is the HSPICE analog waveform figure of or door dynamic with 16 inputs of Fig. 7 realization.

Figure 10 is the 16 narrow pulse waveform figure that input is dynamic or door produces corresponding to different input voltage amplitudes that realize with Fig. 7.

Figure 11 compares for 16 inputs of using Fig. 3, Fig. 6 and Fig. 7 to realize the worst time-delay dynamic or door, and abscissa is the transistorized W/L ratio of each or student's pull-up network.

Figure 12 is the antinoise curve of or door dynamic with 32 inputs of Fig. 3, Fig. 6 and Fig. 7 realization.

Number in the figure: the 210th, pulldown network, the 220th, the preliminary filling fulgurite, 230 and 240 is respectively the preliminary filling fulgurite and the discharge tube of output dynamic point;

PMOS pipe

1,2 is the switching tube of narrow-pulse generator, NMOS pipe 3 is the discharge tube of narrow-pulse generator, NMOS pipe 4 following trombone slides for the output dynamic point,

PMOS pipe

5,6 is the preliminary filling fulgurite, 10 is pulldown network, 11 is delay cell, PMOS pipe 16 is the switching tube of the pulse generator of pulldown network 12 correspondences, PMOS pipe 15 is the switching tube of the pulse generator of pulldown network 13 correspondences,

PMOS pipe

17,18,19,20 is the switching tube of the pulse generator of four pulldown network correspondences in parallel, and dotted line 21,22 begins to form and arrive peaked time point for burst pulse.

Embodiment

Fig. 1 to Fig. 4 has done brief description in background information.

Fig. 5 is the structure general diagram that proposes according to operation principle, elaborates in the summary of the invention in front.Fig. 6 is one of Fig. 5 special case, promptly uses the particular circuit configurations figure of the structure realization of single pulldown network (pulldown network has only a branch).Wherein G is the external dynamic point, and F is output dynamic point, just an internal dynamic point; Narrow-pulse generator mainly comprises

PMOS pipe

1,2, NMOS pipe 3 and time delay network 11; And 10 are pulldown network.Their annexation is: clock reaches the grid of NMOS pipe 3 and PMOS pipe 1 through the time-delay of time delay network 11; 1,2 series connection of PMOS pipe; The drain electrode of the drain electrode of PMOS pipe 2 and NMOS pipe 3 is connected together, and the following trombone slide that drives output dynamic point F is a NMOS pipe 4; The grid of PMOS pipe 2 is driven by dynamic point G; The formation of output dynamic point F: PMOS pipe 5 and NMOS pipe 4 are serially connected, and middle tie point promptly is the output dynamic point, and wherein PMOS pipe 5 is directly driven by clock, and NMOS pipe 4 is driven by the public drain electrode tie point of PMOS pipe 2 with NMOS pipe 3.The concrete course of work is as follows: when CLOCK became low level, when promptly entering pre-charging stage, dynamic point G, F all were charged as high level gradually; Simultaneously, because the time-delay of time delay network, P point does not enter low level state, but remains on the high level state (through just entering low level state certain time of delay) in previous cycle, thus the U point by NMOS manage 3 drop-down be low level.When CLOCK was drawn to high level again by the low level after stable gradually, circuit entered evaluate phase, because identical, P names a person for a particular job and is in low level state (through just entering high level state certain time of delay), and PMOS pipe 1 is opened at this moment; Here it should be noted that, pulldown network 10 must raise simultaneously or be close to and begin effectively to receive external signal simultaneously at CLOCK, if having at least one to be input as high level, internal dynamic point F is by drop-down, PMOS manages 2 conductings, power vd D begins through 1 and 2 pair of U point charging of PMOS pipe, and the time of charging is depended on the setting of time delay network, after high level arrives the P point, PMOS pipe 1 will turn-off, and NMOS manages 3 with conducting, and the electric charge of U point parasitic capacitance will be released, and level is replied and is " 0 ".In this process, naming a person for a particular job at U produces the burst pulse of a moment, and drives output dynamic point G, makes it be " 0 " by drop-down.If all inputs of pulldown network 10 are low level, then PMOS pipe 2 will keep off state, and U names a person for a particular job and can not be recharged, and promptly can not produce burst pulse.Finishing of above all stage is a complete cycle.

Fig. 7 and Fig. 8 also are the special cases of Fig. 5, are the circuit of band narrow-pulse generator of the structure realization of in parallel with two pulldown network respectively and four pulldown network parallel connections.Its operation principle and Fig. 6 are similarly, but the parasitic capacitance that a plurality of drop-down branches are sent away external dynamic point reduces, thereby the worst case time-delay is reduced; Simultaneously owing to the difference between the time-delay of worst case time-delay and worst-case noise also has been reduced, so its noise resisting ability is bigger.16 inputs or door design in can select two branched structures of Fig. 7 for use, and 32 inputs or Men Ze select for use the structure of Fig. 8 four branches more suitable.From these two figure as can be seen, the PMOS pipe in parallel that needs only corresponding increase narrow-pulse generator from the multiple-limb that singly is branched off into Fig. 7, Fig. 8 of Fig. 6 is just passable, as PMOS pipe 16 and

PMOS pipe

18,19,20, structurally has extraordinary extensibility, can very freely select branch in parallel according to the number that door leaf is gone into, and can not increase too many transistor, this is that the present invention is local very cleverly.

Simulation and checking

More than proposed particular circuit configurations of the present invention, will provide the HSPICE analog result to verify above principle and it is analyzed in this part.Simulation is in the CMOS technology of 0.18 μ m/1.8V and carries out under 55 ℃ environment.As shown in Figure 9, be the signal waveform analog result of or door dynamic with one 16 input domino of Fig. 7 realization.From simulation as can be seen, each effectively input (INPUT be high) all correspondence a burst pulse (V (U)), and both time-delays are very little; The voltage V (F) that internal dynamic point F is ordered by burst pulse normal drop-down be low level.Dotted line 21 to the time interval between the dotted line 22 is the charging interval that second burst pulse produces, and from the CLOCK and V (P) signal in this time interval, when CLOCK just entered high level, the level V (P) that P is ordered still was in low level really.And same, when CLOCK had just entered low level, V (P) also still was in high level.Figure 10 has provided the oscillogram with the burst pulse of 16 inputs of Fig. 7 realization or door generation, can see, when input signal when 1.8V constantly is reduced to 534mV, burst pulse will be decreased to the threshold voltage of NMOS pipe with bigger amplitude, 360mV has just verified the overanxious function of noise of pulse generator.These two analog results have been verified the feasibility and the correctness of principle well.

In addition, when proposing principle and specific implementation method in front, pointed out once that circuit that the present invention and a lot of document are proposed compared and have better noise resisting ability and faster speed, the HSPICE proof of analog result of Figure 11 and Figure 12 this point.Figure 11 be the dynamic OR circuit of 16 inputs that realizes with Fig. 6, Fig. 7 with realize with Fig. 3 respectively with 16 inputs of different big or small KEEPER dynamically or the comparison of the worst time-delay of door.The wide length of KEEPER has been marked on the figure.Many inputs the worst time-delay dynamic or door occurs under the situation of having only a parallel transistor conducting, as shown in Figure 11, owing to eliminated warfare, the worst time-delay of the circuit structure that the present invention proposes is very little, and adopts the structure of many pulldown network parallel connections to make the worst time-delay become littler.Figure 12 is above each or the door antinoise curve [3] under the worst noise situations when fan-in is increased to 32bit.So-called antinoise curve is the curve of one group of noise amplitude with respect to the noise time width, Regional Representative's more than curve is noise level to circuit danger, and following Regional Representative's is safe noise level, and shared big more its noise resisting ability of just representing of area of antinoise curve and abscissa and ordinate is strong more.As can be seen, circuit engineering proposed by the invention has very strong noise resisting ability from the figure, and the circuit of two pulldown network has better noise resisting ability than the circuit of single pulldown network, has verified conclusion that the front proposed and analysis result thus.

List of references

[1]Li?Ding，et?al.“On?Circuit?Techniques?to?Improve?Noise?Immunity?of?CMOS?DynamicLogic”，IEEE?Trans.VLSI?Syst.，vol.12，pp.910-924，September?2004.

[2]Atila?Alvandpour，et?al.“A?Sub-130-nm?Conditional?Keeper?Technique”，IEEE?J.Solid-StateCircuits，vol.37，pp.633-638，May?2002.

[3]G.A.Katopis，“Delta-I?noise?specification?for?a?high-performance?computing?machine”，Proc.IEEE，vol.73，pp.1405-1415，Sept.1985.

Claims

1. an anti-noise high-speed domino circuit is characterized in that output stage mainly comprises a narrow-pulse generator and output dynamic point, and the burst pulse that the narrow-pulse generator that the output dynamic point is produced by narrow-pulse generator produces drives; This circuit is connected to form through circuit by narrow-pulse generator (200), pulldown network (210), the first preliminary filling fulgurite (220), the second preliminary filling fulgurite (230) and discharge tube (210); Wherein, output dynamic point (F) is driven by narrow-pulse generator (200), and narrow arteries and veins generator (200) is by dynamic point G1, the G2 of each breakout correspondence of clock Clock and pulldown network (210) ... Gn control; The first preliminary filling fulgurite (220) is used in pre-charging stage each branch of pulldown network being charged; Each branch's parallel connection of pulldown network, the branch of pulldown network connects with narrow-pulse generator (200) and output dynamic point F.

2. domino circuit according to claim 1, but it is characterized in that the extend type that branches into of described pulldown network.

3. domino circuit according to claim 1, it is characterized in that described pulldown network only has a branch, its narrow-pulse generator (200) is made up of PMOS pipe (1), the 2nd PMOS pipe (2), the 3rd NMOS pipe (3) time delay network (11), wherein, clock reaches the grid of the 3rd NMOS pipe (3) and PMOS pipe (1) through the time-delay of time delay network (11); The one PMOS pipe (1), the 2nd PMOS pipe (2) series connection; The drain electrode of the drain electrode of the 2nd PMOS pipe (2) and the 3rd NMOS pipe (3) is connected together, and the following trombone slide that drives output dynamic point (F) is the 4th a NMOS pipe (4); The grid of the 2nd PMOS pipe (2) is driven by dynamic point (G); Output dynamic point (F) is constructed as follows: the 5th PMOS pipe (5) and the 4th NMOS pipe (4) are serially connected in a bit, middle tie point promptly is the output dynamic point, wherein, the 5th PMOS pipe (5) is directly driven by clock, and the 4th NMOS pipe (4) is driven by the public drain electrode tie point of the 2nd PMOS pipe (2) and the 3rd NMOS pipe (3).

4. domino circuit according to claim 3 is characterized in that increasing PMOS pipe in parallel (16) in the described narrow-pulse generator, promptly is extended to the circuit with two branch's pulldown network; Increase a plurality of PMOS pipes, promptly be extended to the circuit of multiple-limb pulldown network.