CN1797376A - Control method for accessing dynamic random access memory - Google Patents
Control method for accessing dynamic random access memory Download PDFInfo
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- CN1797376A CN1797376A CN 200410104125 CN200410104125A CN1797376A CN 1797376 A CN1797376 A CN 1797376A CN 200410104125 CN200410104125 CN 200410104125 CN 200410104125 A CN200410104125 A CN 200410104125A CN 1797376 A CN1797376 A CN 1797376A
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Abstract
The invention is an access control method of a dynamical random access memory (DRAM), applied to a substrate provided with at least a first or second specification DRAM module socket and a BIOS program for the substrate to control the access to the first or second DRAM module, making the BIOS prestore the related data of the first or second DRAM module; successively, making the substrate execute an initializing program according to the BIOS program, making a memory controller access the DRAM module and finally making the memory controller judge the related data of the DRAM module for the memory to control the access of the module mounted in the DRAM module according to the read related data of the DRAM module.
Description
Technical field
The invention relates to a kind of access control method of dynamic RAM, particularly about a kind of access control method that can supply the dynamic RAM of Memory Controller Hub access DDR-I DRAMDIMM or DDR-II DRAM DIMM with identical bios program.
Background technology
Dynamic RAM (Dynamic Random Access Memory; DRAM) reach the low characteristic of cost greatly because of having storage volume, therefore, many electronic products (for example desktop PC, notebook computer, server or workstation etc.) all adopt it to be used as best internal memory solution, the indispensable part of electronic product especially.
Moreover, for improving the transmission speed of DRAM, therefore the DRAM dealer also constantly releases different DRAM, DDR-I (Double Data Rate-I) DRAM and DDR-IIDRAM for example, and by Dual-Inline-Memory-Modules (Dual In-line Memory Modules; DIMM) slot (Slot) inserts these two kinds of DRAM DIMM on the substrate (Base Board), and generally speaking, different DRAM (being DDR-I DRAM or DDR-II DRAM) DIMM promptly has corresponding dimm socket.
For cooperating the DRAM module of DDR-I DRAM DIMM (hereinafter to be referred as DDR-I DIMM) and two kinds of specifications of DDR-IIDRAM DIMM (hereinafter to be referred as DDR-II DIMM), Intel Company also releases the chipset Lindenhurst that can support DDR-I DIMM and DDR-II DIMM, and it includes a kind of Memory Controller Hub (abbreviating the Lindenhurst chipset as memory chip group Lindenhurst at this).Show the substrate 7 of use DDR-IDRAM dimm socket and the substrate 7 ' required basic structure block schematic diagram of DDR-II DRAM dimm socket as Fig. 1 (A) and Fig. 1 (B).Two substrates (7,7 ') use identical Memory Controller Hub 1 (for example memory chip group Lindenhurst of Intel Company's release) respectively, and distinctly use DDR-IDIMM slot zone 2 and DDR-II dimm socket district 2 ', dimm socket district herein (2,2 ') all have 8 dimm sockets (20,21 ..., 27 and 20 ', 21 ' ..., 27 '), and two dimm socket districts (2,2 '), 6 dimm sockets wherein distinctly are equipped with DDR-IDRAM DIMM 3 and DDR-II DRAM DIMM 4.
Because DDR-I DRAM DIMM 3 and DDR-II DRAM DIMM 4 and incompatible, and both hardware design are also inequality, so though DDR-I DRAM DIMM 3 and DDR-IIDRAM DIMM 4 all can be supported by the memory chip group Lindenhurst of Intel Company, yet, under situation about can't support simultaneously, which specification promptly must go up at two substrates (7,7 ') different bios programs (5,5 ') is installed, be make this memory chip group Lindenhurst judge to be subjected to its dimm socket district (2,2 ') that carries out access control object.
As from the foregoing, this practice obviously causes the inconvenience of processes such as the electronic product dealer writes at bios program design, bios program, tester substrate.Therefore, how allowing the electronic product dealer only need utilize identical bios program can arbitrarily design and produce the substrate of supporting DDR-I DIMM or DDR-II DIMM with this memory chip group Lindenhurst, promptly is the problem of present required solution.
Summary of the invention
For solving the shortcoming of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of access control method of dynamic RAM, can make Memory Controller Hub that DDR-I DRAM DIMM or DDR-II DRAM DIMM are carried out access control by same bios program.
For reaching above-mentioned and other purpose, the invention provides a kind of access control method of dynamic RAM.The access control method of dynamic RAM of the present invention, be applied in and be provided with at least one first specification dynamic RAM (DRAM) module slot or at least one second specification DRAM module slot, Memory Controller Hub and Basic Input or Output System (BIOS) (BasicInput/Output System, BIOS) substrate of program, a DRAM module that is installed in the first specification DRAM module slot or the 2nd DRAM module that is installed in the second specification DRAM module slot are carried out access control for this substrate, this method may further comprise the steps at least: make this bios program the prestore first specification DRAM module and the second specification DRAM module related data; Make this substrate carry out internal memory initialization program (MemoryInitialization) according to this bios program; Make this Memory Controller Hub in the internal memory initialization program, memory modules set on this substrate be carried out access, and memory modules is carried out its SPD (Serial Present Detect) data by SM (System Management) bus with I2C agreement (Protocol) read, judge that according to memory body pattern field (the Memory Type Field) value of DRAM module SPD data being installed on this DRAM module slot is a DRAM module or the 2nd DRAM module; And make this Memory Controller Hub read the DRAM module related data corresponding from this bios program with this DRAM module with this DRAM module, according to the DRAM module related data that is read the DRAM module that is installed in this DRAM module slot is carried out access control for Memory Controller Hub.
The inconvenience of processes such as the access control method of dynamic RAM of the present invention obviously can effectively solve when having Memory Controller Hub access DDR-I DIMM or DDR-II DIMM now and write at bios program design, bios program, tester substrate.
Description of drawings
Fig. 1 (A) and Fig. 1 (B) show that respectively use DDR-I DIMM and DDR-II DIMM are as the required basic structure block schematic diagram of the substrate of memory modules;
The basic structure block schematic diagram that the access control method of Fig. 2 display application dynamic RAM of the present invention makes Memory Controller Hub can carry out access control to DDR-I DIMM or DDR-II DIMM with same bios program; And
Fig. 3 shows the process step synoptic diagram of the access control method of dynamic RAM of the present invention.
Embodiment
Embodiment
Fig. 2 is an access control method of using dynamic RAM of the present invention, the basic structure block schematic diagram that makes Memory Controller Hub can carry out access control to DDR-I DRAM DIMM (being designated hereinafter simply as DDR-I DIMM) or DDR-II DRAM DIMM (being designated hereinafter simply as DDR-II DIMM) with same bios program.In the present embodiment, the required member of the access control method of dynamic RAM of the present invention comprises: Memory Controller Hub 1, bios program 6 and DDR-I dimm socket district 2 or DDR-II dimm socket district 2 ', these members are provided in a side of on the substrate (not marking), can carry out access control for the electronic installation (for example notebook computer, desktop PC, server or workstation) that this substrate is installed to DDR-I DIMM or DDR-II DIMM with identical bios program 6.What this must propose explanation be, this substrate has other various functional units in addition, for simplifying accompanying drawing and explanation, structure herein only shows the member relevant with the present invention, the member that other is irrelevant, for example the hardware configuration of south bridge and north bridge etc. does not show in the accompanying drawings.
DRAM on the electronic installation substrate all uses identical DRAM specification, just, this substrate has unified DRAM specification, present embodiment is the example explanation with DDR-I DRAM or DDR-IIDRAM promptly, and is provided with corresponding Dual-Inline-Memory-Modules (Dual In-line Memory Modules in response to different DRAM specifications on substrate; DIMM) slot (DIMMSlot), just, the DIMM outward appearance of different DRAM specification correspondences is inequality, so that the function of fool proof design to be provided, so the DRAM specification is installed correctly.
The DDR-I DRAM module slot zone 2 of present embodiment and DDR-II DRAM module slot zone 2 ' all have 8 dimm sockets (20,21 ..., 27 and 20 ', 21 ' ..., 27 '), wherein, the dimm socket of this DDR-I DRAM module slot zone 2 (20,21,22,24,25 and 26) is respectively installed a DDR-I DIMM 3, this DDR-II dimm socket district 2 ' dimm socket (21 ', 22 ', 23 ', 25 ', 26 ' and 27 ') DDR-IIDIMM4 respectively is installed.Each DIMM (20,21,22,24,25,26 and 21 ', 22 ', 23 ', 25 ', 26 ', 27 ') distinctly have for example storer of EEPROM (not marking), be used to store the DIMM parameter, just SPD (Serial Presence Detect; SPD) data, and the SPD data of DIMM comprises the field of internal memory model (Memory Type), still thus field value learn that this DIMM is DDR-I or DDR-II.Moreover, each dimm socket all has a SM (System Management) bus, it has 2 signal line, the one, data line (DataLine), another is clock line (Clock Line), being connected to this slot, it is that system passes through the SM bus and uses I2C agreement (Protocol) to go access DIMM SPD data, and the I2C address standard of the specification specifies dimm socket of DIMM is A0H, A2H, A4H, A6H, A8H, AAH, ACH and AEH.Moreover the quantity of this dimm socket is not defined as eight shown in the present embodiment, can be six or four etc. yet, decides on embodiment.
Moreover, the Memory Controller Hub 1 of present embodiment is meant the memory chip group Lindenhurst of Intel Company, because substrate only has the DRAM specification of single kind, so BIOS only need scan each dimm socket (20,21 ..., 27 and 20 ', 21 ' ..., 27 ') the SPD data in internal memory model field (Memory Type Filed), the DRAM DIMM specification that just is installed in as can be known on this dimm socket is DDR-I DIMM 3 or DDR-II DIMM 4.The SPD data has its standard definition (it fixes on PC SDRAM Serial Presence Detect), and wherein the data of Byte 2 is represented the internal memory model, and its value 07 is represented DDR-I DIMM; Its value 08 is represented DDR-II DIMM.
As from the foregoing, BIOS with scan mode read each dimm socket (20,21 ..., 27 and 20 ', 21 ' ..., 27 ') Byte 2 (MemoryType Field) value of the stored SPD data of storer, can judge the DRAM DIMM specification that is installed at present on the dimm socket, and this bios program 6 reads and the corresponding data of this DRAM DIMM specification (just program or data) certainly, and the sub-device of powering is promptly finished internal memory initialization smoothly in boot program.Because above-mentioned bios program and computer opening initialize routine are necessary member and the program of general computer system before operation, also are the technology that computer technician is known, its operation function and inner structure are not explained below therefore.
Fig. 3 shows the process step synoptic diagram of the access control method of dynamic RAM of the present invention.As shown in the figure, at first carry out step S1, because the characteristic difference of DDR-I DIMM and DDR-IIDIMM, so the demand of hardware wiring is promptly inequality, for example the I2C address of DIMM CS (ChipSelect) configuration, dimm socket, clock control mode, CKE pin (Pin) pattern are for sharing or independence and DIMM quantity etc., so need in this bios program 6, to add in advance the related data of DDR-I DIMM 3 and DDR-II DIMM 4, then proceed to step S2 according to the characteristic of DDR-I DRAM and DDR-IIDRAM.
In this step S2, make the substrate of this electronic installation carry out the internal memory initialization program according to this bios program 6, the dimm socket (just DDR-II dimm socket district 2 ') that makes this Memory Controller Hub 1 to set being used on this substrate the dimm socket (DDR-I dimm socket district 2 just) of DDR-I DIMM 3 is installed in initialize routine or be used to install DDR-II DIMM 4 carries out access, and all DRAM dimm sockets are carried out the SPD data read, just BIOS with scan mode (by I2C address A0H, A2H, A4H, A6H, A8H, AAH, ACH and AEH scan dimm socket successively), obtain the data value of SPD internal memory model field (being Byte 2), and judge that according to this data value dimm socket district is DDR-I DIMM 3 or DDR-II DIMM 4, then carry out step S3.
In this step S3, BIOS is by the data value that reads SPD internal memory model field (being Byte 2), as judging that whether dimm socket is that (just, these Byte 2 data value are 07 to represent the dimm socket district be DDR-I DIMM for DDR-I DIMM 3 or DDR-II DIMM4; These Byte 2 data value are 08, and to represent the dimm socket district be DDR-II DIMM).So, then proceed to step S4 if this Memory Controller Hub 1 judges that present DRAM module is DDR-II DIMM 4; Otherwise, then carry out step S5.
In this step S4, make this Memory Controller Hub 1 read the DRAM DIMM related data corresponding from this bios program 6 with this DDR-II DIMM specification to judge DDR-II DIMM specification, for example, be used to declare the variable and the program segment of DDR-II DIMM hardware circuit layout, according to the DDR-II DIMM related data that reads the DDR-II DIMM that is installed in this dimm socket carried out access control for this Memory Controller Hub 1.
In this step S5, make this Memory Controller Hub 1 judge DDR-I DIMM specification and read the DRAM DIMM related data corresponding with this DDR-I DIMM specification from this bios program 6, for example, be used to declare the variable and the program segment of DDR-I DIMM hardware circuit layout, according to the DDR-I DIMM related data that reads, the DDR-I DIMM that is installed in this dimm socket is carried out access control for this Memory Controller Hub 1.
In sum, the access control method of dynamic RAM of the present invention is the characteristic according to DDR-I DIMM and DDR-II DIMM, the related data that in original bios program, adds DDR-I DIMM and DDR-II DIMM, and in the internal memory initialization program, make BIOS with scan mode (by I2C address A0h, A2h, AEh scans dimm socket successively) the SPD data of dimm socket is read, why can judge this DRAM specification, so make the electronic product dealer can arbitrarily design and produce the substrate of supporting DDR-I DIMM or DDR-II DIMM with Memory Controller Hub, design at bios program so the access control method of dynamic RAM of the present invention obviously can effectively solve when having Memory Controller Hub access DDR-I DIMM or DDR-II DIMM now by single bios program, bios program writes, the inconvenience of processes such as tester substrate.
Claims (9)
1. the access control method of a dynamic RAM, be applied in the substrate that is provided with a kind of slot, Memory Controller Hub and Basic Input or Output System (BIOS) program of specification at least one first specification DRAM module slot and at least one second specification DRAM module slot, for this substrate a kind of DRAM module in the DRAM module that is installed in this first specification DRAM module slot and the 2nd DRAM module that is installed in the second specification DRAM module slot is carried out access control, it is characterized in that this method may further comprise the steps at least:
Make this bios program prestore a DRAM module and the 2nd DRAM module related data;
Make this substrate carry out the internal memory initialization program according to this bios program;
Make this Memory Controller Hub in the internal memory initialization program, DRAM module slot set on this substrate is carried out access, and read the data value of the internal memory model field that the DRAM module stores by DRAM module I 2C address, judged that being installed in this DRAM module slot is a kind of DRAM module in a DRAM module and the 2nd DRAM module; And
Make this Memory Controller Hub read the DRAM module related data corresponding from this bios program with this DRAM module with this DRAM module, according to the DRAM module related data that reads, the DRAM module that is installed in this DRAM module slot is carried out access control for Memory Controller Hub.
2. access control method as claimed in claim 1 is characterized in that this memory module slot is meant dimm socket.
3. access control method as claimed in claim 2 is characterized in that, the data value of the internal memory model field that this DRAM module stores is meant Byte 2 data value on the SPD data.
4. access control method as claimed in claim 3 is characterized in that, these Byte 2 data value are 07, and then representing the DRAM module is DDR-I DIMM; These Byte 2 data value are 08, and then representing the DRAM module is DDR-II DIMM.
5. access control method as claimed in claim 3 is characterized in that, this DRAM module slot is to use I2C protocol access SPD data by the SM bus.
6. access control method as claimed in claim 3 is characterized in that, this SPD data is to be stored among the EEPROM.
7. access control method as claimed in claim 1 is characterized in that, a DRAM module is meant DDR-I DRAM DIMM.
8. access control method as claimed in claim 1 is characterized in that, the 2nd DRAM module is meant DDR-II DRAM DIMM.
9. access control method as claimed in claim 1 is characterized in that, Memory Controller Hub is meant the memory chip group Lindenhurst of Intel Company.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101041255A CN100437532C (en) | 2004-12-30 | 2004-12-30 | Control method for accessing dynamic random access memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004101041255A CN100437532C (en) | 2004-12-30 | 2004-12-30 | Control method for accessing dynamic random access memory |
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| CN1797376A true CN1797376A (en) | 2006-07-05 |
| CN100437532C CN100437532C (en) | 2008-11-26 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957726A (en) * | 2009-07-16 | 2011-01-26 | 恒忆有限责任公司 | Phase transition storage in the dual inline type memory module |
| CN102081586A (en) * | 2011-01-25 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Multiple I2C (Inter-IC) slot circuit system and method for transmitting I2C signal |
| CN102906717A (en) * | 2010-05-28 | 2013-01-30 | 惠普发展公司，有限责任合伙企业 | Initializing a memory subsystem of a management controller |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3761635B2 (en) * | 1996-07-12 | 2006-03-29 | 株式会社ダックス | Memory board, memory access method, and memory access device |
| EP1306849B1 (en) * | 2001-10-19 | 2008-02-27 | Samsung Electronics Co., Ltd. | Devices and methods for controlling active termination resistors in a memory system |
| US20030158995A1 (en) * | 2002-02-15 | 2003-08-21 | Ming-Hsien Lee | Method for DRAM control with adjustable page size |
| CN1479209A (en) * | 2003-07-25 | 2004-03-03 | 北京港湾网络有限公司 | Method of maintaining stored information by synchronous dynamic random access memory |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957726A (en) * | 2009-07-16 | 2011-01-26 | 恒忆有限责任公司 | Phase transition storage in the dual inline type memory module |
| US9576662B2 (en) | 2009-07-16 | 2017-02-21 | Micron Technology, Inc. | Phase change memory in a dual inline memory module |
| US10437722B2 (en) | 2009-07-16 | 2019-10-08 | Micron Technology, Inc. | Phase change memory in a dual inline memory module |
| US11494302B2 (en) | 2009-07-16 | 2022-11-08 | Micron Technology, Inc. | Phase change memory in a dual inline memory module |
| CN102906717A (en) * | 2010-05-28 | 2013-01-30 | 惠普发展公司，有限责任合伙企业 | Initializing a memory subsystem of a management controller |
| CN102906717B (en) * | 2010-05-28 | 2016-05-04 | 惠普发展公司，有限责任合伙企业 | Memory sub-system to Management Controller initializes |
| US9870233B2 (en) | 2010-05-28 | 2018-01-16 | Hewlett Packard Enterprise Development Lp | Initializing a memory subsystem of a management controller |
| CN102081586A (en) * | 2011-01-25 | 2011-06-01 | 鸿富锦精密工业（深圳）有限公司 | Multiple I2C (Inter-IC) slot circuit system and method for transmitting I2C signal |
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| CN100437532C (en) | 2008-11-26 |
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Effective date of registration: 20181120 Address after: Building 1, No. 231 Jiulong Road, Caoqiao Street, Pinghu City, Jiaxing City, Zhejiang Province Patentee after: Jiaxing Jinxu Medical Technology Co., Ltd. Address before: Taipei City, Taiwan, China Patentee before: Inventec Corporation |
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Granted publication date: 20081126 Termination date: 20181230 |
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