CN1767070A - Shift register circuit - Google Patents

Shift register circuit Download PDF

Info

Publication number
CN1767070A
CN1767070A CN 200510099226 CN200510099226A CN1767070A CN 1767070 A CN1767070 A CN 1767070A CN 200510099226 CN200510099226 CN 200510099226 CN 200510099226 A CN200510099226 A CN 200510099226A CN 1767070 A CN1767070 A CN 1767070A
Authority
CN
China
Prior art keywords
source
drain electrode
couples
transistorized
grid
Prior art date
Application number
CN 200510099226
Other languages
Chinese (zh)
Other versions
CN100495576C (en
Inventor
魏俊卿
吴仰恩
林威呈
Original Assignee
友达光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友达光电股份有限公司 filed Critical 友达光电股份有限公司
Priority to CNB2005100992262A priority Critical patent/CN100495576C/en
Publication of CN1767070A publication Critical patent/CN1767070A/en
Application granted granted Critical
Publication of CN100495576C publication Critical patent/CN100495576C/en

Links

Abstract

The invention relates to a shift register circuit, which possesses a plurality of series-connected stage shift register including a first transistor with the grid and the first resource/leakage connecting with output signal of the front stage register. The second transistor with the grid is connected with the second resource/leakage electrode of the first transistor; the first resource/leakage electrode is connected with a first clock signal, the second resource/leakage electrode is connected with the output end of the second resource/leakage electrode. The first lower module is coupled with the output end and the first clock signal; when the output signal and the first clock signal of the front stage shift register are connected with the low voltage level, it coupled with the first voltage level. The second lower module is coupled with the output end and the second clock signal; when the output signal and the second clock signal of the front stage shift register are connected with the low voltage level, it coupled with the first voltage level.

Description

Shift-register circuit

Technical field

The present invention relates to a kind of driving circuit of LCD, particularly the driving circuit of the shift register in a kind of driving circuit of LCD.

Background technology

Design of drive circuit has been become a kind of major technique of following LCD on the glass substrate of display panels, its biggest advantage is to save the cost of drive IC.With TFT thin film transistor monitor, the technology of amorphous silicon has become present main flow, but with amorphous silicon film transistor, its instability as the voltage drift of critical voltage, has become problem maximum on the circuit design.Please refer to Fig. 1, Fig. 1 be the thin film transistor (TFT) of a 300um technology at 80 ℃, under the different running times, the synoptic diagram of voltage and electric current.Curve 11,12,13,14 and 15 is respectively the voltage-current curve figure of thin film transistor (TFT) after using 0,2,4,6 and 8 hour.Can find by Fig. 1, thin film transistor (TFT) is long more service time, the situation of the voltage drift of its critical voltage is just obvious more, and this voltage drift just may cause the shift register on the driving circuit to export incorrect signal, and produces the problem that LCD can't normally show.

Please refer to Fig. 2, Fig. 2 is the circuit diagram of an existing shift register.Conducting makes its critical voltage produce voltage drift to transistor T 21 with the voltage of the lasting reception of T22 VDD, and causes output terminal N can't maintain normal closed condition (off state).Please refer to Fig. 3, Fig. 3 is the output signal synoptic diagram of shift register among Fig. 2.When curve 31 has just been brought into use for the shift register among Fig. 2, the volt-time curve of output terminal N.32 of curves are the volt-time curve that the shift register among Fig. 2 uses output terminal N after 6 hours.Can be found that by curve 32 existing shift register is after long-time the use, its output end signal can can't remain on a closed condition fully, just may cause the incorrect output of show image concerning LCD.

Summary of the invention

Purpose of the present invention is for providing a kind of shift register circuit that reduces the voltage drift situation of transistor generation.

The invention provides a kind of shift register circuit, shift register with a plurality of serial connection levels, comprise: a first transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein first of the grid of this first transistor and this first transistor source/drain electrode couples the output signal of a prime shift register.One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this transistor seconds couples second source/drain electrode of this first transistor, first source/drain electrode of this transistor seconds couples one first clock signal, and second source/drain electrode of this transistor seconds couples an output terminal.One first drop-down module couples this output terminal and this first clock signal, when the output signal of this prime shift register and this first clock signal are low voltage level, couples this output terminal to one first voltage level.One second drop-down module couples this output terminal and a second clock signal, when the output signal of this prime shift register and this second clock signal are low voltage level, couples this output terminal to this first voltage level.

The present invention more provides a kind of shift register circuit, shift register with a plurality of serial connection levels, comprise: a first transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, first of the grid of this first transistor and this first transistor source/drain electrode couples the output signal of a prime shift register.One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this transistor seconds couples second source/drain electrode of this first transistor, first source/drain electrode of this transistor seconds couples one first clock signal, and second source/drain electrode of this transistor seconds couples an output terminal.One the 3rd transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 3rd transistorized first source/drain electrode couples this output terminal, and the 3rd transistorized second source/drain electrode couples this first voltage level.One the 4th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 4th transistorized second source/drain electrode couples this first voltage level, the 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistorized first source/drain electrode couples the grid of this transistor seconds.One the 5th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 5th transistorized grid and the 5th transistorized first source/drain electrode couple this second clock signal, and the 5th transistorized second source/drain electrode couples the 3rd transistorized grid.One the 6th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 6th transistorized second source/drain electrode couples this first voltage level, the 6th transistorized grid couples this first clock signal, and the 6th transistorized first source/drain electrode couples the 3rd transistorized grid.One the 7th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 7th transistorized second source/drain electrode couples this first voltage level, the 7th transistorized grid couples the output signal of this prime shift register, and the 7th transistorized first source/drain electrode couples the 3rd transistorized grid.One the 8th transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 8th transistorized first source/drain electrode couples this output terminal, and the 8th transistorized second source/drain electrode couples this first voltage level.One the 9th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 9th transistorized second source/drain electrode couples this first voltage level, the 9th transistorized grid couples the 8th transistorized grid, and the 9th transistorized first source/drain electrode couples the grid of this transistor seconds.The tenth transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the tenth transistorized grid and the tenth transistorized first source/drain electrode couple this first clock signal, and the tenth transistorized second source/drain electrode couples the 8th transistorized grid.The 11 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 11 transistorized second source/drain electrode couples this first voltage level, the 11 transistorized grid couples this second clock signal, and the 11 transistorized first source/drain electrode couples the 8th transistorized grid.The tenth two-transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, second source/drain electrode of the tenth two-transistor couples this first voltage level, the grid of the tenth two-transistor couples this output terminal, and first source/drain electrode of the tenth two-transistor couples the 8th transistorized grid.

For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.

Description of drawings

Fig. 1 be the thin film transistor (TFT) of a 300um technology at 80 ℃, under the different running times, the synoptic diagram of voltage and electric current.

Fig. 2 is the circuit diagram of an existing shift register.

Fig. 3 is the output signal synoptic diagram of shift register among Fig. 2.

Fig. 4 is the synoptic diagram of the shift register of first embodiment according to the invention.

Fig. 5 is the synoptic diagram according to the shift register of second embodiment of the present invention.

Fig. 6 is the synoptic diagram according to the shift register of the 3rd embodiment of the present invention.

Fig. 7 is the circuit diagram of one first drop-down module according to an embodiment of the invention.

Fig. 8 is the circuit diagram of one second drop-down module according to an embodiment of the invention.

Fig. 9 is the circuit diagram of one the 3rd drop-down module according to an embodiment of the invention.

Figure 10 is the circuit diagram according to the 4th embodiment of the present invention.

Figure 11 is the sequential chart of shift register shown in Figure 10.

The reference numeral explanation

11,12,13,14,15,31,32-curve

41,51, the 61-first drop-down module

42,52, the 62-second drop-down module

The 53-switchgear

63-the 3rd drop-down module

T21, T22, T41, T42, T51, T52, T61, T62, T71, T72, T73, T74, T75, T81, T82, T83, T84, T85, T91, T92, T93, T94, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17-transistor

N70, N80, N1, N2, N3, N4-end points

Embodiment

Fig. 4 is the synoptic diagram of the shift register of first embodiment according to the invention.The output signal N with shift register that utilizes the first drop-down module 41 and the second drop-down module 42 to replace among first embodiment is coupled to low-voltage source VSS and is in closed condition to keep output signal N.The grid of transistor T 41 and its first source/drain electrode couple the output signal (N-1) and the first drop-down module 41 of prime shift register.Second source/drain electrode of transistor T 41 couples the grid of transistor T 42.First source/drain electrode of transistor T 42 couples one first clock signal clk, and second source/drain electrode of transistor T 42 couples the output signal N of first drop-down module 41, the second drop-down module 42 and shift register.The first drop-down module 41 and the second drop-down module 42 couple first clock signal clk and second clock signal XCLK respectively.When the output signal (N-1) of prime shift register was low voltage level with first clock signal clk, this first drop-down module 41 coupled the output signal N of shift register to low-voltage source VSS.When the output signal (N-1) of prime shift register was low voltage level with second clock signal XCLK, this second drop-down module 42 coupled the output signal N of shift register to low-voltage source VSS.When the grid of current transistor T 42 and first clock signal clk were high-voltage level, the output signal N of shift register was a high-voltage level.

Fig. 5 is the synoptic diagram according to the shift register of second embodiment of the present invention.Increase by a switchgear 53 with first embodiment difference shown in Figure 4 at second embodiment, when being high-voltage level, close this first drop-down module in order to output signal N at shift register.The grid of transistor T 51 and its first source/drain electrode couple the output signal (N-1) and the first drop-down module 51 of prime shift register.Second source/drain electrode of transistor T 51 couples the grid of transistor T 52.First source/drain electrode of transistor T 52 couples one first clock signal clk, and second source/drain electrode of transistor T 52 couples the output signal N of first drop-down module 51, the second drop-down module 52 and shift register.The first drop-down module 51 and the second drop-down module 52 couple first clock signal clk and second clock signal XCLK respectively.When the output signal (N-1) of prime shift register was low voltage level with first clock signal clk, this first drop-down module 51 coupled the output signal N of shift register to low-voltage source VSS.When the output signal (N-1) of prime shift register was low voltage level with second clock signal XCLK, this second drop-down module 52 coupled the output signal N of shift register to low-voltage source VSS.When the grid of transistor T 52 and first clock signal clk were high-voltage level, the output signal N that this switchgear 53 cuts out the first drop-down module 51 and shift register was a high-voltage level.

Fig. 6 is the synoptic diagram according to the shift register of the 3rd embodiment of the present invention.In the present embodiment, utilizing the output signal (N+1) of a level shift register is a voltage source, is coupled to low-voltage source VSS in order to the output signal N with shift register.The grid of transistor T 61 and its first source/drain electrode couple the output signal (N-1) and the first drop-down module 61 of prime shift register.Second source/drain electrode of transistor T 61 couples the grid of transistor T 62.First source/drain electrode of transistor T 62 couples one first clock signal clk, and second source/drain electrode of transistor T 62 couples the output signal N of first drop-down module 61, the second drop-down module 62 and shift register.The 3rd drop-down module 63 couples the output signal (N+1) of second source/drain electrode, the first drop-down module 61 and the secondary shift register of transistor T 62.The first drop-down module 61 and the second drop-down module 62 couple first clock signal clk and second clock signal XCLK respectively.When the output signal (N-1) of prime shift register was low voltage level with first clock signal clk, this first drop-down module 61 coupled the output signal N of shift register to low-voltage source VSS.When the grid of transistor T 62 and second clock signal XCLK were low voltage level, this second drop-down module 62 coupled the output signal N of shift register to low-voltage source VSS.When the grid of output signal (N-1) transistor T 62 of prime shift register and first clock signal clk were high-voltage level, the output signal N of shift register was a high-voltage level.When the output signal (N+1) of secondary shift register is the output signal (N) of high-voltage level and shift register at the corresponding levels during for low voltage level, three module 63 couples the output signal N of shift register to low-voltage source VSS.

In the 4th, 5 and 6 figure, the first drop-down module 41,51 and 61, the second drop-down module 42,52 and the 62, the 3rd drop-down module 63 and switchgear 53 can be combined by resistance, electric capacity, transistor, multiplexer, logic gate or other similar assembly, may constitute or by circuit that a plurality of assembly combined for single component.In order to be described in more detail, hereinafter special with the preferred embodiment explanation, but be not that the present invention is limited to this embodiment.

Fig. 7 is the circuit diagram of one first drop-down module according to an embodiment of the invention.The circuit of the first drop-down module shown in Figure 7 is applicable to the first drop-down module 41,51 and 61.First source/drain electrode of transistor T 71 couples the output signal N of shift register, and its second source/drain electrode is coupled to a low-voltage source VSS.First source/drain electrode of transistor T 72 couples the grid as transistor T 42, T52 and T62, and second source/drain electrode of transistor T 72 is coupled to the grid that a low-voltage source VSS and its grid couple transistor T 71.First source/drain electrode of the grid of transistor T 73 and this transistor T 73 couples second clock signal XCLK, and second source/drain electrode of transistor T 73 couples the grid of this transistor T 71.The grid of transistor T 74 couples first clock signal clk, and first source/drain electrode of transistor T 74 couples second source/drain electrode of transistor T 73, and second source/drain electrode of transistor T 74 couples low-voltage source VSS.The grid of transistor T 75 couples the output signal (N-1) of prime shift register, and first source/drain electrode of transistor T 75 couples the grid of transistor T 71, and second source/drain electrode of transistor T 75 couples low-voltage source VSS.When the output signal (N-1) of prime shift register was high-voltage level, transistor T 75 was switched on, and the current potential of end points N70 is coupled to low-voltage source VSS, closes transistor T 72 and T71.When the output signal (N-1) of prime shift register is low voltage level with first clock signal clk, this moment, second clock signal XCLK was a high-voltage level, end points N70 is a high-voltage level, turn-on transistor T72 and T71 make the output signal N of shift register be coupled to low-voltage source VSS.

Fig. 8 is the circuit diagram of one second drop-down module according to an embodiment of the invention.The circuit of the second drop-down module shown in Figure 8 is applicable to the second drop-down module 42,52 and 62.First source/drain electrode of transistor T 81 couples the output signal N of shift register, and its second source/drain electrode is coupled to a low-voltage source VSS.First source/drain electrode of transistor T 82 couples the grid as transistor T 42, T52 and T62, and second source/drain electrode of transistor T 82 is coupled to the grid that a low-voltage source VSS and its grid couple transistor T 81.First source/drain electrode of the grid of transistor T 83 and this transistor T 83 couples first clock signal clk, and second source/drain electrode of transistor T 83 couples the grid of this transistor T 81.The grid of transistor T 84 couples second clock signal XCLK, and first source/drain electrode of transistor T 84 couples second source/drain electrode of transistor T 83, and second source/drain electrode of transistor T 84 couples low-voltage source VSS.The grid of transistor T 85 couples the output signal N of shift register, and first source/drain electrode of transistor T 85 couples the grid of transistor T 81, and second source/drain electrode of transistor T 85 couples low-voltage source VSS.When the output signal N of shift register and second clock signal XCLK were low voltage level, transistor T 83 was switched on, and end points N80 is high-voltage level and turn-on transistor T82 and T81.After transistor T 81 was switched on, the output signal N of shift register was coupled to low-voltage source VSS.When the output signal N of shift register is high-voltage level, transistor T 85 conductings, end points N80 is coupled to low-voltage source VSS, and closing transistor T 81 is high-voltage level with T82 with the output signal N that keeps shift register.

Fig. 9 is the circuit diagram of one the 3rd drop-down module according to an embodiment of the invention.The circuit of the 3rd drop-down module shown in Figure 9 is applicable to the 3rd drop-down module 63.First source/drain electrode of transistor T 91 couples secondary shift register output signal (N+1), and the grid of transistor T 91 couples the first drop-down module, the first drop-down module circuit diagram as shown in Figure 7.Second source/drain electrode of transistor T 91 couples first source/drain electrode of transistor T 92.Second source/drain electrode of transistor T 92 couples low-voltage source VSS, and the grid of transistor T 92 couples first clock signal clk.Transistor T 93 first source/drain electrode couple the output signal N of shift register, and its second source/drain electrode is coupled to a low-voltage source VSS.First source/drain electrode of transistor T 94 couples the grid as transistor T 42, T52 and T62, and second source/drain electrode of transistor T 94 is coupled to the grid that a low-voltage source VSS and its grid couple transistor T 93.When secondary shift register output signal (N+1) and transistor T 91 grids receive high-voltage level, and first clock signal clk is when being low voltage level, and transistor T 93 is switched on, and the output signal N of shift register is coupled to low-voltage source VSS.

Figure 10 is the circuit diagram according to the 4th embodiment of the present invention.The grid of transistor T 1 and its first source/drain electrode couple the output signal (N-1) of a prime shift register.The grid of transistor T 2 couples second source/drain electrode of this transistor T 1, and first source/drain electrode of transistor T 2 couples one first clock signal clk, and second source/drain electrode of transistor T 2 couples shift register output signal N.First source/drain electrode of transistor T 3 couples shift register output signal N, and second source/drain electrode of transistor T 3 couples low-voltage source VSS.Second source/drain electrode of transistor T 4 couples low-voltage source VSS, and the grid of transistor T 4 couples the grid of transistor T 3, and first source/drain electrode of transistor T 4 couples the grid of transistor T 2.The grid of transistor T 5 and its first source/drain electrode couple second clock signal XCLK, and second source/drain electrode of transistor T 5 couples the grid of transistor T 3.Second source/drain electrode of transistor T 6 couples low-voltage source VSS, and the grid of transistor T 6 couples first clock signal clk, and first source/drain electrode of transistor T 6 couples the grid of transistor T 3.Second source/drain electrode of transistor T 7 couples low-voltage source VSS, and the grid of transistor T 7 couples the output signal (N-1) of this prime shift register, and first source/drain electrode of transistor T 7 couples the grid of transistor T 3.First source/drain electrode of transistor T 8 couples shift register output signal N, and second source/drain electrode of transistor T 8 couples low-voltage source VSS.Second source/drain electrode of transistor T 9 couples low-voltage source VSS, and the grid of transistor T 9 couples the grid of this transistor T 8, and first source/drain electrode of transistor T 9 couples the grid of transistor T 2.The grid of transistor T 10 and its first source/drain electrode couple first clock signal clk, and second source/drain electrode of transistor T 10 couples the grid of transistor T 8.Second source/drain electrode of transistor T 11 couples low-voltage source VSS, and the grid of transistor T 11 couples second clock signal XCLK, and first source/drain electrode of transistor T 11 couples the grid of transistor T 8.Second source/drain electrode of transistor T 12 couples low-voltage source VSS, and the grid of transistor T 12 couples shift register output signal N, and first source/drain electrode of transistor T 12 couples the grid of this transistor T 8.The grid of transistor T 13 couples the grid of this transistor T 3, and first source/drain electrode of transistor T 13 couples the output signal (N+1) of secondary shift register.First source/drain electrode of transistor T 14 couples second source/drain electrode of this transistor T 13, and second source/drain electrode of transistor T 14 couples low-voltage source VSS, and the grid of transistor T 14 couples first clock signal clk.The grid of transistor T 15 couples second source/drain electrode of this transistor T 13, and second source/drain electrode of transistor T 15 couples low-voltage source VSS, and first source/drain electrode of transistor T 15 couples the output signal N of shift register.The grid of transistor T 16 couples second source/drain electrode of transistor T 13, and second source/drain electrode of transistor T 16 couples low-voltage source VSS, and first source/drain electrode of transistor T 16 couples the grid of transistor T 2.The grid of transistor T 17 couples the output signal N of shift register, and first source/drain electrode of transistor T 17 couples the grid of transistor T 3, and second source/drain electrode of transistor T 17 couples low-voltage source VSS.

Figure 11 is the sequential chart of shift register shown in Figure 10.When time t1, the output signal of prime shift register (N-1) is a high-voltage level, transistor T 1, T2 and T7 conducting, and end points N1 is a high-voltage level.This moment, first clock signal clk was a low voltage level, so the output signal N of shift register is a low voltage level.The second clock signal is high-voltage level at this moment, and transistor T 11 conductings make end points N2 be coupled to low-voltage source VSS.

When time t2, the signal of the output terminal of prime shift register (N-1) becomes low voltage level, transistor T 1 is closed with transistor T 7, so the current potential of end points N1 can not kept high-voltage level for discharge because of there being discharge path, makes transistor seconds T2 continue to be switched on.This moment, first clock signal clk was a high-voltage level, and to forming the coupling capacitance charging between the first source/drain electrode of transistor seconds T2 and the grid, made the voltage level of end points N1 continue rising.When time t2, first clock signal is that high-voltage level makes that the output terminal N of shift register is a high-voltage level, transistor T 17 conductings, and end points N3 is coupled to low-voltage source VSS makes transistor T 3 and T4 be closed.

When time t3, the output signal N of shift register is a low voltage level, and transistor T 17 is closed, and end points N3 is that high-voltage level makes transistor T 13 be switched on.At this moment, the output signal of secondary shift register (N+1) is a high-voltage level, therefore end points N4 is a high-voltage level, turn-on transistor T15 and T16, make the output signal N of shift register and the grid of transistor T 2 be coupled to low-voltage source VSS, make the output signal N of shift register not be vulnerable to interference of noise and fluctuate.

Beyond time t3, when first clock signal was low voltage level, the output signal N of shift register was coupled to low-voltage source VSS by transistor T 3.When the second clock signal was low voltage level, the output signal N of shift register was coupled to low-voltage source VSS by transistor T 8.Utilize so following pull mechanism can guarantee that the output signal N of shift register remains on closed condition, and can not be subjected to The noise.

In the circuit of Figure 10, shift register has utilized the signal (N+1) of secondary shift register to be used as voltage source, is fixed on low voltage level in order to the output signal N with shift register, avoids being subjected to noise and drift.And first clock signal and second clock signal only have for 50% work period, compare with 100% work period of T22 with transistor T 21 in the existing shift register among Fig. 1, voltage drift situation according to transistorized critical voltage in the shift register of the present invention significantly reduces, and utilizes transistor T 15 and T16 more can reduce the fall time (falling time) of shift register.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (18)

1. a shift register circuit has a plurality of shift registers that are connected in series level, comprising:
One the first transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, first source/drain electrode of the grid of this first transistor and this first transistor couples the output signal of a prime shift register;
One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the grid of this transistor seconds couples second source/drain electrode of this first transistor, first source/drain electrode of this transistor seconds couples one first clock signal, and second source/drain electrode of this transistor seconds couples an output terminal;
One first drop-down module couples this output terminal and this first clock signal, when the output signal of this prime shift register and this first clock signal are low voltage level, couples this output terminal to one first voltage level; And
One second drop-down module couples this output terminal and a second clock signal, when the output signal of this prime shift register and this second clock signal are low voltage level, couples this output terminal to this first voltage level.
2. shift register circuit as claimed in claim 1, wherein, more comprise one the 3rd drop-down module, couple the output signal of a level shift register, when the output signal of secondary shift register is high-voltage level, couple this output terminal to this first voltage level.
3. shift register circuit as claimed in claim 1 wherein, more comprises one first switchgear, couples this output terminal and this first drop-down module, when this output terminal is high-voltage level, closes this first drop-down module.
4. shift register circuit as claimed in claim 1, wherein, the phase differential of this second clock signal and this first clock signal is 180 degree.
5. shift register circuit as claimed in claim 1, wherein, this first clock signal has 50% or be lower than for 50% work period.
6. shift register circuit as claimed in claim 1, wherein, this first drop-down module comprises:
One the 3rd transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 3rd transistorized first source/drain electrode couples this output terminal, and the 3rd transistorized second source/drain electrode couples this first voltage level;
One the 4th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 4th transistorized second source/drain electrode couples this first voltage level, the 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistorized first source/drain electrode couples the grid of this transistor seconds;
One the 5th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 5th transistorized grid and the 5th transistorized first source/drain electrode couple this second clock signal, and the 5th transistorized second source/drain electrode couples the 3rd transistorized grid;
One the 6th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 6th transistorized second source/drain electrode couples this first voltage level, the 6th transistorized grid couples this first clock signal, and the 6th transistorized first source/drain electrode couples the 3rd transistorized grid; And
One the 7th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 7th transistorized second source/drain electrode couples this first voltage level, the 7th transistorized grid couples the output signal of this prime shift register, and the 7th transistorized first source/drain electrode couples the 3rd transistorized grid.
7. shift register circuit as claimed in claim 1, wherein, this second drop-down module comprises:
One the 8th transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 8th transistorized first source/drain electrode couples this output terminal, and the 8th transistorized second source/drain electrode couples this first voltage level;
One the 9th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 9th transistorized second source/drain electrode couples this first voltage level, the 9th transistorized grid couples the 8th transistorized grid, and the 9th transistorized first source/drain electrode couples the grid of this transistor seconds;
The tenth transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the tenth transistorized grid and the tenth transistorized first source/drain electrode couple this first clock signal, and the tenth transistorized second source/drain electrode couples the 8th transistorized grid;
The 11 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 11 transistorized second source/drain electrode couples this first voltage level, the 11 transistorized grid couples this second clock signal, and the 11 transistorized first source/drain electrode couples the 8th transistorized grid; And
The tenth two-transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, second source/drain electrode of the tenth two-transistor couples this first voltage level, the grid of the tenth two-transistor couples this output terminal, and first source/drain electrode of the tenth two-transistor couples the 8th transistorized grid.
8. shift register circuit as claimed in claim 2, wherein, the 3rd drop-down module comprises:
The 13 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 13 transistorized grid couples this first drop-down module, and the 13 transistorized first source/drain electrode couples the output signal of this secondary shift register;
The 14 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 14 transistorized first source/drain electrode couples the 13 transistorized second source/drain electrode, the 14 transistorized second source/drain electrode couples this first voltage level, and the 14 transistorized grid couples this first clock signal;
The 15 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 15 transistorized grid couples the 13 transistorized second source/drain electrode, the 15 transistorized second source/drain electrode couples this first voltage level, and the 15 transistorized first source/drain electrode couples this output terminal; And
The 16 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 16 transistorized grid couples the 13 transistorized second source/drain electrode, the 16 transistorized second source/drain electrode couples this first voltage level, and the 16 transistorized first source/drain electrode couples the grid of this transistor seconds.
9. shift register circuit as claimed in claim 3, wherein, this first switchgear is 1 the 17 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 17 transistorized grid couples this output terminal, and the 17 transistorized first source/drain electrode couples this first drop-down module, and the 17 transistorized second source/drain electrode couples this first voltage level.
10. shift register circuit as claimed in claim 1, if this shift register is in the first order shift register, wherein the output signal of this prime shift register is a sensitizing pulse signal.
11. a shift register circuit, the shift register with a plurality of serial connection levels comprises:
One the first transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein first of the grid of this first transistor and this first transistor source/drain electrode couples the output signal of a prime shift register;
One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the grid of this transistor seconds couples second source/drain electrode of this first transistor, first source/drain electrode of this transistor seconds couples one first clock signal, and second source/drain electrode of this transistor seconds couples an output terminal;
One the 3rd transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 3rd transistorized first source/drain electrode couples this output terminal, and the 3rd transistorized second source/drain electrode couples this first voltage level;
One the 4th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 4th transistorized second source/drain electrode couples this first voltage level, the 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistorized first source/drain electrode couples the grid of this transistor seconds;
One the 5th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 5th transistorized grid and the 5th transistorized first source/drain electrode couple this second clock signal, and the 5th transistorized second source/drain electrode couples the 3rd transistorized grid;
One the 6th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 6th transistorized second source/drain electrode couples this first voltage level, the 6th transistorized grid couples this first clock signal, and the 6th transistorized first source/drain electrode couples the 3rd transistorized grid;
One the 7th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 7th transistorized second source/drain electrode couples this first voltage level, the 7th transistorized grid couples the output signal of this prime shift register, and the 7th transistorized first source/drain electrode couples the 3rd transistorized grid;
One the 8th transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein, the 8th transistorized first source/drain electrode couples this output terminal, and the 8th transistorized second source/drain electrode couples this first voltage level;
One the 9th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 9th transistorized second source/drain electrode couples this first voltage level, the 9th transistorized grid couples the 8th transistorized grid, and the 9th transistorized first source/drain electrode couples the grid of this transistor seconds;
The tenth transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the tenth transistorized grid and the tenth transistorized first source/drain electrode couple this first clock signal, and the tenth transistorized second source/drain electrode couples the 8th transistorized grid;
The 11 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 11 transistorized second source/drain electrode couples this first voltage level, the 11 transistorized grid couples this second clock signal, and the 11 transistorized first source/drain electrode couples the 8th transistorized grid; And
The tenth two-transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, second source/drain electrode of the tenth two-transistor couples this first voltage level, the grid of the tenth two-transistor couples this output terminal, and first source/drain electrode of the tenth two-transistor couples the 8th transistorized grid.
12. shift register circuit as claimed in claim 11 wherein, more comprises one the 3rd drop-down module, couple the output signal of a level shift register, when the output signal of secondary shift register is high-voltage level, couple this output terminal to this first voltage level, comprising:
The 13 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 13 transistorized grid couples the 3rd transistorized grid, and the 13 transistorized first source/drain electrode couples the output signal of this secondary shift register;
The 14 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 14 transistorized first source/drain electrode couples the 13 transistorized second source/drain electrode, the 14 transistorized second source/drain electrode couples this first voltage level, and the 14 transistorized grid couples this first clock signal;
The 15 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 15 transistorized grid couples the 13 transistorized second source/drain electrode, the 15 transistorized second source/drain electrode couples this first voltage level, and the 15 transistorized first source/drain electrode couples this output terminal; And
The 16 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 16 transistorized grid couples the 13 transistorized second source/drain electrode, the 16 transistorized second source/drain electrode couples this first voltage level, and the 16 transistorized first source/drain electrode couples the grid of this transistor seconds.
13. shift register circuit as claimed in claim 11 wherein, more comprises one first switchgear, when this output terminal is high-voltage level, closes the 3rd transistor, comprising:
The 17 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein, the 17 transistorized grid couples this output terminal, the 17 transistorized first source/drain electrode couples the 3rd transistorized grid, and the 17 transistorized second source/drain electrode couples this first voltage level.
14. shift register circuit as claimed in claim 11, wherein, the phase differential of this second clock signal and this first clock signal is 180 degree.
15. shift register circuit as claimed in claim 11, wherein, this first clock signal has 50% or be lower than for 50% work period.
16. shift register circuit as claimed in claim 11, if this shift register is in the first order shift register, wherein, the output signal of this prime shift register is a sensitizing pulse signal.
17. shift register circuit as claimed in claim 11, wherein, described transistor is a nmos pass transistor.
18. shift register circuit as claimed in claim 11, wherein, described transistor is the TFT thin film transistor (TFT), is arranged on the glass substrate.
CNB2005100992262A 2005-09-07 2005-09-07 Shift register circuit CN100495576C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100992262A CN100495576C (en) 2005-09-07 2005-09-07 Shift register circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100992262A CN100495576C (en) 2005-09-07 2005-09-07 Shift register circuit

Publications (2)

Publication Number Publication Date
CN1767070A true CN1767070A (en) 2006-05-03
CN100495576C CN100495576C (en) 2009-06-03

Family

ID=36742858

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100992262A CN100495576C (en) 2005-09-07 2005-09-07 Shift register circuit

Country Status (1)

Country Link
CN (1) CN100495576C (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100463042C (en) * 2006-09-27 2009-02-18 友达光电股份有限公司 Control circuit capable of removing residual charge
CN101042937B (en) * 2007-04-24 2010-10-13 友达光电股份有限公司 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display
CN101887757A (en) * 2010-07-08 2010-11-17 友达光电股份有限公司 Shift register circuit and shift register
US7992063B2 (en) 2006-09-01 2011-08-02 Au Optronics Corp. Control circuit for releasing residual charges
CN101562047B (en) * 2008-04-15 2011-08-24 北京京东方光电科技有限公司 Shift register and liquid crystal display grate drive device
CN101645243B (en) * 2008-08-06 2012-02-15 胜华科技股份有限公司 Shift register
CN102411916A (en) * 2011-11-18 2012-04-11 友达光电股份有限公司 Grid electrode driving circuit and grid electrode driving method thereof
CN102650751A (en) * 2011-09-22 2012-08-29 京东方科技集团股份有限公司 GOA (Gate Driver on Array) circuit, array base plate and liquid crystal display device
CN101645308B (en) * 2008-08-07 2012-08-29 北京京东方光电科技有限公司 Shift register comprising multiple stage circuit units
CN101661798B (en) * 2009-09-24 2012-08-29 友达光电股份有限公司 Shift register circuit and method for generating grid signals thereof
CN104200788A (en) * 2009-03-26 2014-12-10 株式会社半导体能源研究所 Liquid crystal display device, driving method of the same, and electronic device including the same
TWI690837B (en) * 2019-01-07 2020-04-11 友達光電股份有限公司 Shift register

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7992063B2 (en) 2006-09-01 2011-08-02 Au Optronics Corp. Control circuit for releasing residual charges
CN100463042C (en) * 2006-09-27 2009-02-18 友达光电股份有限公司 Control circuit capable of removing residual charge
CN101042937B (en) * 2007-04-24 2010-10-13 友达光电股份有限公司 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display
CN101562047B (en) * 2008-04-15 2011-08-24 北京京东方光电科技有限公司 Shift register and liquid crystal display grate drive device
CN101645243B (en) * 2008-08-06 2012-02-15 胜华科技股份有限公司 Shift register
CN101645308B (en) * 2008-08-07 2012-08-29 北京京东方光电科技有限公司 Shift register comprising multiple stage circuit units
CN104200788A (en) * 2009-03-26 2014-12-10 株式会社半导体能源研究所 Liquid crystal display device, driving method of the same, and electronic device including the same
CN101661798B (en) * 2009-09-24 2012-08-29 友达光电股份有限公司 Shift register circuit and method for generating grid signals thereof
CN101887757B (en) * 2010-07-08 2014-03-26 友达光电股份有限公司 Shift register circuit and shift register
CN101887757A (en) * 2010-07-08 2010-11-17 友达光电股份有限公司 Shift register circuit and shift register
CN102650751A (en) * 2011-09-22 2012-08-29 京东方科技集团股份有限公司 GOA (Gate Driver on Array) circuit, array base plate and liquid crystal display device
CN102650751B (en) * 2011-09-22 2014-08-06 京东方科技集团股份有限公司 GOA (Gate Driver on Array) circuit, array base plate and liquid crystal display device
CN102411916B (en) * 2011-11-18 2013-08-14 友达光电股份有限公司 Grid electrode driving circuit and grid electrode driving method thereof
CN102411916A (en) * 2011-11-18 2012-04-11 友达光电股份有限公司 Grid electrode driving circuit and grid electrode driving method thereof
TWI690837B (en) * 2019-01-07 2020-04-11 友達光電股份有限公司 Shift register

Also Published As

Publication number Publication date
CN100495576C (en) 2009-06-03

Similar Documents

Publication Publication Date Title
JP6159903B1 (en) Semiconductor device
US9685134B2 (en) Shift register unit, gate driving circuit and display device
US9779682B2 (en) GOA circuit with forward-backward scan function
JP6498772B2 (en) GOA circuit and liquid crystal display device
JP6415684B2 (en) Gate electrode drive circuit with bootstrap function
CN103208251B (en) A kind of shift register cell, gate driver circuit and display device
JP6240781B2 (en) Array substrate row drive circuit
US9177666B2 (en) Shift register unit and driving method thereof, shift register and display apparatus
CN103440839B (en) Shifting deposit unit, shift register and display device
US9887013B2 (en) Shift register unit, shift register, and display apparatus
US9355741B2 (en) Display apparatus having a gate drive circuit
CN104282287B (en) A kind of GOA unit and driving method, GOA circuit and display device
US9349331B2 (en) Shift register unit circuit, shift register, array substrate and display apparatus
KR101443131B1 (en) Driving circuit, shifting register, gate driver, array substrate and display device
US7394102B2 (en) Pulse output circuit, shift register, and display device
TWI400686B (en) Shift register of lcd devices
US8964932B2 (en) Shift register, gate driving circuit and display
KR101493186B1 (en) Shift register unit, shift register and display apparatus
US8686990B2 (en) Scanning signal line drive circuit and display device equipped with same
JP6423956B2 (en) Gate electrode drive circuit based on IGZO manufacturing process
US20130088265A1 (en) Gate driver on array, shifting regester and display screen
JP6593891B2 (en) Shift register, stage transmission gate driver circuit and display panel
US20160343323A1 (en) Goa circuit of ltps semiconductor tft
US9640276B2 (en) Shift register unit and gate driving circuit
US20150310819A1 (en) Gate Driver for Narrow Bezel LCD

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant