CN1696920A - Enhancement type expandable time sharing bus architecture - Google Patents
Enhancement type expandable time sharing bus architecture Download PDFInfo
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- CN1696920A CN1696920A CN 200410044604 CN200410044604A CN1696920A CN 1696920 A CN1696920 A CN 1696920A CN 200410044604 CN200410044604 CN 200410044604 CN 200410044604 A CN200410044604 A CN 200410044604A CN 1696920 A CN1696920 A CN 1696920A
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Abstract
An intensified extensible time - sharing bus is featured as using common bus of address and file to transmit address and file between microprocessor and storage in time - sharing mode through bus boundary of microprocessor and storage, utilizing logic integration of two control lines to decide that the address and file common bus is used to transmit address, to fetch file or to write in file so script for preparing boundary can be saved and storage space with elasticity and times can be obtained.
Description
Technical field
The invention relates to the bus between the integrated circuit (IC), refer to a kind of reinforced extendible time-sharing bus framework especially.
Background technology
Known micro control system mainly is by microprocessor, storer and I/O device constitute, as shown in Figure 1, the transmission of the data between this microprocessor 110 and this storer 120 (or I/O device) is by one group of address bus 130, one group of data bus 140 and cooperate one group of read-write control signal line 150 to carry out, wherein, this address bus 130 is in order to carry the address of storer 120 (or I/O device), and the width of address bus 130 is promptly being represented the size of storage space, and promptly representing maximum memory span as 8 address lines is 256 bit groups (byte).
When aforesaid micro control system increases memory span, the width of this address bus 130 also must with increase, for example when memory span increases to 64k bit group, must increase to 16 address lines this moment, thus except the cost that increases the PCB of system, and can increase the routing and the packaging cost of storer, and the memory span of total system is after having designed, just do not have extendibility, and the restriction that its making is arranged and use.
The restriction of using at this kind address bus in U.S. USP6, in 493, No. 778 patent case bulletins, is used the extendible time-sharing bus framework, to transmit address and data at same address data bus.Its function mode as shown in Figure 2, when controlling signal MC1 be noble potential, when MC0 is electronegative potential, the address data bus transmits a high-order tuple address (AH), when controlling signal MC1 and MC0 are noble potential, the address data bus transmits a low level tuple address (AL), when controlling signal MC1 is electronegative potential and MC0 when being noble potential, the address data bus transmits a data bits tuple.The Partner device can obtain one 16 address lines with high-order tuple address (AH) and low level tuple address (AL) combination.So, device need not to extend to 16 address lines and also can deal with access when memory span increases to 64k bit group.
Yet because various application are increasingly sophisticated, the memory span of 64k bit can't satisfy existing demands of applications.When facing the access of the memory span that surpasses the 64k bit, this kind bus architecture can utilize memory row to switch (memory bank switch) technology to solve the problem of address lines deficiency, only this can increase the more time on memory row is switched, and reduces system effectiveness.Simultaneously, the access of only execute store mapping thereon of this bus architecture (memory map) can't be carried out the access of output input mapping (I/O map), also can't carry out the outburst transmission of block, therefore, the bus architecture of aforementioned micro control system gives improved necessity in fact.
The inventor whence originally in the spirit of positive invention, is urgently thought a kind of extendible type time-shared bus framework that can address the above problem because of in this, and several times research experiment is eventually to finishing this novel progressive invention.
Summary of the invention
Fundamental purpose of the present invention provides a kind of reinforced extendible time-sharing bus framework, to save the pin number of integrated circuit (IC) wafer.
Another object of the present invention provides a kind of reinforced extendible time-sharing bus framework, with the capacity of extended storage easily.
A further object of the present invention provides a kind of reinforced extendible time-sharing bus framework, to export input mapping access.
Another purpose of the present invention provides a kind of reinforced extendible time-sharing bus framework, to carry out block transmission access.
For reaching aforesaid purpose, a kind of reinforced extendible time-sharing bus framework of the present invention, it is the data reading-writing that is used between a drive end device and at least one Partner device, this bus architecture mainly comprises a drive end bus interface and a Partner bus interface, wherein, this drive end interface is to reach at least two control lines with an address and data shared bus to be connected with this Partner bus interface, this address and data shared bus are to transmit address and data between this drive end device and this Partner device with timesharing, these at least two control lines then are that to be driven by this drive end device be accurate position of first logic or the accurate position of second logic, so that make this drive end device and this Partner device determine that according to the logical combination of this control line this address and data shared bus are in order to transmission storer address, output/input address, read data, write data, block reads data or block writes data.
Described reinforced extendible time-sharing bus framework, wherein, this Partner bus interface has a storer address working storage, with when carrying out the memory data read-write, the storer address that read and write is locked.
Described reinforced extendible time-sharing bus framework, wherein, this Partner bus interface has more a data base working storage, it is the position of the data base that provided of this Partner device of record, to cooperate the content of this storer address working storage device, produce actual address by memory mapped.
Described reinforced extendible time-sharing bus framework, wherein, this Partner bus interface has an output/input address working storage, with when exporting/input data when read-write, the output/input address that read and write is locked.
Described reinforced extendible time-sharing bus framework, wherein, this Partner bus interface has more an output/input working storage, it is the position of output/input of being provided of this Partner device of record, to cooperate the content of this output/input address working storage device, produce actual address by output/input mapping.
Described reinforced extendible time-sharing bus framework, wherein, this Partner bus interface has more identity identification working storage to write down the numbering at this Partner bus interface, use the numbering that the identity identification numbering sent when this drive end device and this Partner bus interface is write down when identical, this Partner bus interface is given activation.
Described reinforced extendible time-sharing bus framework, wherein, these at least two control lines are to comprise one first control line and one second control line.
Described reinforced extendible time-sharing bus framework wherein, when this first control line is the accurate position of first logic earlier than second control line, is the execute store access.
Described reinforced extendible time-sharing bus framework wherein, when this first control line is the accurate position of second logic earlier than second control line, is that execute store writes.
Described reinforced extendible time-sharing bus framework wherein, is write fashionablely when execute store, and when this second control line was the accurate position of second logic, this address and data shared bus write data in order to transmission.
Described reinforced extendible time-sharing bus framework, wherein, when this second control line was the accurate position of second logic earlier than first control line, execute store was read.
Described reinforced extendible time-sharing bus framework, wherein, when execute store was read, when this first control line was second logic standard position, this address and data shared bus were read data in order to transmission.
Described reinforced extendible time-sharing bus framework wherein, when this second control line is the accurate position of first logic earlier than first control line, is carried out output/input access.
Described reinforced extendible time-sharing bus framework wherein, when this first control line is the accurate position of second logic earlier than second control line, is carried out output/input and is write.
Described reinforced extendible time-sharing bus framework wherein, is write fashionablely when execute store, and when this second control line was the accurate position of second logic, this address and data shared bus write data in order to transmission.
Described reinforced extendible time-sharing bus framework wherein, when this second control line is the accurate position of second logic earlier than first control line, is carried out output/input and is read.
Described reinforced extendible time-sharing bus framework, wherein, when execute store was read, when this first control line was second logic standard position, this address and data shared bus were to read data in order to transmission.
Described reinforced extendible time-sharing bus framework, wherein, this drive end device is a microprocessor, this Partner device is a storer.
Described reinforced extendible time-sharing bus framework, wherein, the accurate position of this first logic is the logic low level, the accurate position of this second logic is the logic high levle.
To sum up institute is old, and via using reinforced extendible time-sharing bus framework of the present invention, it really can reach following purpose and advantage:
(1) resilient memory span: only need fixing address bus width, can reach the ability of extended storage, allow the user of this microprocessor, can be along with different application, additions and deletions memory span freely, and must not change microprocessor again.For example, when this address and data bus 350 were 8 bits, known technology only can provide the storage space of 64K, and the technology of the present invention then can provide 24M storage space and the 24M output input space.
(2) save cost: because of the number of microprocessor and storer pin can be along with memory span increases, whole pin number can reach the degree of simplifying most, so can effectively save the PCB of system cost, and can reduce routing and packaging cost: in addition, also can have influence on the size of wafer because of the number number of pin (PAD), because the pin fixed number, so, can significantly reduce chip area in the application of need mass storage.
(3) variation of increase access: this drive end device 310 can use output input mapping or storer mapping, with access Partner device 320 according to the characteristic of Partner device 320.
(4) increase access speed: this drive end device 310 can be carried out the block transmission, to increase data transmitting speed between itself and the Partner device 320.
Description of drawings
Fig. 1 is the synoptic diagram of known extendible time-sharing bus framework;
Fig. 2 is the sequential chart of known extendible time-sharing bus framework;
Fig. 3 is a reinforced extendible time-sharing bus configuration diagram of the present invention;
Fig. 4 is the functional block diagram at Partner bus of the present invention interface;
Fig. 5 is an example of the memory mapped that adopted of extendible time-sharing bus framework of the present invention;
Fig. 6 is the state transition diagram that is relevant to storage access of this bus control unit inside of the present invention;
Fig. 7 is the state transition diagram that is relevant to output input access of this bus control unit inside of the present invention;
Fig. 8 is that the cycle sequential chart is write out in storer mapping of the present invention;
Fig. 9 is a storer mapping readout interval sequential chart of the present invention;
Figure 10 is that the cycle sequential chart is write out in output input mapping of the present invention;
Figure 11 is an output input mapping readout interval sequential chart of the present invention;
Figure 12 is that the cycle sequential chart is write out in block memory mapping of the present invention;
Figure 13 is a block memory mapping readout interval sequential chart of the present invention;
Figure 14 be storer mapping of the present invention read/write cycle sequential chart;
Embodiment
One preferred embodiment of relevant reinforced extendible time-sharing bus framework of the present invention, please be earlier with reference to shown in Figure 3, it is the data reading-writing that is used between a drive end device 310 and at least one Partner device 320, in present embodiment, this drive end device 310 is a microprocessor 311, and this Partner device 320 is a storer 321.This bus architecture mainly comprises a drive end bus interface 330 and a Partner bus interface 340, wherein, this drive end bus interface 330 is to be connected with this Partner bus interface 340 with the address of a N bit and data shared bus 350 and at least two control lines 360.This address and data shared bus 350 are in order to transmitting address and data information between this microprocessor 311 and this storer 321, and 360 of these at least two control lines are in order to determine that this address and data shared bus 350 are to be used for transmitting address, to read data or to write data.
With reference to shown in Figure 4, this Partner bus interface 340 is the logic state combination of this control line MC0 and MC1 to be decoded with general decode logic by its bus control unit 410, can judge on present this address and the data shared bus 350 it is to transmit which kind of information, so that this storer 321 is sent suitable read-write control signal, correctly to finish the action of storage access.
This Partner bus interface 340 and with address working storage 420 again, 430 and 440 lock the address of the storer 321 that will read and write, that is judge on this address and the data bus 350 it is when transmitting the address information according to the decoding of this bus control unit 410, this address is locked, in this preferred embodiment, this address working storage 420 and 430 is address portions in partly reaching with the high address that one group of flip-flop pins the address information, this address working storage 440 pins low address part with one group of bolt-lock, and the address of the storer that will read and write is locked, so can obtain the address space of 23N altogether.
By this address working storage 420,430 and 440 address that locked, promptly can be used to storer 321 addressing, so that with access specific memory device, and be further to expand accessible memory span, this Partner bus interface 340 has more a data base working storage 450, it is in order to the position of the most data bases that provided by this storer 321 to be provided, the content of using data base working storage 450 cooperates upward this address working storage 420,430 and 440 content, calculating by an address mapping operations unit 470, arrive the physical storage address with mapping (Mapping), with reference to shown in Figure 5, in this preferred embodiment, this data base working storage 450 has the N bit, and therefore, it can write down 2 altogether
N Individual data base 510, cooperate again that this address working storage 420,430 and 440 provided 2
3NAddress space, after memory mapped, can obtain 2
4NAddress space.
Please refer to shown in Figure 4 again, this Partner bus interface 340 has more an identity identification working storage 460, it is in order to write down the identiflication number that this Partner bus interface 340 is had, with the numbering at the identity identification sent when drive end bus interface 330 numbering and this Partner bus interface 340 when identical, then this Partner bus interface 340 is given activation (enable), therefore, can make a drive end device 310 carry out the read-write of data, and further expand accessible memory span again the Partner device 320 of majority.
In present embodiment, this identity identification working storage 460 also is the N bit, and it can discern 2 altogether
NIndividual Partner device 320, therefore, the effect via working storages such as this address working storage 420,430 and 440, data base working storage 450 and identification working storages 460 just can obtain 2
5NAddress space, but not General N bit bus 2
NAddress space.In addition, if do not use identity identification working storage 460, also can obtain 2
4NAddress space, if simultaneously do not use identity identification working storage 460 and data base working storage 450, also can obtain 2
3NAddress space, and owing to have these address spaces, thus in the use of system, just can free additions and deletions storage space, and can be not limited because of the width of address bus.
The reinforced extendible time-sharing bus framework of present embodiment is to be that example is illustrated to have two control line MC0 and MC1, in when desiring to carry out data reading-writing, these two control line MC0 and MC1 are that to be driven by this microprocessor 311 be logic high levle or logic low level, to define different store access cycles.When this strengthens extendible time-sharing bus idle (idle), this control line MC1 and MC0 are the logic high levle, when these microprocessor 311 desires are carried out a storer mapping access, then earlier this control line MC0 is driven and be the logic low level, when these microprocessor 311 desires were carried out the access of an output input mapping, then earlier this control line MC1 being driven was the logic low level.When action is write out in this microprocessor 311 desires execution one, then when this control line MC1 and MC0 are the logic low level, earlier this control line MC0 is driven and be the logic high levle, when this microprocessor 311 desires carry out one when reading in action, then when this control line MC1 and MC0 are the logic low level, earlier this control line MC1 is driven and be the logic high levle.
Fig. 6 is the state transition diagram that is relevant to storage access of these bus control unit 410 inside, Fig. 7 is the state transition diagram that is relevant to output input access of these bus control unit 410 inside, to carry out the various store access cycles of the reinforced extendible time-sharing bus framework of the present invention respectively.
Fig. 8 is that the cycle sequential chart is write out in a storer mapping, when T1, because be when carrying out a storer mapping access, then this control line MC0 is driven to the logic low level, this moment this bus control unit 410 to detect this control line MC0 be that logic low level and MC1 are the logic high levle, then enter the MA1 state and produce a controlling signal 421, pin the high address part information of being transmitted on this address and the data bus 350 (AH) so that drive this address working storage 420.When T2, this control line MC1 is driven to the logic low level, 410 of this bus control units enter the MA2 state and produce a controlling signal 431, pin the middle address part information of being transmitted on this address and the data bus 350 (AM) so that drive this address working storage 430.When T3, this control line MC0 is driven to the logic high levle, 410 of this bus control units enter the WMA3 state and produce a controlling signal 441, pin the low address part information of being transmitted on this address and the data bus 350 (AL) so that drive this address working storage 440, because this moment, this control line MC0 was driven to the logic high levle earlier than MC1,, this bus control unit 410 is write cycle so can detecting this.When T4, this control line MC1 is driven to the logic high levle, represent that these drive end device 310 preparations finish this storer and write out the cycle, so 410 of this bus control units enter the data of writing (WData) state and produce controlling signal 411,412, so that the data information of being transmitted on this address and the data bus 350 (DATA) is write in this storer 321.
In like manner, Fig. 9 is a storer mapping readout interval sequential chart, and when itself and the main difference of Fig. 8 were T3, this control line MC1 was driven to the logic high levle earlier than MC0, is readout interval so this bus control unit 410 can detect this.
Figure 10 is that the cycle sequential chart is write out in an output input mapping (I/O map), and when itself and the main difference of Fig. 8 were T1, this control line MC1 was driven to the logic low level earlier than MC0, is output input mapping store access cycle so this bus control unit 410 can detect this.
Figure 11 is an output input mapping readout interval sequential chart, and when itself and the main difference of Figure 10 were T3, this control line MC1 was driven to the logic high levle earlier than MC0, was readout interval so this bus control unit 410 can detect this.
Figure 12 is that the cycle sequential chart is write out in a block memory mapping, and when T3, this control line MC0 is driven to the logic high levle earlier than MC1, so this bus control unit 410 can detect this for writing out the cycle.When T3 ',,, 410 of this bus control units write data (BWData) state so entering outburst because this moment, this control line MC0 was driven to the logic low level once more.In T3 " time; because this moment, this control line MC0 was driven to the logic high levle once more; so 410 of this bus control units produce controlling signal 411,412; so that the data information of being transmitted on this address and the data bus 350 (DATA) is write in this storer 321, and reenter data (BWData) state that writes that breaks out.When T4, this control line MC1 is driven to the logic high levle, represent that these drive end device 310 preparations finish this storer and write out the cycle, so 410 of this bus control units enter to extend and write data (EWData) state and produce controlling signal 411,412, so that the finishing touch data information of being transmitted on this address and the data bus 350 (DATA) is write in this storer 321.
Figure 13 is a block memory mapping readout interval sequential chart, when T3, this control line MC1 is driven to the logic high levle earlier than MC0, so it is readout interval that this bus control unit 410 can detect this, so 410 of this bus control units produce controlling signal 411,412, so that related data in this storer 321 is read out on this address and the data bus 350, so that setting-up time (setup time) and hold time (holdtime) when meeting this drive end device 310 and reading.When T3 ',,, 410 of this bus control units read data (BRData) state so entering outburst because this moment, this control line MC1 was driven to the logic low level once more.In T3 " time, because this moment, this control line MC1 was driven to the logic high levle once more, this moment, this drive end device 310 read the data on this address and the data bus 350, this bus control unit 410 also reenters data (BRData) state that reads that breaks out.When T4, this control line MC0 is driven to the logic high levle, represent that these drive end device 310 preparations finish this storer and read the cycle, so 410 of this bus control units enter to extend and read data (ERData) state and produce controlling signal 411,412, so that finishing touch data information (DATA) is read out on this address and the data bus 350 from this this storer 321.
Figure 14 is that a storer mapping is read/sequential chart write cycle (Read-Modify-Write), when T3, this control line MC1 is driven to the logic high levle earlier than MC0, so it is readout interval that this bus control unit 410 can detect this, 410 of this bus control units produce controlling signal 411,412, so that related data in this storer 321 is read out on this address and the data bus 350, so that setting-up time (setup time) and hold time (hold time) when meeting this drive end device 310 and reading.When T3 ',,, 410 of this bus control units read data (BRData) state so entering outburst because this moment, this control line MC1 was driven to the logic low level once more.In T3 " time, because this moment, this control line MC0 was driven to the logic high levle once more, this moment, this drive end device 310 read the data on this address and the data bus 350, and this bus control unit 410 enters the data of writing (WData) state.When T4, this control line MC1 is driven to the logic high levle, represent that these drive end device 310 preparations finish this storer and read in the cycle, so 410 of this bus control units produce controlling signal 411,412, so that the data information of being transmitted on this address and the data bus 350 (DATA) is write in this storer 321, read/write cycle to finish the storer mapping.
This output input mapping mapping block writes out, reads and read/write cycle sequential chart can no longer repeat to give unnecessary details at this by drawing easily among Fig. 7.In Figure 10 and Figure 11, this output input mapping mapping write out and the readout interval sequential chart in, the address number of output input mapping is 2
3NIf, but simplify the hardware design of this bus control unit 410, the address number that also can be designed to export the input mapping is 2
1NAgain, skilled person can use hardware description language (for example Verilog or VHD1) to finish the hardware design of this bus control unit 410 easily by the state transition diagram of Fig. 6 and Fig. 7.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (19)
1, a kind of reinforced extendible time-sharing bus framework, it is characterized in that, it is the data reading-writing that is used between a drive end device and at least one Partner device, this bus architecture mainly comprises a drive end bus interface and a Partner bus interface, wherein, this drive end interface is to reach at least two control lines with an address and data shared bus to be connected with this Partner bus interface, this address and data shared bus are to transmit address and data between this drive end device and this Partner device with timesharing, these at least two control lines then are that to be driven by this drive end device be accurate position of first logic or the accurate position of second logic, so that make this drive end device and this Partner device determine that according to the logical combination of this control line this address and data shared bus are in order to transmission storer address, output/input address, read data, write data, block reads data or block writes data.
2, reinforced extendible time-sharing bus framework according to claim 1 is characterized in that, wherein, this Partner bus interface has a storer address working storage, with when carrying out the memory data read-write, the storer address that read and write is locked.
3, reinforced extendible time-sharing bus framework according to claim 2, it is characterized in that, wherein, this Partner bus interface has more a data base working storage, it is the position of the data base that provided of this Partner device of record, to cooperate the content of this storer address working storage device, produce actual address by memory mapped.
4, reinforced extendible time-sharing bus framework according to claim 1, it is characterized in that wherein, this Partner bus interface has an output/input address working storage, with when exporting/input data when read-write, the output/input address that read and write is locked.
5, reinforced extendible time-sharing bus framework according to claim 2, it is characterized in that, wherein, this Partner bus interface has more an output/input working storage, it is the position of output/input of being provided of this Partner device of record, to cooperate the content of this output/input address working storage device, produce actual address by output/input mapping.
6, reinforced extendible time-sharing bus framework according to claim 3, it is characterized in that, wherein, this Partner bus interface has more identity identification working storage to write down the numbering at this Partner bus interface, use the numbering that the identity identification numbering sent when this drive end device and this Partner bus interface is write down when identical, this Partner bus interface is given activation.
According to claim 2,3,4,5 or 6 described reinforced extendible time-sharing bus frameworks, it is characterized in that 7, wherein, these at least two control lines are to comprise one first control line and one second control line.
8, reinforced extendible time-sharing bus framework according to claim 1 is characterized in that, wherein, when this first control line is the accurate position of first logic earlier than second control line, is the execute store access.
9, reinforced extendible time-sharing bus framework according to claim 8 is characterized in that, wherein, when this first control line is the accurate position of second logic earlier than second control line, is that execute store writes.
10, reinforced extendible time-sharing bus framework according to claim 9 is characterized in that, wherein, writes fashionablely when execute store, and when this second control line was the accurate position of second logic, this address and data shared bus write data in order to transmission.
11, reinforced extendible time-sharing bus framework according to claim 8 is characterized in that, wherein, when this second control line was the accurate position of second logic earlier than first control line, execute store was read.
12, reinforced extendible time-sharing bus framework according to claim 11 is characterized in that, wherein, when execute store was read, when this first control line was second logic standard position, this address and data shared bus were read data in order to transmission.
13, reinforced extendible time-sharing bus framework according to claim 1 is characterized in that, wherein, when this second control line is the accurate position of first logic earlier than first control line, carries out output/input access.
14, reinforced extendible time-sharing bus framework according to claim 13 is characterized in that, wherein, when this first control line is the accurate position of second logic earlier than second control line, carries out output/input and writes.
15, reinforced extendible time-sharing bus framework according to claim 14 is characterized in that, wherein, writes fashionablely when execute store, and when this second control line was the accurate position of second logic, this address and data shared bus write data in order to transmission.
16, reinforced extendible time-sharing bus framework according to claim 13 is characterized in that, wherein, when this second control line is the accurate position of second logic earlier than first control line, carries out output/input and reads.
17, reinforced extendible time-sharing bus framework according to claim 16 is characterized in that, wherein, when execute store was read, when this first control line was second logic standard position, this address and data shared bus were to read data in order to transmission.
18, reinforced extendible time-sharing bus framework according to claim 1 is characterized in that, wherein, this drive end device is a microprocessor, and this Partner device is a storer.
19, reinforced extendible time-sharing bus framework according to claim 1 is characterized in that, wherein, the accurate position of this first logic is the logic low level, and the accurate position of this second logic is the logic high levle.
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| CNB2004100446042A CN100354849C (en) | 2004-05-14 | 2004-05-14 | Enhancement type expandable time sharing bus architecture |
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| CNB2004100446042A CN100354849C (en) | 2004-05-14 | 2004-05-14 | Enhancement type expandable time sharing bus architecture |
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| CN110737610A (en) * | 2018-07-19 | 2020-01-31 | 新唐科技股份有限公司 | Signal interface system and data transmission method thereof |
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| FR2462745B1 (en) * | 1979-07-30 | 1986-01-03 | Jeumont Schneider | DEVICE FOR TEMPORAL SHARING OF ACCESS TO A MEMORY CONNECTED TO A SINGLE BUS BETWEEN A CENTRAL COMPUTER AND A PLURALITY OF PERIPHERAL COMPUTERS |
| JPH0338725A (en) * | 1989-07-05 | 1991-02-19 | Mitsubishi Electric Corp | Data processor and microprocessor |
| JP3075649B2 (en) * | 1993-02-01 | 2000-08-14 | 積水化学工業株式会社 | Time division multiplex communication system |
| US6016270A (en) * | 1998-03-06 | 2000-01-18 | Alliance Semiconductor Corporation | Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations |
| CN1128413C (en) * | 1999-12-13 | 2003-11-19 | 凌阳科技股份有限公司 | Extendible time-sharing bus structure |
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| CN110737610A (en) * | 2018-07-19 | 2020-01-31 | 新唐科技股份有限公司 | Signal interface system and data transmission method thereof |
| CN110737610B (en) * | 2018-07-19 | 2020-12-01 | 新唐科技股份有限公司 | Signal interface system and data transmission method thereof |
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